Index: gd32vf103xb.ld
===================================================================
--- gd32vf103xb.ld (nonexistent)
+++ gd32vf103xb.ld (revision 411)
@@ -0,0 +1,68 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY( reset_handler )
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+ .vector_table :
+ {
+ KEEP (*(SORT_NONE(.vector_table)))
+ } >FLASH
+
+ .text :
+ {
+ *(.rodata .rodata.*)
+ *(.srodata .srodata.*)
+ *(.text .text.*)
+ } >FLASH
+
+ . = ALIGN(4);
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ _sidata = .;
+ .data : AT( _sidata )
+ {
+ _sdata = .;
+ *(.rdata)
+ *(.data .data.*)
+ *(.sdata .sdata.*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM
+
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+ PROVIDE( _fbss = . );
+ PROVIDE( __bss_start = . );
+
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+
+ . = ALIGN(8);
+ PROVIDE( _end = . );
+ PROVIDE( end = . );
+
+ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >RAM
+}
Index: gd32vf103xb_boot.S
===================================================================
--- gd32vf103xb_boot.S (nonexistent)
+++ gd32vf103xb_boot.S (revision 411)
@@ -0,0 +1,277 @@
+
+#include <riscv_encoding.h>
+
+/*
+ Uncomment this line if you have only -march=rv32imac instead of -march=rv32imac_zicsr:
+.option arch, +zicsr
+ */
+
+/*
+ * Main vector table entries.
+ */
+.global vtable
+.type vtable, %object
+.section .vector_table,"a",%progbits
+vtable:
+ j reset_handler
+ .align 2
+ .word 0
+ .word 0
+ .word eclic_msip_handler
+ .word 0
+ .word 0
+ .word 0
+ .word eclic_mtip_handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word eclic_bwei_handler
+ .word eclic_pmovi_handler
+ .word watchdog_IRQn_handler
+ .word LVD_IRQn_handler
+ .word tamper_IRQn_handler
+ .word RTC_IRQn_handler
+ .word FMC_IRQn_handler
+ .word RCU_IRQn_handler
+ .word EXTI0_IRQn_handler
+ .word EXTI1_IRQn_handler
+ .word EXTI2_IRQn_handler
+ .word EXTI3_IRQn_handler
+ .word EXTI4_IRQn_handler
+ .word DMA0_chan0_IRQn_handler
+ .word DMA0_chan1_IRQn_handler
+ .word DMA0_chan2_IRQn_handler
+ .word DMA0_chan3_IRQn_handler
+ .word DMA0_chan4_IRQn_handler
+ .word DMA0_chan5_IRQn_handler
+ .word DMA0_chan6_IRQn_handler
+ .word ADC0_1_IRQn_handler
+ .word CAN0_TX_IRQn_handler
+ .word CAN0_RX0_IRQn_handler
+ .word CAN0_RX1_IRQn_handler
+ .word CAN0_EWMC_IRQn_handler
+ .word EXTI5_9_IRQn_handler
+ .word TIM0_break_IRQn_handler
+ .word TIM0_update_IRQn_handler
+ .word TIM0_trigger_commutation_IRQn_handler
+ .word TIM0_channel_IRQn_handler
+ .word TIM1_IRQn_handler
+ .word TIM2_IRQn_handler
+ .word TIM3_IRQn_handler
+ .word I2C0_EV_IRQn_handler
+ .word I2C0_ER_IRQn_handler
+ .word I2C1_EV_IRQn_handler
+ .word I2C1_ER_IRQn_handler
+ .word SPI0_IRQn_handler
+ .word SPI1_IRQn_handler
+ .word USART0_IRQn_handler
+ .word USART1_IRQn_handler
+ .word USART2_IRQn_handler
+ .word EXTI10_15_IRQn_handler
+ .word RTC_alarm_IRQn_handler
+ .word USB_wakeup_IRQn_handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXMC_IRQn_handler
+ .word 0
+ .word TIM4_IRQn_handler
+ .word SPI2_IRQn_handler
+ .word UART3_IRQn_handler
+ .word UART4_IRQn_handler
+ .word TIM5_IRQn_handler
+ .word TIM6_IRQn_handler
+ .word DMA1_chan0_IRQn_handler
+ .word DMA1_chan1_IRQn_handler
+ .word DMA1_chan2_IRQn_handler
+ .word DMA1_chan3_IRQn_handler
+ .word DMA1_chan4_IRQn_handler
+ .word 0
+ .word 0
+ .word CAN1_TX_IRQn_handler
+ .word CAN1_RX0_IRQn_handler
+ .word CAN1_RX1_IRQn_handler
+ .word CAN1_EWMC_IRQn_handler
+ .word USB_IRQn_handler
+
+ /*
+ * Weak aliases to point each exception hadnler to the
+ * 'default_interrupt_handler', unless the application defines
+ * a function with the same name to override the reference.
+ */
+ .weak eclic_msip_handler
+ .set eclic_msip_handler,default_interrupt_handler
+ .weak eclic_mtip_handler
+ .set eclic_mtip_handler,default_interrupt_handler
+ .weak eclic_bwei_handler
+ .set eclic_bwei_handler,default_interrupt_handler
+ .weak eclic_pmovi_handler
+ .set eclic_pmovi_handler,default_interrupt_handler
+ .weak watchdog_IRQn_handler
+ .set watchdog_IRQn_handler,default_interrupt_handler
+ .weak LVD_IRQn_handler
+ .set LVD_IRQn_handler,default_interrupt_handler
+ .weak tamper_IRQn_handler
+ .set tamper_IRQn_handler,default_interrupt_handler
+ .weak RTC_IRQn_handler
+ .set RTC_IRQn_handler,default_interrupt_handler
+ .weak FMC_IRQn_handler
+ .set FMC_IRQn_handler,default_interrupt_handler
+ .weak RCU_IRQn_handler
+ .set RCU_IRQn_handler,default_interrupt_handler
+ .weak EXTI0_IRQn_handler
+ .set EXTI0_IRQn_handler,default_interrupt_handler
+ .weak EXTI1_IRQn_handler
+ .set EXTI1_IRQn_handler,default_interrupt_handler
+ .weak EXTI2_IRQn_handler
+ .set EXTI2_IRQn_handler,default_interrupt_handler
+ .weak EXTI3_IRQn_handler
+ .set EXTI3_IRQn_handler,default_interrupt_handler
+ .weak EXTI4_IRQn_handler
+ .set EXTI4_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan0_IRQn_handler
+ .set DMA0_chan0_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan1_IRQn_handler
+ .set DMA0_chan1_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan2_IRQn_handler
+ .set DMA0_chan2_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan3_IRQn_handler
+ .set DMA0_chan3_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan4_IRQn_handler
+ .set DMA0_chan4_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan5_IRQn_handler
+ .set DMA0_chan5_IRQn_handler,default_interrupt_handler
+ .weak DMA0_chan6_IRQn_handler
+ .set DMA0_chan6_IRQn_handler,default_interrupt_handler
+ .weak ADC0_1_IRQn_handler
+ .set ADC0_1_IRQn_handler,default_interrupt_handler
+ .weak CAN0_TX_IRQn_handler
+ .set CAN0_TX_IRQn_handler,default_interrupt_handler
+ .weak CAN0_RX0_IRQn_handler
+ .set CAN0_RX0_IRQn_handler,default_interrupt_handler
+ .weak CAN0_RX1_IRQn_handler
+ .set CAN0_RX1_IRQn_handler,default_interrupt_handler
+ .weak CAN0_EWMC_IRQn_handler
+ .set CAN0_EWMC_IRQn_handler,default_interrupt_handler
+ .weak EXTI5_9_IRQn_handler
+ .set EXTI5_9_IRQn_handler,default_interrupt_handler
+ .weak TIM0_break_IRQn_handler
+ .set TIM0_break_IRQn_handler,default_interrupt_handler
+ .weak TIM0_update_IRQn_handler
+ .set TIM0_update_IRQn_handler,default_interrupt_handler
+ .weak TIM0_trigger_commutation_IRQn_handler
+ .set TIM0_trigger_commutation_IRQn_handler,default_interrupt_handler
+ .weak TIM0_channel_IRQn_handler
+ .set TIM0_channel_IRQn_handler,default_interrupt_handler
+ .weak TIM1_IRQn_handler
+ .set TIM1_IRQn_handler,default_interrupt_handler
+ .weak TIM2_IRQn_handler
+ .set TIM2_IRQn_handler,default_interrupt_handler
+ .weak TIM3_IRQn_handler
+ .set TIM3_IRQn_handler,default_interrupt_handler
+ .weak I2C0_EV_IRQn_handler
+ .set I2C0_EV_IRQn_handler,default_interrupt_handler
+ .weak I2C0_ER_IRQn_handler
+ .set I2C0_ER_IRQn_handler,default_interrupt_handler
+ .weak I2C1_EV_IRQn_handler
+ .set I2C1_EV_IRQn_handler,default_interrupt_handler
+ .weak I2C1_ER_IRQn_handler
+ .set I2C1_ER_IRQn_handler,default_interrupt_handler
+ .weak SPI0_IRQn_handler
+ .set SPI0_IRQn_handler,default_interrupt_handler
+ .weak SPI1_IRQn_handler
+ .set SPI1_IRQn_handler,default_interrupt_handler
+ .weak USART0_IRQn_handler
+ .set USART0_IRQn_handler,default_interrupt_handler
+ .weak USART1_IRQn_handler
+ .set USART1_IRQn_handler,default_interrupt_handler
+ .weak USART2_IRQn_handler
+ .set USART2_IRQn_handler,default_interrupt_handler
+ .weak EXTI10_15_IRQn_handler
+ .set EXTI10_15_IRQn_handler,default_interrupt_handler
+ .weak RTC_alarm_IRQn_handler
+ .set RTC_alarm_IRQn_handler,default_interrupt_handler
+ .weak USB_wakeup_IRQn_handler
+ .set USB_wakeup_IRQn_handler,default_interrupt_handler
+ .weak EXMC_IRQn_handler
+ .set EXMC_IRQn_handler,default_interrupt_handler
+ .weak TIM4_IRQn_handler
+ .set TIM4_IRQn_handler,default_interrupt_handler
+ .weak SPI2_IRQn_handler
+ .set SPI2_IRQn_handler,default_interrupt_handler
+ .weak UART3_IRQn_handler
+ .set UART3_IRQn_handler,default_interrupt_handler
+ .weak UART4_IRQn_handler
+ .set UART4_IRQn_handler,default_interrupt_handler
+ .weak TIM5_IRQn_handler
+ .set TIM5_IRQn_handler,default_interrupt_handler
+ .weak TIM6_IRQn_handler
+ .set TIM6_IRQn_handler,default_interrupt_handler
+ .weak DMA1_chan0_IRQn_handler
+ .set DMA1_chan0_IRQn_handler,default_interrupt_handler
+ .weak DMA1_chan1_IRQn_handler
+ .set DMA1_chan1_IRQn_handler,default_interrupt_handler
+ .weak DMA1_chan2_IRQn_handler
+ .set DMA1_chan2_IRQn_handler,default_interrupt_handler
+ .weak DMA1_chan3_IRQn_handler
+ .set DMA1_chan3_IRQn_handler,default_interrupt_handler
+ .weak DMA1_chan4_IRQn_handler
+ .set DMA1_chan4_IRQn_handler,default_interrupt_handler
+ .weak CAN1_TX_IRQn_handler
+ .set CAN1_TX_IRQn_handler,default_interrupt_handler
+ .weak CAN1_RX0_IRQn_handler
+ .set CAN1_RX0_IRQn_handler,default_interrupt_handler
+ .weak CAN1_RX1_IRQn_handler
+ .set CAN1_RX1_IRQn_handler,default_interrupt_handler
+ .weak CAN1_EWMC_IRQn_handler
+ .set CAN1_EWMC_IRQn_handler,default_interrupt_handler
+ .weak USB_IRQn_handler
+ .set USB_IRQn_handler,default_interrupt_handler
+
+/*
+ * A 'default' interrupt handler, in case an interrupt triggers
+ * without a handler being defined.
+ */
+.section .text.default_interrupt_handler,"ax",%progbits
+default_interrupt_handler:
+ default_interrupt_loop:
+ j default_interrupt_loop
+
+/*
+ * Assembly 'reset handler' function to initialize core CPU registers.
+ */
+.global reset_handler
+.type reset_handler,@function
+reset_handler:
+ // Disable interrupts until they are needed.
+ csrc CSR_MSTATUS, MSTATUS_MIE
+ // Move from 0x00000000 to 0x08000000 address space if necessary.
+ la a0, in_address_space
+ li a1, 1
+ slli a1, a1, 27
+ bleu a1, a0, in_address_space
+ add a0, a0, a1
+ jr a0
+ in_address_space:
+ // Load the initial stack pointer value.
+ la sp, _sp
+ // Set the vector table's base address.
+ la a0, vtable
+ csrw CSR_MTVT, a0
+ // Set non-vectored interrupts to use the default handler.
+ // (That will gracefully crash the program,
+ // so only use vectored interrupts for now.)
+ la a0, default_interrupt_handler
+ csrw CSR_MTVEC, a0
+ // Call 'main(0,0)' (.data/.bss sections initialized there)
+ li a0, 0
+ li a1, 0
+ call main
Index: include/gd32vf103.h
===================================================================
--- include/gd32vf103.h (nonexistent)
+++ include/gd32vf103.h (revision 411)
@@ -0,0 +1,560 @@
+
+#ifndef GD32VF103xB
+#define GD32VF103xB
+/*
+ * GD32VF103CB device header file.
+ * Written to be as compatible as possible with STM32F1 code.
+ * These definitions are incomplete and application-specific.
+ */
+#include <stdint.h>
+
+/**
+ * Compatibility definitions and RISC-V specific values.
+ */
+extern volatile uint32_t SystemCoreClock;
+
+/**
+ * Interrupt handler enumeration.
+ */
+typedef enum IRQn {
+ CLIC_INT_RESERVED = 0,
+ CLIC_INT_SFT = 3,
+ CLIC_INT_TMR = 7,
+ CLIC_INT_BWEI = 17,
+ CLIC_INT_PMOVI = 18,
+ WWDG_IRQn = 19,
+ PVD_IRQn = 20,
+ TAMPER_IRQn = 21,
+ RTC_IRQn = 22,
+ FLASH_IRQn = 23,
+ RCC_IRQn = 24,
+ EXTI0_IRQn = 25,
+ EXTI1_IRQn = 26,
+ EXTI2_IRQn = 27,
+ EXTI3_IRQn = 28,
+ EXTI4_IRQn = 29,
+ DMA1_Channel1_IRQn = 30,
+ DMA1_Channel2_IRQn = 31,
+ DMA1_Channel3_IRQn = 32,
+ DMA1_Channel4_IRQn = 33,
+ DMA1_Channel5_IRQn = 34,
+ DMA1_Channel6_IRQn = 35,
+ DMA1_Channel7_IRQn = 36,
+ ADC1_2_IRQn = 37,
+ /*
+ These two interrupts aren't connected to the USB peripheral
+ on GD32 chips, but names are maintained for STM32F1 compatibility.
+ */
+ USB_HP_CAN1_TX_IRQn = 38,
+ CAN1_TX_IRQn = 38,
+ USB_LP_CAN1_RX0_IRQn = 39,
+ CAN1_RX0_IRQn = 39,
+ CAN1_RX1_IRQn = 40,
+ CAN1_SCE_IRQn = 41,
+ EXTI9_5_IRQn = 42,
+ TIM1_BRK_IRQn = 43,
+ TIM1_UP_IRQn = 44,
+ TIM1_TRG_COM_IRQn = 45,
+ TIM1_CC_IRQn = 46,
+ TIM2_IRQn = 47,
+ TIM3_IRQn = 48,
+ TIM4_IRQn = 49,
+ I2C1_EV_IRQn = 50,
+ I2C1_ER_IRQn = 51,
+ I2C2_EV_IRQn = 52,
+ I2C2_ER_IRQn = 53,
+ SPI1_IRQn = 54,
+ SPI2_IRQn = 55,
+ USART1_IRQn = 56,
+ USART2_IRQn = 57,
+ USART3_IRQn = 58,
+ EXTI15_10_IRQn = 59,
+ RTC_Alarm_IRQn = 60,
+ USBWakeUp_IRQn = 61,
+ /*
+ Extra interrupts not available on STM32F1 chips:
+ (Numbered peripherals are still 1-indexed)
+ */
+ EXMC_IRQn = 67,
+ TIM5_IRQn = 69,
+ SPI3_IRQn = 70,
+ UART4_IRQn = 71,
+ UART5_IRQn = 72,
+ TIM6_IRQn = 73,
+ TIM7_IRQn = 74,
+ DMA2_Channel1_IRQn = 75,
+ DMA2_Channel2_IRQn = 76,
+ DMA2_Channel3_IRQn = 77,
+ DMA2_Channel4_IRQn = 78,
+ DMA2_Channel5_IRQn = 79,
+ CAN2_TX_IRQn = 82,
+ CAN2_RX0_IRQn = 83,
+ CAN2_RX1_IRQn = 84,
+ CAN2_SCE_IRQn = 85,
+ USBFS_IRQn = 86,
+ ECLIC_NUM_INTERRUPTS
+} IRQn_Type;
+
+/**
+ * RCC / RCU peripheral struct.
+ */
+typedef struct
+{
+ volatile uint32_t CR;
+ volatile uint32_t CFGR;
+ volatile uint32_t CIR;
+ volatile uint32_t APB2RSTR;
+ volatile uint32_t APB1RSTR;
+ volatile uint32_t AHBENR;
+ volatile uint32_t APB2ENR;
+ volatile uint32_t APB1ENR;
+ volatile uint32_t BDCR;
+ /* The following registers differ from STM32F1: */
+ volatile uint32_t RSTSCK;
+ volatile uint32_t AHBRSTR;
+ volatile uint32_t CFGR1;
+ volatile uint32_t DSV;
+} RCC_TypeDef;
+
+/**
+ * GPIO peripheral struct.
+ */
+typedef struct
+{
+ volatile uint32_t CRL;
+ volatile uint32_t CRH;
+ volatile uint32_t IDR;
+ volatile uint32_t ODR;
+ volatile uint32_t BSRR;
+ volatile uint32_t BRR;
+ volatile uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * AFIO peripheral struct.
+ */
+typedef struct
+{
+ volatile uint32_t EVCR;
+ volatile uint32_t MAPR;
+ volatile uint32_t EXTICR[ 4 ];
+ uint32_t RESERVED0;
+ volatile uint32_t MAPR2;
+} AFIO_TypeDef;
+
+/**
+ * DMA peripheral struct (global).
+ */
+typedef struct
+{
+ volatile uint32_t ISR;
+ volatile uint32_t IFCR;
+} DMA_TypeDef;
+
+/**
+ * DMA peripheral struct (per-channel).
+ */
+typedef struct
+{
+ volatile uint32_t CCR;
+ volatile uint32_t CNDTR;
+ volatile uint32_t CPAR;
+ volatile uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+/**
+ * SPI peripheral struct.
+ */
+typedef struct
+{
+ volatile uint32_t CR1;
+ volatile uint32_t CR2;
+ volatile uint32_t SR;
+ volatile uint32_t DR;
+ volatile uint32_t CRCPR;
+ volatile uint32_t RXCRCR;
+ volatile uint32_t TXCRCR;
+ volatile uint32_t I2SCFGR;
+ volatile uint32_t I2SPR;
+} SPI_TypeDef;
+
+/* Global register block address definitions. */
+#define RCC ( ( RCC_TypeDef * ) 0x40021000 )
+#define GPIOA ( ( GPIO_TypeDef * ) 0x40010800 )
+#define GPIOB ( ( GPIO_TypeDef * ) 0x40010C00 )
+#define GPIOC ( ( GPIO_TypeDef * ) 0x40011000 )
+#define GPIOD ( ( GPIO_TypeDef * ) 0x40011400 )
+#define GPIOE ( ( GPIO_TypeDef * ) 0x40011800 )
+#define AFIO ( ( AFIO_TypeDef * ) 0x40010000 )
+#define DMA1 ( ( DMA_TypeDef * ) 0x40020000 )
+#define DMA2 ( ( DMA_TypeDef * ) 0x40020400 )
+#define DMA1_Channel1 ( ( DMA_Channel_TypeDef * ) 0x40020008 )
+#define DMA1_Channel2 ( ( DMA_Channel_TypeDef * ) 0x4002001C )
+#define DMA1_Channel3 ( ( DMA_Channel_TypeDef * ) 0x40020030 )
+#define DMA1_Channel4 ( ( DMA_Channel_TypeDef * ) 0x40020044 )
+#define DMA1_Channel5 ( ( DMA_Channel_TypeDef * ) 0x40020058 )
+#define DMA1_Channel6 ( ( DMA_Channel_TypeDef * ) 0x4002006C )
+#define DMA1_Channel7 ( ( DMA_Channel_TypeDef * ) 0x40020080 )
+#define DMA2_Channel1 ( ( DMA_Channel_TypeDef * ) 0x40020408 )
+#define DMA2_Channel2 ( ( DMA_Channel_TypeDef * ) 0x4002041C )
+#define DMA2_Channel3 ( ( DMA_Channel_TypeDef * ) 0x40020430 )
+#define DMA2_Channel4 ( ( DMA_Channel_TypeDef * ) 0x40020444 )
+#define DMA2_Channel5 ( ( DMA_Channel_TypeDef * ) 0x40020458 )
+#define SPI1 ( ( SPI_TypeDef * ) 0x40013000 )
+#define SPI2 ( ( SPI_TypeDef * ) 0x40003800 )
+#define SPI3 ( ( SPI_TypeDef * ) 0x40003C00 )
+
+/* RCC register bit definitions. */
+/* APB2RSTR */
+#define RCC_APB2RSTR_AFIORST_Pos ( 0U )
+#define RCC_APB2RSTR_AFIORST_Msk ( 0x1UL << RCC_APB2RSTR_AFIORST_Pos )
+#define RCC_APB2RSTR_AFIORST ( RCC_APB2RSTR_AFIORST_Msk )
+#define RCC_APB2RSTR_IOPARST_Pos ( 2U )
+#define RCC_APB2RSTR_IOPARST_Msk ( 0x1UL << RCC_APB2RSTR_IOPARST_Pos )
+#define RCC_APB2RSTR_IOPARST ( RCC_APB2RSTR_IOPARST_Msk )
+#define RCC_APB2RSTR_IOPBRST_Pos ( 3U )
+#define RCC_APB2RSTR_IOPBRST_Msk ( 0x1UL << RCC_APB2RSTR_IOPBRST_Pos )
+#define RCC_APB2RSTR_IOPBRST ( RCC_APB2RSTR_IOPBRST_Msk )
+#define RCC_APB2RSTR_IOPCRST_Pos ( 4U )
+#define RCC_APB2RSTR_IOPCRST_Msk ( 0x1UL << RCC_APB2RSTR_IOPCRST_Pos )
+#define RCC_APB2RSTR_IOPCRST ( RCC_APB2RSTR_IOPCRST_Msk )
+#define RCC_APB2RSTR_IOPDRST_Pos ( 5U )
+#define RCC_APB2RSTR_IOPDRST_Msk ( 0x1UL << RCC_APB2RSTR_IOPDRST_Pos )
+#define RCC_APB2RSTR_IOPDRST ( RCC_APB2RSTR_IOPDRST_Msk )
+#define RCC_APB2RSTR_IOPERST_Pos ( 6U )
+#define RCC_APB2RSTR_IOPERST_Msk ( 0x1UL << RCC_APB2RSTR_IOPERST_Pos )
+#define RCC_APB2RSTR_IOPERST ( RCC_APB2RSTR_IOPERST_Msk )
+#define RCC_APB2RSTR_ADC1RST_Pos ( 9U )
+#define RCC_APB2RSTR_ADC1RST_Msk ( 0x1UL << RCC_APB2RSTR_ADC1RST_Pos )
+#define RCC_APB2RSTR_ADC1RST ( RCC_APB2RSTR_ADC1RST_Msk )
+#define RCC_APB2RSTR_ADC2RST_Pos ( 10U )
+#define RCC_APB2RSTR_ADC2RST_Msk ( 0x1UL << RCC_APB2RSTR_ADC2RST_Pos )
+#define RCC_APB2RSTR_ADC2RST ( RCC_APB2RSTR_ADC2RST_Msk )
+#define RCC_APB2RSTR_TIM1RST_Pos ( 11U )
+#define RCC_APB2RSTR_TIM1RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM1RST_Pos )
+#define RCC_APB2RSTR_TIM1RST ( RCC_APB2RSTR_TIM1RST_Msk )
+#define RCC_APB2RSTR_SPI1RST_Pos ( 12U )
+#define RCC_APB2RSTR_SPI1RST_Msk ( 0x1UL << RCC_APB2RSTR_SPI1RST_Pos )
+#define RCC_APB2RSTR_SPI1RST ( RCC_APB2RSTR_SPI1RST_Msk )
+#define RCC_APB2RSTR_USART1RST_Pos ( 14U )
+#define RCC_APB2RSTR_USART1RST_Msk ( 0x1UL << RCC_APB2RSTR_USART1RST_Pos )
+#define RCC_APB2RSTR_USART1RST ( RCC_APB2RSTR_USART1RST_Msk )
+/* AHBENR */
+#define RCC_AHBENR_DMA1EN_Pos ( 0U )
+#define RCC_AHBENR_DMA1EN_Msk ( 0x1UL << RCC_AHBENR_DMA1EN_Pos )
+#define RCC_AHBENR_DMA1EN ( RCC_AHBENR_DMA1EN_Msk )
+/* Note: DMA2 not present on STM32F103 chips */
+#define RCC_AHBENR_DMA2EN_Pos ( 1U )
+#define RCC_AHBENR_DMA2EN_Msk ( 0x1UL << RCC_AHBENR_DMA2EN_Pos )
+#define RCC_AHBENR_DMA2EN ( RCC_AHBENR_DMA2EN_Msk )
+#define RCC_AHBENR_SRAMEN_Pos ( 2U )
+#define RCC_AHBENR_SRAMEN_Msk ( 0x1UL << RCC_AHBENR_SRAMEN_Pos )
+#define RCC_AHBENR_SRAMEN ( RCC_AHBENR_SRAMEN_Msk )
+#define RCC_AHBENR_FLITFEN_Pos ( 4U )
+#define RCC_AHBENR_FLITFEN_Msk ( 0x1UL << RCC_AHBENR_FLITFEN_Pos )
+#define RCC_AHBENR_FLITFEN ( RCC_AHBENR_FLITFEN_Msk )
+#define RCC_AHBENR_CRCEN_Pos ( 6U )
+#define RCC_AHBENR_CRCEN_Msk ( 0x1UL << RCC_AHBENR_CRCENEN_Pos )
+#define RCC_AHBENR_CRCEN ( RCC_AHBENR_CRCENEN_Msk )
+/* Note: EXMC not present on STM32F103 chips */
+#define RCC_AHBENR_EXMCEN_Pos ( 8U )
+#define RCC_AHBENR_EXMCEN_Msk ( 0x1UL << RCC_AHBENR_EXMCEN_Pos )
+#define RCC_AHBENR_EXMCEN ( RCC_AHBENR_EXMCEN_Msk )
+/* Note: USB handled differently on STM32F103 chips */
+#define RCC_AHBENR_USBFSEN_Pos ( 12U )
+#define RCC_AHBENR_USBFSEN_Msk ( 0x1UL << RCC_AHBENR_USBFSEN_Pos )
+#define RCC_AHBENR_USBFSEN ( RCC_AHBENR_USBFSEN_Msk )
+/* APB2ENR */
+#define RCC_APB2ENR_AFIOEN_Pos ( 0U )
+#define RCC_APB2ENR_AFIOEN_Msk ( 0x1UL << RCC_APB2ENR_AFIOEN_Pos )
+#define RCC_APB2ENR_AFIOEN ( RCC_APB2ENR_AFIOEN_Msk )
+#define RCC_APB2ENR_IOPAEN_Pos ( 2U )
+#define RCC_APB2ENR_IOPAEN_Msk ( 0x1UL << RCC_APB2ENR_IOPAEN_Pos )
+#define RCC_APB2ENR_IOPAEN ( RCC_APB2ENR_IOPAEN_Msk )
+#define RCC_APB2ENR_IOPBEN_Pos ( 3U )
+#define RCC_APB2ENR_IOPBEN_Msk ( 0x1UL << RCC_APB2ENR_IOPBEN_Pos )
+#define RCC_APB2ENR_IOPBEN ( RCC_APB2ENR_IOPBEN_Msk )
+#define RCC_APB2ENR_IOPCEN_Pos ( 4U )
+#define RCC_APB2ENR_IOPCEN_Msk ( 0x1UL << RCC_APB2ENR_IOPCEN_Pos )
+#define RCC_APB2ENR_IOPCEN ( RCC_APB2ENR_IOPCEN_Msk )
+#define RCC_APB2ENR_IOPDEN_Pos ( 5U )
+#define RCC_APB2ENR_IOPDEN_Msk ( 0x1UL << RCC_APB2ENR_IOPDEN_Pos )
+#define RCC_APB2ENR_IOPDEN ( RCC_APB2ENR_IOPDEN_Msk )
+#define RCC_APB2ENR_IOPEEN_Pos ( 6U )
+#define RCC_APB2ENR_IOPEEN_Msk ( 0x1UL << RCC_APB2ENR_IOPEEN_Pos )
+#define RCC_APB2ENR_IOPEEN ( RCC_APB2ENR_IOPEEN_Msk )
+#define RCC_APB2ENR_ADC1EN_Pos ( 9U )
+#define RCC_APB2ENR_ADC1EN_Msk ( 0x1UL << RCC_APB2ENR_ADC1EN_Pos )
+#define RCC_APB2ENR_ADC1EN ( RCC_APB2ENR_ADC1EN_Msk )
+#define RCC_APB2ENR_ADC2EN_Pos ( 10U )
+#define RCC_APB2ENR_ADC2EN_Msk ( 0x1UL << RCC_APB2ENR_ADC2EN_Pos )
+#define RCC_APB2ENR_ADC2EN ( RCC_APB2ENR_ADC2EN_Msk )
+#define RCC_APB2ENR_TIM1EN_Pos ( 11U )
+#define RCC_APB2ENR_TIM1EN_Msk ( 0x1UL << RCC_APB2ENR_TIM1EN_Pos )
+#define RCC_APB2ENR_TIM1EN ( RCC_APB2ENR_TIM1EN_Msk )
+#define RCC_APB2ENR_SPI1EN_Pos ( 12U )
+#define RCC_APB2ENR_SPI1EN_Msk ( 0x1UL << RCC_APB2ENR_SPI1EN_Pos )
+#define RCC_APB2ENR_SPI1EN ( RCC_APB2ENR_SPI1EN_Msk )
+#define RCC_APB2ENR_USART1EN_Pos ( 14U )
+#define RCC_APB2ENR_USART1EN_Msk ( 0x1UL << RCC_APB2ENR_USART1EN_Pos )
+#define RCC_APB2ENR_USART1EN ( RCC_APB2ENR_USART1EN_Msk )
+
+/* AFIO register bit definitions. */
+
+/* GPIO register bit definitions. */
+/* CRL */
+#define GPIO_CRL_MODE_Pos ( 0U )
+#define GPIO_CRL_MODE_Msk ( 0x33333333UL << GPIO_CRL_MODE_Pos )
+#define GPIO_CRL_MODE ( GPIO_CRL_MODE_Msk )
+#define GPIO_CRL_MODE0_Pos ( 0U )
+#define GPIO_CRL_MODE0_Msk ( 0x3UL << GPIO_CRL_MODE0_Pos )
+#define GPIO_CRL_MODE0 ( GPIO_CRL_MODE0_Msk )
+#define GPIO_CRL_MODE1_Pos ( 4U )
+#define GPIO_CRL_MODE1_Msk ( 0x3UL << GPIO_CRL_MODE1_Pos )
+#define GPIO_CRL_MODE1 ( GPIO_CRL_MODE1_Msk )
+#define GPIO_CRL_MODE2_Pos ( 8U )
+#define GPIO_CRL_MODE2_Msk ( 0x3UL << GPIO_CRL_MODE2_Pos )
+#define GPIO_CRL_MODE2 ( GPIO_CRL_MODE2_Msk )
+#define GPIO_CRL_MODE3_Pos ( 12U )
+#define GPIO_CRL_MODE3_Msk ( 0x3UL << GPIO_CRL_MODE3_Pos )
+#define GPIO_CRL_MODE3 ( GPIO_CRL_MODE3_Msk )
+#define GPIO_CRL_MODE4_Pos ( 16U )
+#define GPIO_CRL_MODE4_Msk ( 0x3UL << GPIO_CRL_MODE4_Pos )
+#define GPIO_CRL_MODE4 ( GPIO_CRL_MODE4_Msk )
+#define GPIO_CRL_MODE5_Pos ( 20U )
+#define GPIO_CRL_MODE5_Msk ( 0x3UL << GPIO_CRL_MODE5_Pos )
+#define GPIO_CRL_MODE5 ( GPIO_CRL_MODE5_Msk )
+#define GPIO_CRL_MODE6_Pos ( 24U )
+#define GPIO_CRL_MODE6_Msk ( 0x3UL << GPIO_CRL_MODE6_Pos )
+#define GPIO_CRL_MODE6 ( GPIO_CRL_MODE6_Msk )
+#define GPIO_CRL_MODE7_Pos ( 28U )
+#define GPIO_CRL_MODE7_Msk ( 0x3UL << GPIO_CRL_MODE7_Pos )
+#define GPIO_CRL_MODE7 ( GPIO_CRL_MODE7_Msk )
+#define GPIO_CRL_CNF_Pos ( 2U )
+#define GPIO_CRL_CNF_Msk ( 0x33333333UL << GPIO_CRL_CNF_Pos )
+#define GPIO_CRL_CNF ( GPIO_CRL_CNF_Msk )
+#define GPIO_CRL_CNF0_Pos ( 2U )
+#define GPIO_CRL_CNF0_Msk ( 0x3UL << GPIO_CRL_CNF0_Pos )
+#define GPIO_CRL_CNF0 ( GPIO_CRL_CNF0_Msk )
+#define GPIO_CRL_CNF1_Pos ( 6U )
+#define GPIO_CRL_CNF1_Msk ( 0x3UL << GPIO_CRL_CNF1_Pos )
+#define GPIO_CRL_CNF1 ( GPIO_CRL_CNF1_Msk )
+#define GPIO_CRL_CNF2_Pos ( 10U )
+#define GPIO_CRL_CNF2_Msk ( 0x3UL << GPIO_CRL_CNF2_Pos )
+#define GPIO_CRL_CNF2 ( GPIO_CRL_CNF2_Msk )
+#define GPIO_CRL_CNF3_Pos ( 14U )
+#define GPIO_CRL_CNF3_Msk ( 0x3UL << GPIO_CRL_CNF3_Pos )
+#define GPIO_CRL_CNF3 ( GPIO_CRL_CNF3_Msk )
+#define GPIO_CRL_CNF4_Pos ( 18U )
+#define GPIO_CRL_CNF4_Msk ( 0x3UL << GPIO_CRL_CNF4_Pos )
+#define GPIO_CRL_CNF4 ( GPIO_CRL_CNF4_Msk )
+#define GPIO_CRL_CNF5_Pos ( 22U )
+#define GPIO_CRL_CNF5_Msk ( 0x3UL << GPIO_CRL_CNF5_Pos )
+#define GPIO_CRL_CNF5 ( GPIO_CRL_CNF5_Msk )
+#define GPIO_CRL_CNF6_Pos ( 26U )
+#define GPIO_CRL_CNF6_Msk ( 0x3UL << GPIO_CRL_CNF6_Pos )
+#define GPIO_CRL_CNF6 ( GPIO_CRL_CNF6_Msk )
+#define GPIO_CRL_CNF7_Pos ( 30U )
+#define GPIO_CRL_CNF7_Msk ( 0x3UL << GPIO_CRL_CNF7_Pos )
+#define GPIO_CRL_CNF7 ( GPIO_CRL_CNF7_Msk )
+/* CRH */
+#define GPIO_CRH_MODE_Pos ( 0U )
+#define GPIO_CRH_MODE_Msk ( 0x33333333UL << GPIO_CRH_MODE_Pos )
+#define GPIO_CRH_MODE ( GPIO_CRH_MODE_Msk )
+#define GPIO_CRH_MODE8_Pos ( 0U )
+#define GPIO_CRH_MODE8_Msk ( 0x3UL << GPIO_CRH_MODE8_Pos )
+#define GPIO_CRH_MODE8 ( GPIO_CRH_MODE8_Msk )
+#define GPIO_CRH_MODE9_Pos ( 4U )
+#define GPIO_CRH_MODE9_Msk ( 0x3UL << GPIO_CRH_MODE9_Pos )
+#define GPIO_CRH_MODE9 ( GPIO_CRH_MODE9_Msk )
+#define GPIO_CRH_MODE10_Pos ( 8U )
+#define GPIO_CRH_MODE10_Msk ( 0x3UL << GPIO_CRH_MODE10_Pos )
+#define GPIO_CRH_MODE10 ( GPIO_CRH_MODE10_Msk )
+#define GPIO_CRH_MODE11_Pos ( 12U )
+#define GPIO_CRH_MODE11_Msk ( 0x11UL << GPIO_CRH_MODE11_Pos )
+#define GPIO_CRH_MODE11 ( GPIO_CRH_MODE11_Msk )
+#define GPIO_CRH_MODE12_Pos ( 16U )
+#define GPIO_CRH_MODE12_Msk ( 0x3UL << GPIO_CRH_MODE12_Pos )
+#define GPIO_CRH_MODE12 ( GPIO_CRH_MODE12_Msk )
+#define GPIO_CRH_MODE13_Pos ( 20U )
+#define GPIO_CRH_MODE13_Msk ( 0x3UL << GPIO_CRH_MODE13_Pos )
+#define GPIO_CRH_MODE13 ( GPIO_CRH_MODE13_Msk )
+#define GPIO_CRH_MODE14_Pos ( 24U )
+#define GPIO_CRH_MODE14_Msk ( 0x3UL << GPIO_CRH_MODE14_Pos )
+#define GPIO_CRH_MODE14 ( GPIO_CRH_MODE14_Msk )
+#define GPIO_CRH_MODE15_Pos ( 28U )
+#define GPIO_CRH_MODE15_Msk ( 0x3UL << GPIO_CRH_MODE15_Pos )
+#define GPIO_CRH_MODE15 ( GPIO_CRH_MODE15_Msk )
+#define GPIO_CRH_CNF_Pos ( 2U )
+#define GPIO_CRH_CNF_Msk ( 0x33333333UL << GPIO_CRH_CNF_Pos )
+#define GPIO_CRH_CNF ( GPIO_CRH_CNF_Msk )
+#define GPIO_CRH_CNF8_Pos ( 2U )
+#define GPIO_CRH_CNF8_Msk ( 0x3UL << GPIO_CRH_CNF8_Pos )
+#define GPIO_CRH_CNF8 ( GPIO_CRH_CNF8_Msk )
+#define GPIO_CRH_CNF9_Pos ( 6U )
+#define GPIO_CRH_CNF9_Msk ( 0x3UL << GPIO_CRH_CNF9_Pos )
+#define GPIO_CRH_CNF9 ( GPIO_CRH_CNF9_Msk )
+#define GPIO_CRH_CNF10_Pos ( 10U )
+#define GPIO_CRH_CNF10_Msk ( 0x3UL << GPIO_CRH_CNF10_Pos )
+#define GPIO_CRH_CNF10 ( GPIO_CRH_CNF10_Msk )
+#define GPIO_CRH_CNF11_Pos ( 14U )
+#define GPIO_CRH_CNF11_Msk ( 0x11UL << GPIO_CRH_CNF11_Pos )
+#define GPIO_CRH_CNF11 ( GPIO_CRH_CNF11_Msk )
+#define GPIO_CRH_CNF12_Pos ( 18U )
+#define GPIO_CRH_CNF12_Msk ( 0x3UL << GPIO_CRH_CNF12_Pos )
+#define GPIO_CRH_CNF12 ( GPIO_CRH_CNF12_Msk )
+#define GPIO_CRH_CNF13_Pos ( 22U )
+#define GPIO_CRH_CNF13_Msk ( 0x3UL << GPIO_CRH_CNF13_Pos )
+#define GPIO_CRH_CNF13 ( GPIO_CRH_CNF13_Msk )
+#define GPIO_CRH_CNF14_Pos ( 214U )
+#define GPIO_CRH_CNF14_Msk ( 0x3UL << GPIO_CRH_CNF14_Pos )
+#define GPIO_CRH_CNF14 ( GPIO_CRH_CNF14_Msk )
+#define GPIO_CRH_CNF15_Pos ( 30U )
+#define GPIO_CRH_CNF15_Msk ( 0x3UL << GPIO_CRH_CNF15_Pos )
+#define GPIO_CRH_CNF15 ( GPIO_CRH_CNF15_Msk )
+
+/* Global DMA register bit definitions. */
+
+/* Per-channel DMA register bit definitions. */
+/* CCR / CHCTL */
+#define DMA_CCR_EN_Pos ( 0U )
+#define DMA_CCR_EN_Msk ( 0x1UL << DMA_CCR_EN_Pos )
+#define DMA_CCR_EN ( DMA_CCR_EN_Msk )
+#define DMA_CCR_TCIE_Pos ( 1U )
+#define DMA_CCR_TCIE_Msk ( 0x1UL << DMA_CCR_TCIE_Pos )
+#define DMA_CCR_TCIE ( DMA_CCR_TCIE_Msk )
+#define DMA_CCR_HTIE_Pos ( 2U )
+#define DMA_CCR_HTIE_Msk ( 0x1UL << DMA_CCR_HTIE_Pos )
+#define DMA_CCR_HTIE ( DMA_CCR_HTIE_Msk )
+#define DMA_CCR_TEIE_Pos ( 3U )
+#define DMA_CCR_TEIE_Msk ( 0x1UL << DMA_CCR_TEIE_Pos )
+#define DMA_CCR_TEIE ( DMA_CCR_TEIE_Msk )
+#define DMA_CCR_DIR_Pos ( 4U )
+#define DMA_CCR_DIR_Msk ( 0x1UL << DMA_CCR_DIR_Pos )
+#define DMA_CCR_DIR ( DMA_CCR_DIR_Msk )
+#define DMA_CCR_CIRC_Pos ( 5U )
+#define DMA_CCR_CIRC_Msk ( 0x1UL << DMA_CCR_CIRC_Pos )
+#define DMA_CCR_CIRC ( DMA_CCR_CIRC_Msk )
+#define DMA_CCR_PINC_Pos ( 6U )
+#define DMA_CCR_PINC_Msk ( 0x1UL << DMA_CCR_PINC_Pos )
+#define DMA_CCR_PINC ( DMA_CCR_PINC_Msk )
+#define DMA_CCR_MINC_Pos ( 7U )
+#define DMA_CCR_MINC_Msk ( 0x1UL << DMA_CCR_MINC_Pos )
+#define DMA_CCR_MINC ( DMA_CCR_MINC_Msk )
+#define DMA_CCR_PSIZE_Pos ( 8U )
+#define DMA_CCR_PSIZE_Msk ( 0x3UL << DMA_CCR_PSIZE_Pos )
+#define DMA_CCR_PSIZE ( DMA_CCR_PSIZE_Msk )
+#define DMA_CCR_MSIZE_Pos ( 10U )
+#define DMA_CCR_MSIZE_Msk ( 0x3UL << DMA_CCR_MSIZE_Pos )
+#define DMA_CCR_MSIZE ( DMA_CCR_MSIZE_Msk )
+#define DMA_CCR_PL_Pos ( 12U )
+#define DMA_CCR_PL_Msk ( 0x3UL << DMA_CCR_PL_Pos )
+#define DMA_CCR_PL ( DMA_CCR_PL_Msk )
+#define DMA_CCR_MEM2MEM_Pos ( 14U )
+#define DMA_CCR_MEM2MEM_Msk ( 0x1UL << DMA_CCR_MEM2MEM_Pos )
+#define DMA_CCR_MEM2MEM ( DMA_CCR_MEM2MEM_Msk )
+
+/* SPI register bit definitions. */
+/* CR1 */
+#define SPI_CR1_CPHA_Pos ( 0U )
+#define SPI_CR1_CPHA_Msk ( 0x1UL << SPI_CR1_CPHA_Pos )
+#define SPI_CR1_CPHA ( SPI_CR1_CPHA_Msk )
+#define SPI_CR1_CPOL_Pos ( 1U )
+#define SPI_CR1_CPOL_Msk ( 0x1UL << SPI_CR1_CPOL_Pos )
+#define SPI_CR1_CPOL ( SPI_CR1_CPOL_Msk )
+#define SPI_CR1_MSTR_Pos ( 2U )
+#define SPI_CR1_MSTR_Msk ( 0x1UL << SPI_CR1_MSTR_Pos )
+#define SPI_CR1_MSTR ( SPI_CR1_MSTR_Msk )
+#define SPI_CR1_BR_Pos ( 3U )
+#define SPI_CR1_BR_Msk ( 0x7UL << SPI_CR1_BR_Pos )
+#define SPI_CR1_BR ( SPI_CR1_BR_Msk )
+#define SPI_CR1_SPE_Pos ( 6U )
+#define SPI_CR1_SPE_Msk ( 0x1UL << SPI_CR1_SPE_Pos )
+#define SPI_CR1_SPE ( SPI_CR1_SPE_Msk )
+#define SPI_CR1_LSBFIRST_Pos ( 7U )
+#define SPI_CR1_LSBFIRST_Msk ( 0x1UL << SPI_CR1_LSBFIRST_Pos )
+#define SPI_CR1_LSBFIRST ( SPI_CR1_LSBFIRST_Msk )
+#define SPI_CR1_SSI_Pos ( 8U )
+#define SPI_CR1_SSI_Msk ( 0x1UL << SPI_CR1_SSI_Pos )
+#define SPI_CR1_SSI ( SPI_CR1_SSI_Msk )
+#define SPI_CR1_SSM_Pos ( 9U )
+#define SPI_CR1_SSM_Msk ( 0x1UL << SPI_CR1_SSM_Pos )
+#define SPI_CR1_SSM ( SPI_CR1_SSM_Msk )
+#define SPI_CR1_RXONLY_Pos ( 10U )
+#define SPI_CR1_RXONLY_Msk ( 0x1UL << SPI_CR1_RXONLY_Pos )
+#define SPI_CR1_RXONLY ( SPI_CR1_RXONLY_Msk )
+#define SPI_CR1_DFF_Pos ( 11U )
+#define SPI_CR1_DFF_Msk ( 0x1UL << SPI_CR1_DFF_Pos )
+#define SPI_CR1_DFF ( SPI_CR1_DFF_Msk )
+#define SPI_CR1_CRCNEXT_Pos ( 12U )
+#define SPI_CR1_CRCNEXT_Msk ( 0x1UL << SPI_CR1_CRCNEXT_Pos )
+#define SPI_CR1_CRCNEXT ( SPI_CR1_CRCNEXT_Msk )
+#define SPI_CR1_CRCEN_Pos ( 13U )
+#define SPI_CR1_CRCEN_Msk ( 0x1UL << SPI_CR1_CRCEN_Pos )
+#define SPI_CR1_CRCEN ( SPI_CR1_CRCEN_Msk )
+#define SPI_CR1_BIDIOE_Pos ( 14U )
+#define SPI_CR1_BIDIOE_Msk ( 0x1UL << SPI_CR1_BIDIOE_Pos )
+#define SPI_CR1_BIDIOE ( SPI_CR1_BIDIOE_Msk )
+#define SPI_CR1_BIDIMODE_Pos ( 15U )
+#define SPI_CR1_BIDIMODE_Msk ( 0x1UL << SPI_CR1_BIDIMODE_Pos )
+#define SPI_CR1_BIDIMODE ( SPI_CR1_BIDIMODE_Msk )
+/* CR2 */
+#define SPI_CR2_RXDMAEN_Pos ( 0U )
+#define SPI_CR2_RXDMAEN_Msk ( 0x1UL << SPI_CR2_RXDMAEN_Pos )
+#define SPI_CR2_RXDMAEN ( SPI_CR2_RXDMAEN_Msk )
+#define SPI_CR2_TXDMAEN_Pos ( 1U )
+#define SPI_CR2_TXDMAEN_Msk ( 0x1UL << SPI_CR2_TXDMAEN_Pos )
+#define SPI_CR2_TXDMAEN ( SPI_CR2_TXDMAEN_Msk )
+#define SPI_CR2_SSOE_Pos ( 2U )
+#define SPI_CR2_SSOE_Msk ( 0x1UL << SPI_CR2_SSOE_Pos )
+#define SPI_CR2_SSOE ( SPI_CR2_SSOE_Msk )
+/*
+ Note: 'NSS pulse mode' and 'TI mode' bits don't show up in
+ STM32F103 reference documents.
+ */
+#define SPI_CR2_NSSP_Pos ( 3U )
+#define SPI_CR2_NSSP_Msk ( 0x1UL << SPI_CR2_NSSP_Pos )
+#define SPI_CR2_NSSP ( SPI_CR2_NSSP_Msk )
+#define SPI_CR2_TIMOD_Pos ( 4U )
+#define SPI_CR2_TIMOD_Msk ( 0x1UL << SPI_CR2_TIMOD_Pos )
+#define SPI_CR2_TIMOD ( SPI_CR2_TIMOD_Msk )
+#define SPI_CR2_ERRIE_Pos ( 5U )
+#define SPI_CR2_ERRIE_Msk ( 0x1UL << SPI_CR2_ERRIE_Pos )
+#define SPI_CR2_ERRIE ( SPI_CR2_ERRIE_Msk )
+#define SPI_CR2_RXNEIE_Pos ( 6U )
+#define SPI_CR2_RXNEIE_Msk ( 0x1UL << SPI_CR2_RXNEIE_Pos )
+#define SPI_CR2_RXNEIE ( SPI_CR2_RXNEIE_Msk )
+#define SPI_CR2_TXEIE_Pos ( 7U )
+#define SPI_CR2_TXEIE_Msk ( 0x1UL << SPI_CR2_TXEIE_Pos )
+#define SPI_CR2_TXEIE ( SPI_CR2_TXEIE_Msk )
+/* SR / STAT */
+#define SPI_SR_RXNE_Pos ( 0U )
+#define SPI_SR_RXNE_Msk ( 0x1UL << SPI_SR_RXNE_Pos )
+#define SPI_SR_RXNE ( SPI_SR_RXNE_Msk )
+#define SPI_SR_TXE_Pos ( 1U )
+#define SPI_SR_TXE_Msk ( 0x1UL << SPI_SR_TXE_Pos )
+#define SPI_SR_TXE ( SPI_SR_TXE_Msk )
+#define SPI_SR_CHSIDE_Pos ( 2U )
+#define SPI_SR_CHSIDE_Msk ( 0x1UL << SPI_SR_CHSIDE_Pos )
+#define SPI_SR_CHSIDE ( SPI_SR_CHSIDE_Msk )
+#define SPI_SR_UDR_Pos ( 3U )
+#define SPI_SR_UDR_Msk ( 0x1UL << SPI_SR_UDR_Pos )
+#define SPI_SR_UDR ( SPI_SR_UDR_Msk )
+#define SPI_SR_CRCERR_Pos ( 4U )
+#define SPI_SR_CRCERR_Msk ( 0x1UL << SPI_SR_CRCERR_Pos )
+#define SPI_SR_CRCERR ( SPI_SR_CRCERR_Msk )
+#define SPI_SR_MODF_Pos ( 5U )
+#define SPI_SR_MODF_Msk ( 0x1UL << SPI_SR_MODF_Pos )
+#define SPI_SR_MODF ( SPI_SR_MODF_Msk )
+#define SPI_SR_OVR_Pos ( 6U )
+#define SPI_SR_OVR_Msk ( 0x1UL << SPI_SR_OVR_Pos )
+#define SPI_SR_OVR ( SPI_SR_OVR_Msk )
+#define SPI_SR_BSY_Pos ( 7U )
+#define SPI_SR_BSY_Msk ( 0x1UL << SPI_SR_BSY_Pos )
+#define SPI_SR_BSY ( SPI_SR_BSY_Msk )
+/* Note: "Format error" bit doesn't show up in STM32F1 documentation */
+#define SPI_SR_FERR_Pos ( 8U )
+#define SPI_SR_FERR_Msk ( 0x1UL << SPI_SR_FERR_Pos )
+#define SPI_SR_FERR ( SPI_SR_FERR_Msk )
+
+#endif
Index: include/n200_eclic.h
===================================================================
--- include/n200_eclic.h (nonexistent)
+++ include/n200_eclic.h (revision 411)
@@ -0,0 +1,49 @@
+
+#ifndef N200_ECLIC_H
+#define N200_ECLIC_H
+
+#include <riscv_const.h>
+
+#define ECLICINTCTLBITS 4
+
+/*
+ ECLIC memory map
+ Offset
+ 0x0000 1B RW ecliccfg
+ */
+#define ECLIC_CFG_OFFSET 0x0
+/* 0x0004 4B R eclicinfo */
+#define ECLIC_INFO_OFFSET 0x4
+/* 0x000B 1B RW mintthresh */
+#define ECLIC_MTH_OFFSET 0xB
+
+/* 0x1000+4*i 1B/input RW eclicintip[i] */
+#define ECLIC_INT_IP_OFFSET _AC(0x1000,UL)
+/* 0x1001+4*i 1B/input RW eclicintie[i] */
+#define ECLIC_INT_IE_OFFSET _AC(0x1001,UL)
+/* 0x1002+4*i 1B/input RW eclicintattr[i] */
+#define ECLIC_INT_ATTR_OFFSET _AC(0x1002,UL)
+
+#define ECLIC_INT_ATTR_SHV 0x01
+#define ECLIC_INT_ATTR_TRIG_LEVEL 0x00
+#define ECLIC_INT_ATTR_TRIG_EDGE 0x02
+#define ECLIC_INT_ATTR_TRIG_POS 0x00
+#define ECLIC_INT_ATTR_TRIG_NEG 0x04
+
+/* 0x1003+4*i 1B/input RW eclicintctl[i] */
+#define ECLIC_INT_CTRL_OFFSET _AC(0x1003,UL)
+/*
+ ...
+ */
+#define ECLIC_ADDR_BASE 0xd2000000
+
+
+#define ECLIC_CFG_NLBITS_MASK _AC(0x1E,UL)
+#define ECLIC_CFG_NLBITS_LSB (1u)
+
+#define MSIP_HANDLER eclic_msip_handler
+#define MTIME_HANDLER eclic_mtip_handler
+#define BWEI_HANDLER eclic_bwei_handler
+#define PMOVI_HANDLER eclic_pmovi_handler
+
+#endif
Index: include/n200_func.h
===================================================================
--- include/n200_func.h (nonexistent)
+++ include/n200_func.h (revision 411)
@@ -0,0 +1,95 @@
+
+#ifndef N200_FUNC_H
+#define N200_FUNC_H
+
+
+#include <stddef.h>
+#include <n200_timer.h>
+#include <n200_eclic.h>
+
+#define ECLIC_GROUP_LEVEL0_PRIO4 0
+#define ECLIC_GROUP_LEVEL1_PRIO3 1
+#define ECLIC_GROUP_LEVEL2_PRIO2 2
+#define ECLIC_GROUP_LEVEL3_PRIO1 3
+#define ECLIC_GROUP_LEVEL4_PRIO0 4
+
+void pmp_open_all_space();
+void switch_m2u_mode();
+uint32_t get_mtime_freq();
+uint32_t mtime_lo(void);
+uint32_t mtime_hi(void);
+uint64_t get_mtime_value();
+uint64_t get_instret_value();
+uint64_t get_cycle_value();
+uint32_t get_cpu_freq();
+uint32_t __attribute__((noinline)) measure_cpu_freq(size_t n);
+
+/******************************************************************
+ ECLIC relevant functions:
+ */
+void eclic_init ( uint32_t num_irq );
+uint64_t get_timer_value();
+void eclic_enable_interrupt (uint32_t source);
+void eclic_disable_interrupt (uint32_t source);
+
+void eclic_set_pending(uint32_t source);
+void eclic_clear_pending(uint32_t source);
+
+void eclic_set_intctrl (uint32_t source, uint8_t intctrl);
+uint8_t eclic_get_intctrl (uint32_t source);
+
+void eclic_set_intattr (uint32_t source, uint8_t intattr);
+uint8_t eclic_get_intattr (uint32_t source);
+
+void eclic_set_cliccfg (uint8_t cliccfg);
+uint8_t eclic_get_cliccfg ();
+
+void eclic_set_mth (uint8_t mth);
+uint8_t eclic_get_mth();
+
+/* sets nlbits */
+void eclic_set_nlbits(uint8_t nlbits);
+
+/* get nlbits */
+uint8_t eclic_get_nlbits();
+
+void eclic_set_irq_lvl(uint32_t source, uint8_t lvl);
+uint8_t eclic_get_irq_lvl(uint32_t source);
+
+void eclic_set_irq_lvl_abs(uint32_t source, uint8_t lvl_abs);
+uint8_t eclic_get_irq_lvl_abs(uint32_t source);
+
+uint8_t eclic_set_irq_priority(uint32_t source, uint8_t priority);
+uint8_t eclic_get_irq_priority(uint32_t source);
+
+void eclic_mode_enable();
+
+void eclic_set_vmode(uint32_t source);
+void eclic_set_nonvmode(uint32_t source);
+
+void eclic_set_level_trig(uint32_t source);
+void eclic_set_posedge_trig(uint32_t source);
+void eclic_set_negedge_trig(uint32_t source);
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static inline void __WFI(void) {
+ __asm volatile ("wfi");
+}
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static inline void __WFE(void) {
+ __asm volatile ("csrs 0x810, 0x1");
+ __asm volatile ("wfi");
+ __asm volatile ("csrc 0x810, 0x1");
+}
+
+#endif
Index: include/n200_timer.h
===================================================================
--- include/n200_timer.h (nonexistent)
+++ include/n200_timer.h (revision 411)
@@ -0,0 +1,16 @@
+
+#ifndef N200_TIMER_H
+#define N200_TIMER_H
+
+#define TIMER_MSIP 0xFFC
+#define TIMER_MSIP_size 0x4
+#define TIMER_MTIMECMP 0x8
+#define TIMER_MTIMECMP_size 0x8
+#define TIMER_MTIME 0x0
+#define TIMER_MTIME_size 0x8
+
+#define TIMER_CTRL_ADDR 0xd1000000
+#define TIMER_REG(offset) _REG32(TIMER_CTRL_ADDR, offset)
+#define TIMER_FREQ ((uint32_t)SystemCoreClock/4) /* units HZ */
+
+#endif
Index: include/riscv_bits.h
===================================================================
--- include/riscv_bits.h (nonexistent)
+++ include/riscv_bits.h (revision 411)
@@ -0,0 +1,36 @@
+
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x) XSTR(x)
+#define XSTR(x) #x
+
+#if __riscv_xlen == 64
+# define SLL32 sllw
+# define STORE sd
+# define LOAD ld
+# define LWU lwu
+# define LOG_REGBYTES 3
+#else
+# define SLL32 sll
+# define STORE sw
+# define LOAD lw
+# define LWU lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
Index: include/riscv_const.h
===================================================================
--- include/riscv_const.h (nonexistent)
+++ include/riscv_const.h (revision 411)
@@ -0,0 +1,18 @@
+
+/* Derived from <linux/const.h> */
+
+#ifndef _RISCV_CONST_H
+#define _RISCV_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define _AC(X,Y) (X##Y)
+#define _AT(T,X) ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x) (_AC(1,UL) << (x))
+#define _BITULL(x) (_AC(1,ULL) << (x))
+
+#endif /* _NUCLEI_CONST_H */
Index: include/riscv_encoding.h
===================================================================
--- include/riscv_encoding.h (nonexistent)
+++ include/riscv_encoding.h (revision 411)
@@ -0,0 +1,1355 @@
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_PUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_VM 0x1F000000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_PUM 0x00040000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1<<19)
+#define MCONTROL_TIMING (1<<18)
+#define MCONTROL_ACTION (0x3f<<12)
+#define MCONTROL_CHAIN (1<<11)
+#define MCONTROL_MATCH (0xf<<7)
+#define MCONTROL_M (1<<6)
+#define MCONTROL_H (1<<5)
+#define MCONTROL_S (1<<4)
+#define MCONTROL_U (1<<3)
+#define MCONTROL_EXECUTE (1<<2)
+#define MCONTROL_STORE (1<<1)
+#define MCONTROL_LOAD (1<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define MIE_SSIE MIP_SSIP
+#define MIE_HSIE MIP_HSIP
+#define MIE_MSIE MIP_MSIP
+#define MIE_STIE MIP_STIP
+#define MIE_HTIE MIP_HTIP
+#define MIE_MTIE MIP_MTIP
+#define MIE_SEIE MIP_SEIP
+#define MIE_HEIE MIP_HEIP
+#define MIE_MEIE MIP_MEIP
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB 1
+#define VM_MBBID 2
+#define VM_SV32 8
+#define VM_SV39 9
+#define VM_SV48 10
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define DEFAULT_NMIVEC 0x00001004
+#define DEFAULT_MTVEC 0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_fpu(reg) ({ unsigned long __tmp; \
+ asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_fpu(reg, val) ({ \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+ else \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+#endif
+#endif
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM 0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+
+#define CSR_MTVT 0x307
+#define CSR_MNXTI 0x345
+
+#define CSR_MCOUNTINHIBIT 0x320
+
+#define CSR_MNVEC 0x7C3
+
+#define CSR_MTVT2 0x7EC
+#define CSR_JALMNXTI 0x7ED
+#define CSR_PUSHMCAUSE 0x7EE
+#define CSR_PUSHMEPC 0x7EF
+#define CSR_PUSHMSUBM 0x7EB
+
+#define CSR_WFE 0x810
+#define CSR_SLEEPVALUE 0x811
+#define CSR_TXEVT 0x812
+
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MSUBM 0x7c4
+
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
+MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
+MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
+MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
+MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
Index: n200_func.c
===================================================================
--- n200_func.c (nonexistent)
+++ n200_func.c (revision 411)
@@ -0,0 +1,431 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include <gd32vf103.h>
+#include <riscv_encoding.h>
+#include <n200_func.h>
+
+/*
+ Uncomment this line if you have only -march=rv32imac instead of -march=rv32imac_zicsr:
+__asm("\t.option arch, +zicsr");
+ */
+
+/* Configure PMP to make all the address space accesable and executable */
+void pmp_open_all_space()
+{
+ /* Config entry0 addr to all 1s to make the range cover all space */
+ asm volatile ("li x6, 0xffffffff":::"x6");
+ asm volatile ("csrw pmpaddr0, x6":::);
+ /* Config entry0 cfg to make it NAPOT address mode, and R/W/X okay */
+ asm volatile ("li x6, 0x7f":::"x6");
+ asm volatile ("csrw pmpcfg0, x6":::);
+}
+
+void switch_m2u_mode()
+{
+ clear_csr (mstatus,MSTATUS_MPP);
+ /* printf("\nIn the m2u function, the mstatus is 0x%x\n", read_csr(mstatus)); */
+ /* printf("\nIn the m2u function, the mepc is 0x%x\n", read_csr(mepc)); */
+ asm volatile ("la x6, 1f ":::"x6");
+ asm volatile ("csrw mepc, x6":::);
+ asm volatile ("mret":::);
+ asm volatile ("1:":::);
+}
+
+uint32_t mtime_lo( void )
+{
+ return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME);
+}
+
+
+uint32_t mtime_hi( void )
+{
+ return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4);
+}
+
+uint64_t get_timer_value()
+{
+ while( 1 )
+ {
+ uint32_t hi = mtime_hi();
+ uint32_t lo = mtime_lo();
+ if (hi == mtime_hi())
+ return ((uint64_t)hi << 32) | lo;
+ }
+}
+
+uint32_t get_timer_freq()
+{
+ return TIMER_FREQ;
+}
+
+uint64_t get_instret_value()
+{
+ while( 1 )
+ {
+ uint32_t hi = read_csr(minstreth);
+ uint32_t lo = read_csr(minstret);
+ if (hi == read_csr(minstreth))
+ return ((uint64_t)hi << 32) | lo;
+ }
+}
+
+uint64_t get_cycle_value()
+{
+ while( 1 )
+ {
+ uint32_t hi = read_csr(mcycleh);
+ uint32_t lo = read_csr(mcycle);
+ if (hi == read_csr(mcycleh))
+ return ((uint64_t)hi << 32) | lo;
+ }
+}
+
+uint32_t __attribute__((noinline)) measure_cpu_freq( size_t n )
+{
+ uint32_t start_mtime, delta_mtime;
+ uint32_t mtime_freq = get_timer_freq();
+
+ /* Don't start measuruing until we see an mtime tick */
+ uint32_t tmp = mtime_lo();
+ do {
+ start_mtime = mtime_lo();
+ } while (start_mtime == tmp);
+
+ uint32_t start_mcycle = read_csr(mcycle);
+
+ do {
+ delta_mtime = mtime_lo() - start_mtime;
+ } while (delta_mtime < n);
+
+ uint32_t delta_mcycle = read_csr(mcycle) - start_mcycle;
+
+ return (delta_mcycle / delta_mtime) * mtime_freq
+ + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
+}
+
+uint32_t get_cpu_freq()
+{
+ uint32_t cpu_freq;
+
+ /* warm up */
+ measure_cpu_freq(1);
+ /* measure for real */
+ cpu_freq = measure_cpu_freq(100);
+
+ return cpu_freq;
+}
+
+
+/*
+ Note that there are no assertions or bounds checking on these parameter values.
+ */
+void eclic_init ( uint32_t num_irq )
+{
+
+ typedef volatile uint32_t vuint32_t;
+
+ /* clear cfg register */
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_CFG_OFFSET)=0;
+
+ /* clear minthresh register */
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_MTH_OFFSET)=0;
+
+ /* clear all IP/IE/ATTR/CTRL bits for all interrupt sources */
+ vuint32_t * ptr;
+
+ vuint32_t * base = (vuint32_t*)(ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET);
+ vuint32_t * upper = (vuint32_t*)(base + num_irq*4);
+
+ for (ptr = base; ptr < upper; ptr=ptr+4){
+ *ptr = 0;
+ }
+}
+
+
+
+void eclic_enable_interrupt( uint32_t source )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IE_OFFSET+source*4) = 1;
+}
+
+void eclic_disable_interrupt( uint32_t source )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IE_OFFSET+source*4) = 0;
+}
+
+void eclic_set_pending( uint32_t source )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IP_OFFSET+source*4) = 1;
+}
+
+void eclic_clear_pending( uint32_t source )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_IP_OFFSET+source*4) = 0;
+}
+
+void eclic_set_intctrl( uint32_t source, uint8_t intctrl )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_CTRL_OFFSET+source*4) = intctrl;
+}
+
+uint8_t eclic_get_intctrl( uint32_t source )
+{
+ return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_CTRL_OFFSET+source*4);
+}
+
+void eclic_set_intattr( uint32_t source, uint8_t intattr )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_ATTR_OFFSET+source*4) = intattr;
+}
+
+uint8_t eclic_get_intattr( uint32_t source )
+{
+ return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_INT_ATTR_OFFSET+source*4);
+}
+
+void eclic_set_cliccfg( uint8_t cliccfg )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_CFG_OFFSET) = cliccfg;
+}
+
+uint8_t eclic_get_cliccfg()
+{
+ return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_CFG_OFFSET);
+}
+
+void eclic_set_mth( uint8_t mth )
+{
+ *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_MTH_OFFSET) = mth;
+}
+
+uint8_t eclic_get_mth()
+{
+ return *(volatile uint8_t*)(ECLIC_ADDR_BASE+ECLIC_MTH_OFFSET);
+}
+
+/* sets nlbits */
+void eclic_set_nlbits( uint8_t nlbits )
+{
+ /* shift nlbits to correct position */
+ uint8_t nlbits_shifted = nlbits << ECLIC_CFG_NLBITS_LSB;
+
+ /* read the current cliccfg */
+ uint8_t old_cliccfg = eclic_get_cliccfg();
+ uint8_t new_cliccfg = (old_cliccfg & (~ECLIC_CFG_NLBITS_MASK)) | (ECLIC_CFG_NLBITS_MASK & nlbits_shifted);
+
+ eclic_set_cliccfg(new_cliccfg);
+}
+
+/* get nlbits */
+uint8_t eclic_get_nlbits( void )
+{
+ //extract nlbits */
+ uint8_t nlbits = eclic_get_cliccfg();
+ nlbits = (nlbits & ECLIC_CFG_NLBITS_MASK) >> ECLIC_CFG_NLBITS_LSB;
+ return nlbits;
+}
+
+/* sets an interrupt level based encoding of nlbits and ECLICINTCTLBITS */
+void eclic_set_irq_lvl( uint32_t source, uint8_t lvl )
+{
+ /* extract nlbits */
+ uint8_t nlbits = eclic_get_nlbits();
+ if( nlbits > ECLICINTCTLBITS ) {
+ nlbits = ECLICINTCTLBITS;
+ }
+
+ /* shift lvl right to mask off unused bits */
+ lvl = lvl >> (8-nlbits);
+ /* shift lvl into correct bit position */
+ lvl = lvl << (8-nlbits);
+
+ /* write to clicintctrl */
+ uint8_t current_intctrl = eclic_get_intctrl(source);
+ /* shift intctrl left to mask off unused bits */
+ current_intctrl = current_intctrl << nlbits;
+ /* shift intctrl into correct bit position */
+ current_intctrl = current_intctrl >> nlbits;
+
+ eclic_set_intctrl(source, (current_intctrl | lvl));
+}
+
+/* gets an interrupt level based encoding of nlbits */
+uint8_t eclic_get_irq_lvl( uint32_t source )
+{
+ /* extract nlbits */
+ uint8_t nlbits = eclic_get_nlbits();
+ if( nlbits > ECLICINTCTLBITS ) {
+ nlbits = ECLICINTCTLBITS;
+ }
+
+ uint8_t intctrl = eclic_get_intctrl(source);
+
+ /* shift intctrl */
+ intctrl = intctrl >> (8-nlbits);
+ /* shift intctrl */
+ uint8_t lvl = intctrl << (8-nlbits);
+
+ return lvl;
+}
+
+void eclic_set_irq_lvl_abs( uint32_t source, uint8_t lvl_abs )
+{
+ /* extract nlbits */
+ uint8_t nlbits = eclic_get_nlbits();
+ if( nlbits > ECLICINTCTLBITS ) {
+ nlbits = ECLICINTCTLBITS;
+ }
+
+ /* shift lvl_abs into correct bit position */
+ uint8_t lvl = lvl_abs << (8-nlbits);
+
+ /* write to clicintctrl */
+ uint8_t current_intctrl = eclic_get_intctrl(source);
+ /* shift intctrl left to mask off unused bits */
+ current_intctrl = current_intctrl << nlbits;
+ /* shift intctrl into correct bit position */
+ current_intctrl = current_intctrl >> nlbits;
+
+ eclic_set_intctrl(source, (current_intctrl | lvl));
+}
+
+uint8_t eclic_get_irq_lvl_abs( uint32_t source )
+{
+ /* extract nlbits */
+ uint8_t nlbits = eclic_get_nlbits();
+ if( nlbits > ECLICINTCTLBITS ) {
+ nlbits = ECLICINTCTLBITS;
+ }
+
+ uint8_t intctrl = eclic_get_intctrl(source);
+
+ /* shift intctrl */
+ intctrl = intctrl >> (8-nlbits);
+ /* shift intctrl */
+ uint8_t lvl_abs = intctrl;
+
+ return lvl_abs;
+}
+
+/* sets an interrupt priority based encoding of nlbits and ECLICINTCTLBITS */
+uint8_t eclic_set_irq_priority( uint32_t source, uint8_t priority )
+{
+ /* extract nlbits */
+ uint8_t nlbits = eclic_get_nlbits();
+ if( nlbits >= ECLICINTCTLBITS ) {
+ nlbits = ECLICINTCTLBITS;
+ return 0;
+ }
+
+ /* shift priority into correct bit position */
+ priority = priority << (8 - ECLICINTCTLBITS);
+
+ /* write to eclicintctrl */
+ uint8_t current_intctrl = eclic_get_intctrl(source);
+ /* shift intctrl right to mask off unused bits */
+ current_intctrl = current_intctrl >> (8-nlbits);
+ /* shift intctrl into correct bit position */
+ current_intctrl = current_intctrl << (8-nlbits);
+
+ eclic_set_intctrl(source, (current_intctrl | priority));
+
+ return priority;
+}
+
+/* gets an interrupt priority based encoding of nlbits */
+uint8_t eclic_get_irq_priority( uint32_t source )
+{
+ /* extract nlbits */
+ uint8_t nlbits = eclic_get_nlbits();
+ if( nlbits > ECLICINTCTLBITS ) {
+ nlbits = ECLICINTCTLBITS;
+ }
+
+ uint8_t intctrl = eclic_get_intctrl(source);
+
+ /* shift intctrl */
+ intctrl = intctrl << nlbits;
+ /* shift intctrl */
+ uint8_t priority = intctrl >> (nlbits+(8 - ECLICINTCTLBITS));
+
+ return priority;
+}
+
+void eclic_mode_enable()
+{
+ uint32_t mtvec_value = read_csr(mtvec);
+ mtvec_value = mtvec_value & 0xFFFFFFC0;
+ mtvec_value = mtvec_value | 0x00000003;
+ write_csr(mtvec,mtvec_value);
+}
+
+/* sets vector-mode or non-vector mode */
+void eclic_set_vmode( uint32_t source )
+{
+ /* read the current attr */
+ uint8_t old_intattr = eclic_get_intattr(source);
+ /* Keep other bits unchanged and only set the LSB bit */
+ uint8_t new_intattr = (old_intattr | 0x1);
+
+ eclic_set_intattr(source,new_intattr);
+}
+
+void eclic_set_nonvmode( uint32_t source )
+{
+ /* read the current attr */
+ uint8_t old_intattr = eclic_get_intattr(source);
+ /* Keep other bits unchanged and only clear the LSB bit */
+ uint8_t new_intattr = (old_intattr & (~0x1));
+
+ eclic_set_intattr(source,new_intattr);
+}
+
+/*
+ Sets interrupt as level sensitive
+
+ Bit 1, trig[0], is defined as "edge-triggered" (0: level-triggered, 1: edge-triggered);
+ Bit 2, trig[1], is defined as "negative-edge" (0: positive-edge, 1: negative-edge).
+ */
+void eclic_set_level_trig( uint32_t source )
+{
+ /* read the current attr */
+ uint8_t old_intattr = eclic_get_intattr(source);
+ /* Keep other bits unchanged and only clear the bit 1 */
+ uint8_t new_intattr = (old_intattr & (~0x2));
+
+ eclic_set_intattr(source,new_intattr);
+}
+
+void eclic_set_posedge_trig( uint32_t source )
+{
+ /* read the current attr */
+ uint8_t old_intattr = eclic_get_intattr(source);
+ /* Keep other bits unchanged and only set the bit 1 */
+ uint8_t new_intattr = (old_intattr | 0x2);
+ /* Keep other bits unchanged and only clear the bit 2 */
+ new_intattr = (old_intattr & (~0x4));
+
+ eclic_set_intattr(source,new_intattr);
+}
+
+void eclic_set_negedge_trig( uint32_t source )
+{
+ /* read the current attr */
+ uint8_t old_intattr = eclic_get_intattr(source);
+ /* Keep other bits unchanged and only set the bit 1 */
+ uint8_t new_intattr = (old_intattr | 0x2);
+ /* Keep other bits unchanged and only set the bit 2 */
+ new_intattr = (old_intattr | 0x4);
+
+ eclic_set_intattr(source,new_intattr);
+}
+
+/*
+void wfe() {
+ core_wfe();
+}
+ */
Radix cross Linux
The main Radix cross Linux repository contains the build scripts of packages, which have the most complete and common functionality for desktop machines
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