Index: v6.x/create-6.3.10-orange-pi5-patch/file.list
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/file.list (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/file.list (revision 152)
@@ -1,6 +1 @@
linux-6.3.10/arch/arm64/boot/dts/rockchip/Makefile
-linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
-linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-linux-6.3.10/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
-linux-6.3.10/include/dt-bindings/soc/rockchip,boot-mode.h
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/phy/phy-snps-pcie3.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/phy/phy-snps-pcie3.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/phy/phy-snps-pcie3.h (nonexistent)
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#ifndef _DT_BINDINGS_PHY_SNPS_PCIE3
-#define _DT_BINDINGS_PHY_SNPS_PCIE3
-
-/*
- * pcie30_phy_mode[2:0]
- * bit2: aggregation
- * bit1: bifurcation for port 1
- * bit0: bifurcation for port 0
- */
-#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
-#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
-#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
-#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
-#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
-
-#endif /* _DT_BINDINGS_PHY_SNPS_PCIE3 */
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/mipi_dsi.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/mipi_dsi.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/mipi_dsi.h (nonexistent)
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
-drivers/video/rockchip/transmitter/mipi_dsi.h
-*/
-#ifndef MIPI_DSI_H_
-#define MIPI_DSI_H_
-
-#ifdef CONFIG_MIPI_DSI_FT
-#include "..\..\common\config.h"
-#endif
-
-//DSI DATA TYPE
-#define DTYPE_DCS_SWRITE_0P 0x05
-#define DTYPE_DCS_SWRITE_1P 0x15
-#define DTYPE_DCS_LWRITE 0x39
-#define DTYPE_GEN_LWRITE 0x29
-#define DTYPE_GEN_SWRITE_2P 0x23
-#define DTYPE_GEN_SWRITE_1P 0x13
-#define DTYPE_GEN_SWRITE_0P 0x03
-
-//command transmit mode
-#define HSDT 0x00
-#define LPDT 0x01
-
-//DSI DATA TYPE FLAG
-#define DATA_TYPE_DCS 0x00
-#define DATA_TYPE_GEN 0x01
-
-//Video Mode
-#define VM_NBMWSP 0x00 //Non burst mode with sync pulses
-#define VM_NBMWSE 0x01 //Non burst mode with sync events
-#define VM_BM 0x02 //Burst mode
-
-//Video Pixel Format
-#define VPF_16BPP 0x00
-#define VPF_18BPP 0x01 //packed
-#define VPF_18BPPL 0x02 //loosely packed
-#define VPF_24BPP 0x03
-
-//Display Command Set
-#define dcs_enter_idle_mode 0x39
-#define dcs_enter_invert_mode 0x21
-#define dcs_enter_normal_mode 0x13
-#define dcs_enter_partial_mode 0x12
-#define dcs_enter_sleep_mode 0x10
-#define dcs_exit_idle_mode 0x38
-#define dcs_exit_invert_mode 0x20
-#define dcs_exit_sleep_mode 0x11
-#define dcs_get_address_mode 0x0b
-#define dcs_get_blue_channel 0x08
-#define dcs_get_diagnostic_result 0x0f
-#define dcs_get_display_mode 0x0d
-#define dcs_get_green_channel 0x07
-#define dcs_get_pixel_format 0x0c
-#define dcs_get_power_mode 0x0a
-#define dcs_get_red_channel 0x06
-#define dcs_get_scanline 0x45
-#define dcs_get_signal_mode 0x0e
-#define dcs_nop 0x00
-#define dcs_read_DDB_continue 0xa8
-#define dcs_read_DDB_start 0xa1
-#define dcs_read_memory_continue 0x3e
-#define dcs_read_memory_start 0x2e
-#define dcs_set_address_mode 0x36
-#define dcs_set_column_address 0x2a
-#define dcs_set_display_off 0x28
-#define dcs_set_display_on 0x29
-#define dcs_set_gamma_curve 0x26
-#define dcs_set_page_address 0x2b
-#define dcs_set_partial_area 0x30
-#define dcs_set_pixel_format 0x3a
-#define dcs_set_scroll_area 0x33
-#define dcs_set_scroll_start 0x37
-#define dcs_set_tear_off 0x34
-#define dcs_set_tear_on 0x35
-#define dcs_set_tear_scanline 0x44
-#define dcs_soft_reset 0x01
-#define dcs_write_LUT 0x2d
-#define dcs_write_memory_continue 0x3c
-#define dcs_write_memory_start 0x2c
-
-#ifndef MHz
-#define MHz 1000000
-#endif
-
-
-#if 0
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long s64;
-typedef unsigned long u64;
-#endif
-
-
-//iomux
-#define OLD_RK_IOMUX 0
-
-
-#endif /* end of MIPI_DSI_H_ */
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/rockchip_vop.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/rockchip_vop.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/rockchip_vop.h (nonexistent)
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-
-#ifndef _DT_BINDINGS_ROCKCHIP_VOP_H
-#define _DT_BINDINGS_ROCKCHIP_VOP_H
-
-#define ROCKCHIP_VOP2_CLUSTER0 0
-#define ROCKCHIP_VOP2_CLUSTER1 1
-#define ROCKCHIP_VOP2_ESMART0 2
-#define ROCKCHIP_VOP2_ESMART1 3
-#define ROCKCHIP_VOP2_SMART0 4
-#define ROCKCHIP_VOP2_SMART1 5
-#define ROCKCHIP_VOP2_CLUSTER2 6
-#define ROCKCHIP_VOP2_CLUSTER3 7
-#define ROCKCHIP_VOP2_ESMART2 8
-#define ROCKCHIP_VOP2_ESMART3 9
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/drm_mipi_dsi.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/drm_mipi_dsi.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/drm_mipi_dsi.h (nonexistent)
@@ -1,53 +0,0 @@
-/*
- * MIPI DSI Bus
- *
- * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
- * Authors:
- * Mark Yao <yzq@rock-chips.com>
- *
- * based on include/drm/drm_mipi_dsi.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _DRM_MIPI_DSI_H__
-#define _DRM_MIPI_DSI_H__
-
-/* DSI mode flags */
-
-/* video mode */
-#define MIPI_DSI_MODE_VIDEO (1 << 0)
-/* video burst mode */
-#define MIPI_DSI_MODE_VIDEO_BURST (1 << 1)
-/* video pulse mode */
-#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE (1 << 2)
-/* enable auto vertical count mode */
-#define MIPI_DSI_MODE_VIDEO_AUTO_VERT (1 << 3)
-/* enable hsync-end packets in vsync-pulse and v-porch area */
-#define MIPI_DSI_MODE_VIDEO_HSE (1 << 4)
-/* disable hfront-porch area */
-#define MIPI_DSI_MODE_VIDEO_HFP (1 << 5)
-/* disable hback-porch area */
-#define MIPI_DSI_MODE_VIDEO_HBP (1 << 6)
-/* disable hsync-active area */
-#define MIPI_DSI_MODE_VIDEO_HSA (1 << 7)
-/* flush display FIFO on vsync pulse */
-#define MIPI_DSI_MODE_VSYNC_FLUSH (1 << 8)
-/* disable EoT packets in HS mode */
-#define MIPI_DSI_MODE_EOT_PACKET (1 << 9)
-/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
-#define MIPI_DSI_CLOCK_NON_CONTINUOUS (1 << 10)
-/* transmit data in low power */
-#define MIPI_DSI_MODE_LPM (1 << 11)
-
-#define MIPI_DSI_FMT_RGB888 0
-#define MIPI_DSI_FMT_RGB666 1
-#define MIPI_DSI_FMT_RGB666_PACKED 2
-#define MIPI_DSI_FMT_RGB565 3
-
-#define MIPI_CSI_FMT_RAW8 0x10
-#define MIPI_CSI_FMT_RAW10 0x11
-
-#endif /* __DRM_MIPI_DSI__ */
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/media-bus-format.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/media-bus-format.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/media-bus-format.h (nonexistent)
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-#include "../../uapi/linux/media-bus-format.h"
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk322x.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk322x.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk322x.h (nonexistent)
@@ -1,57 +0,0 @@
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
- * Author: XiaoDong.Huang
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__
-#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-/* the suspend mode */
-#define RKPM_CTR_PWR_DMNS BIT(0)
-#define RKPM_CTR_GTCLKS BIT(1)
-#define RKPM_CTR_PLLS BIT(2)
-#define RKPM_CTR_VOLTS BIT(3)
-#define RKPM_CTR_GPIOS BIT(4)
-#define RKPM_CTR_DDR BIT(5)
-#define RKPM_CTR_PMIC BIT(6)
-
-/* system clk is 24M,and div to min */
-#define RKPM_CTR_SYSCLK_DIV BIT(7)
-/* switch sysclk to 32k, need hardwart support, and div to min */
-#define RKPM_CTR_SYSCLK_32K BIT(8)
-/* switch sysclk to 32k,disable 24M OSC,
- * need hardwart susport. and div to min
- */
-#define RKPM_CTR_SYSCLK_OSC_DIS BIT(9)
-#define RKPM_CTR_VOL_PWM0 BIT(10)
-#define RKPM_CTR_VOL_PWM1 BIT(11)
-#define RKPM_CTR_VOL_PWM2 BIT(12)
-#define RKPM_CTR_VOL_PWM3 BIT(13)
-#define RKPM_CTR_BUS_IDLE BIT(14)
-#define RKPM_CTR_SRAM BIT(15)
-/*Low Power Function Selection*/
-#define RKPM_CTR_IDLESRAM_MD BIT(16)
-#define RKPM_CTR_IDLEAUTO_MD BIT(17)
-#define RKPM_CTR_ARMDP_LPMD BIT(18)
-#define RKPM_CTR_ARMOFF_LPMD BIT(19)
-#define RKPM_CTR_ARMLOGDP_LPMD BIT(20)
-#define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21)
-#define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3288.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3288.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3288.h (nonexistent)
@@ -1,59 +0,0 @@
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
- * Author: Power.xu
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
-#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
-
-/* the suspend mode */
-#define RKPM_CTR_PWR_DMNS (1 << 0)
-#define RKPM_CTR_GTCLKS (1 << 1)
-#define RKPM_CTR_PLLS (1 << 2)
-#define RKPM_CTR_VOLTS (1 << 3)
-#define RKPM_CTR_GPIOS (1 << 4)
-#define RKPM_CTR_DDR (1 << 5)
-#define RKPM_CTR_PMIC (1 << 6)
-/* system clk is 24M,and div to min */
-#define RKPM_CTR_SYSCLK_DIV (1 << 7)
-/* switch sysclk to 32k, need hardwart support, and div to min */
-#define RKPM_CTR_SYSCLK_32K (1 << 8)
-/* switch sysclk to 32k,disable 24M OSC,
- * need hardwart susport. and div to min
- */
-#define RKPM_CTR_SYSCLK_OSC_DIS (1 << 9)
-#define RKPM_CTR_BUS_IDLE (1 << 14)
-#define RKPM_CTR_SRAM (1 << 15)
-/*Low Power Function Selection*/
-#define RKPM_CTR_IDLESRAM_MD (1 << 16)
-#define RKPM_CTR_IDLEAUTO_MD (1 << 17)
-#define RKPM_CTR_ARMDP_LPMD (1 << 18)
-#define RKPM_CTR_ARMOFF_LPMD (1 << 19)
-#define RKPM_CTR_ARMLOGDP_LPMD (1 << 20)
-#define RKPM_CTR_ARMOFF_LOGDP_LPMD (1 << 21)
-#define RKPM_CTR_ARMLOGOFF_DLPMD (1 << 22)
-
-/* the wake up source */
-#define RKPM_ARMINT_WKUP_EN (1 << 0)
-#define RKPM_SDMMC_WKUP_EN (1 << 2)
-#define RKPM_GPIO_WKUP_EN (1 << 3)
-
-/* the pwm regulator */
-#define PWM0_REGULATOR_EN (1 << 0)
-#define PWM1_REGULATOR_EN (1 << 1)
-#define PWM2_REGULATOR_EN (1 << 2)
-#define PWM3_REGULATOR_EN (1 << 3)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3308.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3308.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3308.h (nonexistent)
@@ -1,105 +0,0 @@
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
- * Author: Joseph Chen
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DT_BINDINGS_RK3308_PM_H__
-#define __DT_BINDINGS_RK3308_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-/*
- * RK3308 system suspend mode configure definitions.
- *
- * Driver:
- * These configures are pass to ATF by SMC in:
- * drivers/soc/rockchip/rockchip_pm_config.c
- *
- * DTS:
- * rockchip_suspend: rockchip-suspend {
- * rockchip,sleep-mode-config = <...>;
- * rockchip,wakeup-config = <...>;
- * rockchip,apios-suspend = <...>;
- * rockchip,pwm-regulator-config = <...>;
- * };
- */
-
-/*
- * Suspend mode:
- * rockchip,sleep-mode-config = <...>;
- */
-#define RKPM_ARMOFF BIT(0) /* vdd_arm off */
-#define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */
-#define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */
-#define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */
-#define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */
-#define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */
-#define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */
-#define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */
-#define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */
-#define RKPM_PWM_VOLTAGE_DEFAULT BIT(10) /* pwm regulator default voltage (same with maskrom) */
-#define RKPM_PWM_VOLTAGE_DEFAULT_BS BIT(20) /* pwm regulator default voltage on 0.895v for RK3308BS chip */
-
-/*
- * Regulator mode:
- * rockchip,pwm-regulator-config = <...>;
- */
-#define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */
-
-/*
- * Wakeup source:
- * rockchip,wakeup-config = <...>;
- */
-#define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */
-#define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */
-#define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */
-#define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */
-#define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */
-#define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */
-#define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */
-#define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */
-#define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */
-
-/*
- * Debug control in system suspend:
- * rockchip,sleep-mode-config = <...>;
- */
-#define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */
-#define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */
-#define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */
-#define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */
-#define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */
-#define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */
-#define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */
-#define RKPM_DBG_REG BIT(29) /* verbose regs */
-#define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */
-#define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */
-
-/*
- * GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin:
- * rockchip,apios-suspend = <...>;
- */
-#define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */
-#define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */
-#define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */
-#define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */
-#define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */
-#define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */
-#define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */
-#define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3328.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3328.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3328.h (nonexistent)
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
- * Author: XiaoDong.Huang
- */
-#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
-#define __DT_BINDINGS_ROCKCHIP_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_CTR_VOL_PWM0 BIT(10)
-#define RKPM_SLP_CTR_VOL_PWM1 BIT(11)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3368.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3368.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3368.h (nonexistent)
@@ -1,56 +0,0 @@
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2015, Fuzhou Rockchip Electronics Co., Ltd
- * Author: Tony.Xie
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
-#define __DT_BINDINGS_ROCKCHIP_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_WFI BIT(0)
-#define RKPM_SLP_ARMPD BIT(1)
-#define RKPM_SLP_ARMOFF BIT(2)
-#define RKPM_SLP_ARMOFF_LOGPD BIT(3)
-#define RKPM_SLP_ARMOFF_LOGOFF BIT(4)
-#define RKPM_RUNNING_ARMMODE BIT(5)
-
-/* func ctrl by pmu auto ctr */
-#define RKPM_SLP_PMU_PLLS_PWRDN BIT(8) /* all plls except ddr's pll*/
-#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
-#define RKPM_SLP_PMU_DIS_OSC BIT(10)
-
-/* func ctrl by software set */
-#define RKPM_SLP_SFT_PLLS_DEEP BIT(16) /* all plls except ddr's pll*/
-#define RKPM_SLP_SFT_32K_EXT BIT(17)
-#define RKPM_SLP_SFT_PD_PERI BIT(18)
-#define RKPM_SLP_SFT_PD_NBSCUS BIT(19) /* noboot scus in muti-cluster */
-
-/* the wake up source */
-#define RKPM_CLUSTER_L_WKUP_EN BIT(0)
-#define RKPM_CLUSTER_B_WKUPB_EN BIT(1)
-#define RKPM_GPIO_WKUP_EN BIT(2)
-#define RKPM_SDIO_WKUP_EN BIT(3)
-#define RKPM_SDMMC_WKUP_EN BIT(4)
-#define RKPM_SIM_WKUP_EN BIT(5)
-#define RKPM_TIMER_WKUP_EN BIT(6)
-#define RKPM_USB_WKUP_EN BIT(7)
-#define RKPM_SFT_WKUP_EN BIT(8)
-#define RKPM_WDT_M0_WKUP_EN BIT(9)
-#define RKPM_TIME_OUT_WKUP_EN BIT(10)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3399.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3399.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3399.h (nonexistent)
@@ -1,61 +0,0 @@
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
- * Author: Tony.Xie
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__
-#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__
-
-/* the suspend mode */
-#define RKPM_SLP_WFI (1 << 0)
-#define RKPM_SLP_ARMPD (1 << 1)
-#define RKPM_SLP_PERILPPD (1 << 2)
-#define RKPM_SLP_DDR_RET (1 << 3)
-#define RKPM_SLP_PLLPD (1 << 4)
-#define RKPM_SLP_OSC_DIS (1 << 5)
-#define RKPM_SLP_CENTER_PD (1 << 6)
-#define RKPM_SLP_AP_PWROFF (1 << 7)
-
-/* the wake up source */
-#define RKPM_CLUSTER_L_WKUP_EN (1 << 0)
-#define RKPM_CLUSTER_B_WKUPB_EN (1 << 1)
-#define RKPM_GPIO_WKUP_EN (1 << 2)
-#define RKPM_SDIO_WKUP_EN (1 << 3)
-#define RKPM_SDMMC_WKUP_EN (1 << 4)
-#define RKPM_TIMER_WKUP_EN (1 << 6)
-#define RKPM_USB_WKUP_EN (1 << 7)
-#define RKPM_SFT_WKUP_EN (1 << 8)
-#define RKPM_WDT_M0_WKUP_EN (1 << 9)
-#define RKPM_TIME_OUT_WKUP_EN (1 << 10)
-#define RKPM_PWM_WKUP_EN (1 << 11)
-#define RKPM_PCIE_WKUP_EN (1 << 13)
-#define RKPM_USB_LINESTATE_WKUP_EN (1 << 14)
-
-/* the pwm regulator */
-#define PWM0_REGULATOR_EN (1 << 0)
-#define PWM1_REGULATOR_EN (1 << 1)
-#define PWM2_REGULATOR_EN (1 << 2)
-#define PWM3A_REGULATOR_EN (1 << 3)
-#define PWM3B_REGULATOR_EN (1 << 4)
-
-/* the APIO voltage domain */
-#define RKPM_APIO0_SUSPEND (1 << 0)
-#define RKPM_APIO1_SUSPEND (1 << 1)
-#define RKPM_APIO2_SUSPEND (1 << 2)
-#define RKPM_APIO3_SUSPEND (1 << 3)
-#define RKPM_APIO4_SUSPEND (1 << 4)
-#define RKPM_APIO5_SUSPEND (1 << 5)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3568.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3568.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3568.h (nonexistent)
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2021, Rockchip Electronics Co., Ltd.
- * Author: XiaoDong.Huang
- */
-
-#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3568_H__
-#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3568_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_WFI BIT(0)
-#define RKPM_SLP_ARMOFF BIT(1)
-#define RKPM_SLP_CENTER_OFF BIT(2)
-#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
-#define RKPM_SLP_FROM_UBOOT BIT(4)
-#define RKPM_SLP_PMIC_LP BIT(5)
-#define RKPM_SLP_HW_PLLS_OFF BIT(6)
-#define RKPM_SLP_PMUALIVE_32K BIT(7)
-#define RKPM_SLP_OSC_DIS BIT(8)
-#define RKPM_SLP_32K_EXT BIT(9)
-#define RKPM_SLP_32K_PVTM BIT(10)
-/* the wake up source */
-#define RKPM_CPU0_WKUP_EN BIT(0)
-#define RKPM_CPU1_WKUP_EN BIT(1)
-#define RKPM_CPU2_WKUP_EN BIT(2)
-#define RKPM_CPU3_WKUP_EN BIT(3)
-#define RKPM_GPIO_WKUP_EN BIT(4)
-#define RKPM_UART0_WKUP_EN BIT(5)
-#define RKPM_SDMMC0_WKUP_EN BIT(6)
-#define RKPM_SDMMC1_WKUP_EN BIT(7)
-#define RKPM_SDMMC2_WKUP_EN BIT(8)
-#define RKPM_USB_WKUP_EN BIT(9)
-#define RKPM_PCIE_WKUP_EN BIT(10)
-#define RKPM_VAD_WKUP_EN BIT(11)
-#define RKPM_TIMER_WKUP_EN BIT(12)
-#define RKPM_PWM0_WKUP_EN BIT(13)
-#define RKPM_TIMEOUT_WKUP_EN BIT(14)
-#define RKPM_SFT_WKUP_EN BIT(15)
-#define RKPM_USB_LINESTATE_WKUP_EN BIT(16)
-
-#define RKPM_SLP_LDO1_ON BIT(0)
-#define RKPM_SLP_LDO2_ON BIT(1)
-#define RKPM_SLP_LDO3_ON BIT(2)
-#define RKPM_SLP_LDO4_ON BIT(3)
-#define RKPM_SLP_LDO5_ON BIT(4)
-#define RKPM_SLP_LDO6_ON BIT(5)
-#define RKPM_SLP_LDO7_ON BIT(6)
-#define RKPM_SLP_LDO8_ON BIT(7)
-#define RKPM_SLP_LDO9_ON BIT(8)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3588.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3588.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3588.h (nonexistent)
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2022, Rockchip Electronics Co., Ltd
- * Author: XiaoDong.Huang
- */
-
-#ifndef __DT_BINDINGS_RK3588_PM_H__
-#define __DT_BINDINGS_RK3588_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_ARMPD BIT(0)
-#define RKPM_SLP_ARMOFF BIT(1)
-#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
-#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
-#define RKPM_SLP_ARMOFF_PMUOFF BIT(4)
-
-/* all plls except ddr's pll*/
-#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
-#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
-#define RKPM_SLP_PMU_DIS_OSC BIT(10)
-
-#define RKPM_SLP_CLK_GT BIT(16)
-#define RKPM_SLP_PMIC_LP BIT(17)
-
-#define RKPM_SLP_32K_EXT BIT(24)
-#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
-#define RKPM_SLP_PMU_DBG BIT(26)
-
-/* the wake up source */
-#define RKPM_CPU0_WKUP_EN BIT(0)
-#define RKPM_CPU1_WKUP_EN BIT(1)
-#define RKPM_CPU2_WKUP_EN BIT(2)
-#define RKPM_CPU3_WKUP_EN BIT(3)
-#define RKPM_CPU4_WKUP_EN BIT(4)
-#define RKPM_CPU5_WKUP_EN BIT(5)
-#define RKPM_CPU6_WKUP_EN BIT(6)
-#define RKPM_CPU7_WKUP_EN BIT(7)
-#define RKPM_GPIO_WKUP_EN BIT(8)
-#define RKPM_SDMMC_WKUP_EN BIT(9)
-#define RKPM_SDIO_WKUP_EN BIT(10)
-#define RKPM_USB_WKUP_EN BIT(11)
-#define RKPM_UART0_WKUP_EN BIT(12)
-#define RKPM_VAD_WKUP_EN BIT(13)
-#define RKPM_TIMER_WKUP_EN BIT(14)
-#define RKPM_SYSINT_WKUP_EN BIT(15)
-#define RKPM_TIME_OUT_WKUP_EN BIT(16)
-#define RKPM_PMUMCU_CEC_WKUP_EN BIT(20)
-#define RKPM_PMUMCU_VAD_WKUP_EN BIT(21)
-
-/* io retention config */
-#define RKPM_EMMCIO_RET_EN BIT(0)
-#define RKPM_VCCIO1_RET_EN BIT(1)
-#define RKPM_VCCIO2_RET_EN BIT(2)
-#define RKPM_VCCIO3_RET_EN BIT(3)
-#define RKPM_VCCIO4_RET_EN BIT(4)
-#define RKPM_VCCIO5_RET_EN BIT(5)
-#define RKPM_VCCIO6_RET_EN BIT(6)
-#define RKPM_PMUIO2_RET_EN BIT(7)
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rv1126.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rv1126.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rv1126.h (nonexistent)
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2020, Fuzhou Rockchip Electronics Co., Ltd
- * Author: XiaoDong.Huang
- */
-
-#ifndef __DT_BINDINGS_RV1126_PM_H__
-#define __DT_BINDINGS_RV1126_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_ARMPD BIT(0)
-#define RKPM_SLP_ARMOFF BIT(1)
-#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
-#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
-
-/* all plls except ddr's pll*/
-#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
-#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
-#define RKPM_SLP_PMU_DIS_OSC BIT(10)
-
-#define RKPM_SLP_CLK_GT BIT(16)
-#define RKPM_SLP_PMIC_LP BIT(17)
-
-#define RKPM_SLP_32K_EXT BIT(24)
-#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
-#define RKPM_SLP_PMU_DBG BIT(26)
-
-/* the wake up source */
-#define RKPM_CPU0_WKUP_EN BIT(0)
-#define RKPM_CPU1_WKUP_EN BIT(1)
-#define RKPM_CPU2_WKUP_EN BIT(2)
-#define RKPM_CPU3_WKUP_EN BIT(3)
-#define RKPM_GPIO_WKUP_EN BIT(4)
-#define RKPM_SDMMC_WKUP_EN BIT(5)
-#define RKPM_SDIO_WKUP_EN BIT(6)
-#define RKPM_USB_WKUP_EN BIT(7)
-#define RKPM_UART1_WKUP_EN BIT(8)
-#define RKPM_SYSINT_WKUP_EN BIT(9)
-#define RKPM_TIME_OUT_WKUP_EN BIT(10)
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk1808.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk1808.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk1808.h (nonexistent)
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
- * Author: XiaoDong.Huang
- */
-
-#ifndef __DT_BINDINGS_RK1808_PM_H__
-#define __DT_BINDINGS_RK1808_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_ARMPD BIT(0)
-#define RKPM_SLP_ARMOFF BIT(1)
-#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
-#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
-
-/* all plls except ddr's pll*/
-#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
-#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
-#define RKPM_SLP_PMU_DIS_OSC BIT(10)
-
-#define RKPM_SLP_CLK_GT BIT(16)
-#define RKPM_SLP_PMIC_LP BIT(17)
-
-#define RKPM_SLP_32K_EXT BIT(24)
-#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
-#define RKPM_SLP_PMU_DBG BIT(26)
-
-/* the wake up source */
-#define RKPM_CLUSTER_WKUP_EN BIT(0)
-#define RKPM_GPIO_WKUP_EN BIT(2)
-#define RKPM_SDIO_WKUP_EN BIT(3)
-#define RKPM_SDMMC_WKUP_EN BIT(4)
-#define RKPM_UART0_WKUP_EN BIT(5)
-#define RKPM_TIMER_WKUP_EN BIT(6)
-#define RKPM_USB_WKUP_EN BIT(7)
-#define RKPM_SFT_WKUP_EN BIT(8)
-#define RKPM_VAD_WKUP_EN BIT(9)
-#define RKPM_TIME_OUT_WKUP_EN BIT(10)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-px30.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-px30.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-px30.h (nonexistent)
@@ -1,53 +0,0 @@
-/*
- * Header providing constants for Rockchip suspend bindings.
- *
- * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
- * Author: XiaoDong.Huang
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
-#define __DT_BINDINGS_ROCKCHIP_PM_H__
-/******************************bits ops************************************/
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define RKPM_SLP_ARMPD BIT(0)
-#define RKPM_SLP_ARMOFF BIT(1)
-#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
-#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
-
-/* all plls except ddr's pll*/
-#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
-#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
-#define RKPM_SLP_PMU_DIS_OSC BIT(10)
-
-#define RKPM_SLP_CLK_GT BIT(16)
-#define RKPM_SLP_PMIC_LP BIT(17)
-
-#define RKPM_SLP_32K_EXT BIT(24)
-#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
-#define RKPM_SLP_PMU_DBG BIT(26)
-
-/* the wake up source */
-#define RKPM_CLUSTER_WKUP_EN BIT(0)
-#define RKPM_GPIO_WKUP_EN BIT(2)
-#define RKPM_SDIO_WKUP_EN BIT(3)
-#define RKPM_SDMMC_WKUP_EN BIT(4)
-#define RKPM_UART0_WKUP_EN BIT(5)
-#define RKPM_TIMER_WKUP_EN BIT(6)
-#define RKPM_USB_WKUP_EN BIT(7)
-#define RKPM_SFT_WKUP_EN BIT(8)
-#define RKPM_TIME_OUT_WKUP_EN BIT(10)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/clock/rk3588-cru.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/clock/rk3588-cru.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/clock/rk3588-cru.h (nonexistent)
@@ -1,1497 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
- * Author: Elaine Zhang <zhangqing@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
-
-/* cru-clocks indices */
-
-/* cru plls */
-#define PLL_B0PLL 1
-#define PLL_B1PLL 2
-#define PLL_LPLL 3
-#define PLL_V0PLL 4
-#define PLL_AUPLL 5
-#define PLL_CPLL 6
-#define PLL_GPLL 7
-#define PLL_NPLL 8
-#define PLL_PPLL 9
-#define ARMCLK_L 10
-#define ARMCLK_B01 11
-#define ARMCLK_B23 12
-
-/* cru clocks */
-#define PCLK_BIGCORE0_ROOT 20
-#define PCLK_BIGCORE0_PVTM 21
-#define PCLK_BIGCORE1_ROOT 22
-#define PCLK_BIGCORE1_PVTM 23
-#define PCLK_DSU_S_ROOT 24
-#define PCLK_DSU_ROOT 25
-#define PCLK_DSU_NS_ROOT 26
-#define PCLK_LITCORE_PVTM 27
-#define PCLK_DBG 28
-#define PCLK_DSU 29
-#define PCLK_S_DAPLITE 30
-#define PCLK_M_DAPLITE 31
-#define MBIST_MCLK_PDM1 32
-#define MBIST_CLK_ACDCDIG 33
-#define HCLK_I2S2_2CH 34
-#define HCLK_I2S3_2CH 35
-#define CLK_I2S2_2CH_SRC 36
-#define CLK_I2S2_2CH_FRAC 37
-#define CLK_I2S2_2CH 38
-#define MCLK_I2S2_2CH 39
-#define I2S2_2CH_MCLKOUT 40
-#define CLK_DAC_ACDCDIG 41
-#define CLK_I2S3_2CH_SRC 42
-#define CLK_I2S3_2CH_FRAC 43
-#define CLK_I2S3_2CH 44
-#define MCLK_I2S3_2CH 45
-#define I2S3_2CH_MCLKOUT 46
-#define PCLK_ACDCDIG 47
-#define HCLK_I2S0_8CH 48
-#define CLK_I2S0_8CH_TX_SRC 49
-#define CLK_I2S0_8CH_TX_FRAC 50
-#define MCLK_I2S0_8CH_TX 51
-#define CLK_I2S0_8CH_TX 52
-#define CLK_I2S0_8CH_RX_SRC 53
-#define CLK_I2S0_8CH_RX_FRAC 54
-#define MCLK_I2S0_8CH_RX 55
-#define CLK_I2S0_8CH_RX 56
-#define I2S0_8CH_MCLKOUT 57
-#define HCLK_PDM1 58
-#define MCLK_PDM1 59
-#define HCLK_AUDIO_ROOT 60
-#define PCLK_AUDIO_ROOT 61
-#define HCLK_SPDIF0 62
-#define CLK_SPDIF0_SRC 63
-#define CLK_SPDIF0_FRAC 64
-#define MCLK_SPDIF0 65
-#define CLK_SPDIF0 66
-#define CLK_SPDIF1 67
-#define HCLK_SPDIF1 68
-#define CLK_SPDIF1_SRC 69
-#define CLK_SPDIF1_FRAC 70
-#define MCLK_SPDIF1 71
-#define ACLK_AV1_ROOT 72
-#define ACLK_AV1 73
-#define PCLK_AV1_ROOT 74
-#define PCLK_AV1 75
-#define PCLK_MAILBOX0 76
-#define PCLK_MAILBOX1 77
-#define PCLK_MAILBOX2 78
-#define PCLK_PMU2 79
-#define PCLK_PMUCM0_INTMUX 80
-#define PCLK_DDRCM0_INTMUX 81
-#define PCLK_TOP 82
-#define PCLK_PWM1 83
-#define CLK_PWM1 84
-#define CLK_PWM1_CAPTURE 85
-#define PCLK_PWM2 86
-#define CLK_PWM2 87
-#define CLK_PWM2_CAPTURE 88
-#define PCLK_PWM3 89
-#define CLK_PWM3 90
-#define CLK_PWM3_CAPTURE 91
-#define PCLK_BUSTIMER0 92
-#define PCLK_BUSTIMER1 93
-#define CLK_BUS_TIMER_ROOT 94
-#define CLK_BUSTIMER0 95
-#define CLK_BUSTIMER1 96
-#define CLK_BUSTIMER2 97
-#define CLK_BUSTIMER3 98
-#define CLK_BUSTIMER4 99
-#define CLK_BUSTIMER5 100
-#define CLK_BUSTIMER6 101
-#define CLK_BUSTIMER7 102
-#define CLK_BUSTIMER8 103
-#define CLK_BUSTIMER9 104
-#define CLK_BUSTIMER10 105
-#define CLK_BUSTIMER11 106
-#define PCLK_WDT0 107
-#define TCLK_WDT0 108
-#define PCLK_CAN0 111
-#define CLK_CAN0 112
-#define PCLK_CAN1 113
-#define CLK_CAN1 114
-#define PCLK_CAN2 115
-#define CLK_CAN2 116
-#define ACLK_DECOM 117
-#define PCLK_DECOM 118
-#define DCLK_DECOM 119
-#define ACLK_DMAC0 120
-#define ACLK_DMAC1 121
-#define ACLK_DMAC2 122
-#define ACLK_BUS_ROOT 123
-#define ACLK_GIC 124
-#define PCLK_GPIO1 125
-#define DBCLK_GPIO1 126
-#define PCLK_GPIO2 127
-#define DBCLK_GPIO2 128
-#define PCLK_GPIO3 129
-#define DBCLK_GPIO3 130
-#define PCLK_GPIO4 131
-#define DBCLK_GPIO4 132
-#define PCLK_I2C1 133
-#define PCLK_I2C2 134
-#define PCLK_I2C3 135
-#define PCLK_I2C4 136
-#define PCLK_I2C5 137
-#define PCLK_I2C6 138
-#define PCLK_I2C7 139
-#define PCLK_I2C8 140
-#define CLK_I2C1 141
-#define CLK_I2C2 142
-#define CLK_I2C3 143
-#define CLK_I2C4 144
-#define CLK_I2C5 145
-#define CLK_I2C6 146
-#define CLK_I2C7 147
-#define CLK_I2C8 148
-#define PCLK_OTPC_NS 149
-#define CLK_OTPC_NS 150
-#define CLK_OTPC_ARB 151
-#define CLK_OTPC_AUTO_RD_G 152
-#define CLK_OTP_PHY_G 153
-#define PCLK_SARADC 156
-#define CLK_SARADC 157
-#define PCLK_SPI0 158
-#define PCLK_SPI1 159
-#define PCLK_SPI2 160
-#define PCLK_SPI3 161
-#define PCLK_SPI4 162
-#define CLK_SPI0 163
-#define CLK_SPI1 164
-#define CLK_SPI2 165
-#define CLK_SPI3 166
-#define CLK_SPI4 167
-#define ACLK_SPINLOCK 168
-#define PCLK_TSADC 169
-#define CLK_TSADC 170
-#define PCLK_UART1 171
-#define PCLK_UART2 172
-#define PCLK_UART3 173
-#define PCLK_UART4 174
-#define PCLK_UART5 175
-#define PCLK_UART6 176
-#define PCLK_UART7 177
-#define PCLK_UART8 178
-#define PCLK_UART9 179
-#define CLK_UART1_SRC 180
-#define CLK_UART1_FRAC 181
-#define CLK_UART1 182
-#define SCLK_UART1 183
-#define CLK_UART2_SRC 184
-#define CLK_UART2_FRAC 185
-#define CLK_UART2 186
-#define SCLK_UART2 187
-#define CLK_UART3_SRC 188
-#define CLK_UART3_FRAC 189
-#define CLK_UART3 190
-#define SCLK_UART3 191
-#define CLK_UART4_SRC 192
-#define CLK_UART4_FRAC 193
-#define CLK_UART4 194
-#define SCLK_UART4 195
-#define CLK_UART5_SRC 196
-#define CLK_UART5_FRAC 197
-#define CLK_UART5 198
-#define SCLK_UART5 199
-#define CLK_UART6_SRC 200
-#define CLK_UART6_FRAC 201
-#define CLK_UART6 202
-#define SCLK_UART6 203
-#define CLK_UART7_SRC 204
-#define CLK_UART7_FRAC 205
-#define CLK_UART7 206
-#define SCLK_UART7 207
-#define CLK_UART8_SRC 208
-#define CLK_UART8_FRAC 209
-#define CLK_UART8 210
-#define SCLK_UART8 211
-#define CLK_UART9_SRC 212
-#define CLK_UART9_FRAC 213
-#define CLK_UART9 214
-#define SCLK_UART9 215
-#define ACLK_CENTER_ROOT 216
-#define ACLK_CENTER_LOW_ROOT 217
-#define HCLK_CENTER_ROOT 218
-#define PCLK_CENTER_ROOT 219
-#define ACLK_DMA2DDR 220
-#define ACLK_DDR_SHAREMEM 221
-#define ACLK_CENTER_S200_ROOT 222
-#define ACLK_CENTER_S400_ROOT 223
-#define FCLK_DDR_CM0_CORE 224
-#define CLK_DDR_TIMER_ROOT 225
-#define CLK_DDR_TIMER0 226
-#define CLK_DDR_TIMER1 227
-#define TCLK_WDT_DDR 228
-#define CLK_DDR_CM0_RTC 228
-#define PCLK_WDT 230
-#define PCLK_TIMER 231
-#define PCLK_DMA2DDR 232
-#define PCLK_SHAREMEM 233
-#define CLK_50M_SRC 234
-#define CLK_100M_SRC 235
-#define CLK_150M_SRC 236
-#define CLK_200M_SRC 237
-#define CLK_250M_SRC 238
-#define CLK_300M_SRC 239
-#define CLK_350M_SRC 240
-#define CLK_400M_SRC 241
-#define CLK_450M_SRC 242
-#define CLK_500M_SRC 243
-#define CLK_600M_SRC 244
-#define CLK_650M_SRC 245
-#define CLK_700M_SRC 246
-#define CLK_800M_SRC 247
-#define CLK_1000M_SRC 248
-#define CLK_1200M_SRC 249
-#define ACLK_TOP_M300_ROOT 250
-#define ACLK_TOP_M500_ROOT 251
-#define ACLK_TOP_M400_ROOT 252
-#define ACLK_TOP_S200_ROOT 253
-#define ACLK_TOP_S400_ROOT 254
-#define CLK_MIPI_CAMARAOUT_M0 255
-#define CLK_MIPI_CAMARAOUT_M1 256
-#define CLK_MIPI_CAMARAOUT_M2 257
-#define CLK_MIPI_CAMARAOUT_M3 258
-#define CLK_MIPI_CAMARAOUT_M4 259
-#define MCLK_GMAC0_OUT 260
-#define REFCLKO25M_ETH0_OUT 261
-#define REFCLKO25M_ETH1_OUT 262
-#define CLK_CIFOUT_OUT 263
-#define PCLK_MIPI_DCPHY0 264
-#define PCLK_MIPI_DCPHY1 265
-#define PCLK_CSIPHY0 268
-#define PCLK_CSIPHY1 269
-#define ACLK_TOP_ROOT 270
-#define PCLK_TOP_ROOT 271
-#define ACLK_LOW_TOP_ROOT 272
-#define PCLK_CRU 273
-#define PCLK_GPU_ROOT 274
-#define CLK_GPU_SRC 275
-#define CLK_GPU 276
-#define CLK_GPU_COREGROUP 277
-#define CLK_GPU_STACKS 278
-#define PCLK_GPU_PVTM 279
-#define CLK_GPU_PVTM 280
-#define CLK_CORE_GPU_PVTM 281
-#define PCLK_GPU_GRF 282
-#define ACLK_ISP1_ROOT 283
-#define HCLK_ISP1_ROOT 284
-#define CLK_ISP1_CORE 285
-#define CLK_ISP1_CORE_MARVIN 286
-#define CLK_ISP1_CORE_VICAP 287
-#define ACLK_ISP1 288
-#define HCLK_ISP1 289
-#define ACLK_NPU1 290
-#define HCLK_NPU1 291
-#define ACLK_NPU2 292
-#define HCLK_NPU2 293
-#define HCLK_NPU_CM0_ROOT 294
-#define FCLK_NPU_CM0_CORE 295
-#define CLK_NPU_CM0_RTC 296
-#define PCLK_NPU_PVTM 297
-#define PCLK_NPU_GRF 298
-#define CLK_NPU_PVTM 299
-#define CLK_CORE_NPU_PVTM 300
-#define ACLK_NPU0 301
-#define HCLK_NPU0 302
-#define HCLK_NPU_ROOT 303
-#define CLK_NPU_DSU0 304
-#define PCLK_NPU_ROOT 305
-#define PCLK_NPU_TIMER 306
-#define CLK_NPUTIMER_ROOT 307
-#define CLK_NPUTIMER0 308
-#define CLK_NPUTIMER1 309
-#define PCLK_NPU_WDT 310
-#define TCLK_NPU_WDT 311
-#define HCLK_EMMC 312
-#define ACLK_EMMC 313
-#define CCLK_EMMC 314
-#define BCLK_EMMC 315
-#define TMCLK_EMMC 316
-#define SCLK_SFC 317
-#define HCLK_SFC 318
-#define HCLK_SFC_XIP 319
-#define HCLK_NVM_ROOT 320
-#define ACLK_NVM_ROOT 321
-#define CLK_GMAC0_PTP_REF 322
-#define CLK_GMAC1_PTP_REF 323
-#define CLK_GMAC_125M 324
-#define CLK_GMAC_50M 325
-#define ACLK_PHP_GIC_ITS 326
-#define ACLK_MMU_PCIE 327
-#define ACLK_MMU_PHP 328
-#define ACLK_PCIE_4L_DBI 329
-#define ACLK_PCIE_2L_DBI 330
-#define ACLK_PCIE_1L0_DBI 331
-#define ACLK_PCIE_1L1_DBI 332
-#define ACLK_PCIE_1L2_DBI 333
-#define ACLK_PCIE_4L_MSTR 334
-#define ACLK_PCIE_2L_MSTR 335
-#define ACLK_PCIE_1L0_MSTR 336
-#define ACLK_PCIE_1L1_MSTR 337
-#define ACLK_PCIE_1L2_MSTR 338
-#define ACLK_PCIE_4L_SLV 339
-#define ACLK_PCIE_2L_SLV 340
-#define ACLK_PCIE_1L0_SLV 341
-#define ACLK_PCIE_1L1_SLV 342
-#define ACLK_PCIE_1L2_SLV 343
-#define PCLK_PCIE_4L 344
-#define PCLK_PCIE_2L 345
-#define PCLK_PCIE_1L0 347
-#define PCLK_PCIE_1L1 348
-#define PCLK_PCIE_1L2 349
-#define CLK_PCIE_AUX0 350
-#define CLK_PCIE_AUX1 351
-#define CLK_PCIE_AUX2 352
-#define CLK_PCIE_AUX3 353
-#define CLK_PCIE_AUX4 354
-#define CLK_PIPEPHY0_REF 355
-#define CLK_PIPEPHY1_REF 356
-#define CLK_PIPEPHY2_REF 357
-#define PCLK_PHP_ROOT 358
-#define PCLK_GMAC0 359
-#define PCLK_GMAC1 360
-#define ACLK_PCIE_ROOT 361
-#define ACLK_PHP_ROOT 362
-#define ACLK_PCIE_BRIDGE 363
-#define ACLK_GMAC0 364
-#define ACLK_GMAC1 365
-#define CLK_PMALIVE0 366
-#define CLK_PMALIVE1 367
-#define CLK_PMALIVE2 368
-#define ACLK_SATA0 369
-#define ACLK_SATA1 370
-#define ACLK_SATA2 371
-#define CLK_RXOOB0 372
-#define CLK_RXOOB1 373
-#define CLK_RXOOB2 374
-#define ACLK_USB3OTG2 375
-#define SUSPEND_CLK_USB3OTG2 376
-#define REF_CLK_USB3OTG2 377
-#define CLK_UTMI_OTG2 378
-#define CLK_PIPEPHY0_PIPE_G 379
-#define CLK_PIPEPHY1_PIPE_G 380
-#define CLK_PIPEPHY2_PIPE_G 381
-#define CLK_PIPEPHY0_PIPE_ASIC_G 382
-#define CLK_PIPEPHY1_PIPE_ASIC_G 383
-#define CLK_PIPEPHY2_PIPE_ASIC_G 384
-#define CLK_PIPEPHY2_PIPE_U3_G 385
-#define CLK_PCIE1L2_PIPE 386
-#define CLK_PCIE4L_PIPE 387
-#define CLK_PCIE2L_PIPE 388
-#define PCLK_PCIE_COMBO_PIPE_PHY0 389
-#define PCLK_PCIE_COMBO_PIPE_PHY1 390
-#define PCLK_PCIE_COMBO_PIPE_PHY2 391
-#define PCLK_PCIE_COMBO_PIPE_PHY 392
-#define HCLK_RGA3_1 393
-#define ACLK_RGA3_1 394
-#define CLK_RGA3_1_CORE 395
-#define ACLK_RGA3_ROOT 396
-#define HCLK_RGA3_ROOT 397
-#define ACLK_RKVDEC_CCU 398
-#define HCLK_RKVDEC0 399
-#define ACLK_RKVDEC0 400
-#define CLK_RKVDEC0_CA 401
-#define CLK_RKVDEC0_HEVC_CA 402
-#define CLK_RKVDEC0_CORE 403
-#define HCLK_RKVDEC1 404
-#define ACLK_RKVDEC1 405
-#define CLK_RKVDEC1_CA 406
-#define CLK_RKVDEC1_HEVC_CA 407
-#define CLK_RKVDEC1_CORE 408
-#define HCLK_SDIO 409
-#define CCLK_SRC_SDIO 410
-#define ACLK_USB_ROOT 411
-#define HCLK_USB_ROOT 412
-#define HCLK_HOST0 413
-#define HCLK_HOST_ARB0 414
-#define HCLK_HOST1 415
-#define HCLK_HOST_ARB1 416
-#define ACLK_USB3OTG0 417
-#define SUSPEND_CLK_USB3OTG0 418
-#define REF_CLK_USB3OTG0 419
-#define ACLK_USB3OTG1 420
-#define SUSPEND_CLK_USB3OTG1 421
-#define REF_CLK_USB3OTG1 422
-#define UTMI_OHCI_CLK48_HOST0 423
-#define UTMI_OHCI_CLK48_HOST1 424
-#define HCLK_IEP2P0 425
-#define ACLK_IEP2P0 426
-#define CLK_IEP2P0_CORE 427
-#define ACLK_JPEG_ENCODER0 428
-#define HCLK_JPEG_ENCODER0 429
-#define ACLK_JPEG_ENCODER1 430
-#define HCLK_JPEG_ENCODER1 431
-#define ACLK_JPEG_ENCODER2 432
-#define HCLK_JPEG_ENCODER2 433
-#define ACLK_JPEG_ENCODER3 434
-#define HCLK_JPEG_ENCODER3 435
-#define ACLK_JPEG_DECODER 436
-#define HCLK_JPEG_DECODER 437
-#define HCLK_RGA2 438
-#define ACLK_RGA2 439
-#define CLK_RGA2_CORE 440
-#define HCLK_RGA3_0 441
-#define ACLK_RGA3_0 442
-#define CLK_RGA3_0_CORE 443
-#define ACLK_VDPU_ROOT 444
-#define ACLK_VDPU_LOW_ROOT 445
-#define HCLK_VDPU_ROOT 446
-#define ACLK_JPEG_DECODER_ROOT 447
-#define ACLK_VPU 448
-#define HCLK_VPU 449
-#define HCLK_RKVENC0_ROOT 450
-#define ACLK_RKVENC0_ROOT 451
-#define HCLK_RKVENC0 452
-#define ACLK_RKVENC0 453
-#define CLK_RKVENC0_CORE 454
-#define HCLK_RKVENC1_ROOT 455
-#define ACLK_RKVENC1_ROOT 456
-#define HCLK_RKVENC1 457
-#define ACLK_RKVENC1 458
-#define CLK_RKVENC1_CORE 459
-#define ICLK_CSIHOST01 460
-#define ICLK_CSIHOST0 461
-#define ICLK_CSIHOST1 462
-#define PCLK_CSI_HOST_0 463
-#define PCLK_CSI_HOST_1 464
-#define PCLK_CSI_HOST_2 465
-#define PCLK_CSI_HOST_3 466
-#define PCLK_CSI_HOST_4 467
-#define PCLK_CSI_HOST_5 468
-#define ACLK_FISHEYE0 469
-#define HCLK_FISHEYE0 470
-#define CLK_FISHEYE0_CORE 471
-#define ACLK_FISHEYE1 472
-#define HCLK_FISHEYE1 473
-#define CLK_FISHEYE1_CORE 474
-#define CLK_ISP0_CORE 475
-#define CLK_ISP0_CORE_MARVIN 476
-#define CLK_ISP0_CORE_VICAP 477
-#define ACLK_ISP0 478
-#define HCLK_ISP0 479
-#define ACLK_VI_ROOT 480
-#define HCLK_VI_ROOT 481
-#define PCLK_VI_ROOT 482
-#define DCLK_VICAP 483
-#define ACLK_VICAP 484
-#define HCLK_VICAP 485
-#define PCLK_DP0 486
-#define PCLK_DP1 487
-#define PCLK_S_DP0 488
-#define PCLK_S_DP1 489
-#define CLK_DP0 490
-#define CLK_DP1 491
-#define HCLK_HDCP_KEY0 492
-#define ACLK_HDCP0 493
-#define HCLK_HDCP0 494
-#define PCLK_HDCP0 495
-#define HCLK_I2S4_8CH 496
-#define ACLK_TRNG0 497
-#define PCLK_TRNG0 498
-#define ACLK_VO0_ROOT 499
-#define HCLK_VO0_ROOT 500
-#define HCLK_VO0_S_ROOT 501
-#define PCLK_VO0_ROOT 502
-#define PCLK_VO0_S_ROOT 503
-#define PCLK_VO0GRF 504
-#define CLK_I2S4_8CH_TX_SRC 505
-#define CLK_I2S4_8CH_TX_FRAC 506
-#define MCLK_I2S4_8CH_TX 507
-#define CLK_I2S4_8CH_TX 508
-#define HCLK_I2S8_8CH 510
-#define CLK_I2S8_8CH_TX_SRC 511
-#define CLK_I2S8_8CH_TX_FRAC 512
-#define MCLK_I2S8_8CH_TX 513
-#define CLK_I2S8_8CH_TX 514
-#define HCLK_SPDIF2_DP0 516
-#define CLK_SPDIF2_DP0_SRC 517
-#define CLK_SPDIF2_DP0_FRAC 518
-#define MCLK_SPDIF2_DP0 519
-#define CLK_SPDIF2_DP0 520
-#define MCLK_SPDIF2 521
-#define HCLK_SPDIF5_DP1 522
-#define CLK_SPDIF5_DP1_SRC 523
-#define CLK_SPDIF5_DP1_FRAC 524
-#define MCLK_SPDIF5_DP1 525
-#define CLK_SPDIF5_DP1 526
-#define MCLK_SPDIF5 527
-#define PCLK_EDP0 528
-#define CLK_EDP0_24M 529
-#define CLK_EDP0_200M 530
-#define PCLK_EDP1 531
-#define CLK_EDP1_24M 532
-#define CLK_EDP1_200M 533
-#define HCLK_HDCP_KEY1 534
-#define ACLK_HDCP1 535
-#define HCLK_HDCP1 536
-#define PCLK_HDCP1 537
-#define ACLK_HDMIRX 538
-#define PCLK_HDMIRX 539
-#define CLK_HDMIRX_REF 540
-#define CLK_HDMIRX_AUD_SRC 541
-#define CLK_HDMIRX_AUD_FRAC 542
-#define CLK_HDMIRX_AUD 543
-#define CLK_HDMIRX_AUD_P_MUX 544
-#define PCLK_HDMITX0 545
-#define CLK_HDMITX0_EARC 546
-#define CLK_HDMITX0_REF 547
-#define PCLK_HDMITX1 548
-#define CLK_HDMITX1_EARC 549
-#define CLK_HDMITX1_REF 550
-#define CLK_HDMITRX_REFSRC 551
-#define ACLK_TRNG1 552
-#define PCLK_TRNG1 553
-#define ACLK_HDCP1_ROOT 554
-#define ACLK_HDMIRX_ROOT 555
-#define HCLK_VO1_ROOT 556
-#define HCLK_VO1_S_ROOT 557
-#define PCLK_VO1_ROOT 558
-#define PCLK_VO1_S_ROOT 559
-#define PCLK_S_EDP0 560
-#define PCLK_S_EDP1 561
-#define PCLK_S_HDMIRX 562
-#define HCLK_I2S10_8CH 563
-#define CLK_I2S10_8CH_RX_SRC 564
-#define CLK_I2S10_8CH_RX_FRAC 565
-#define CLK_I2S10_8CH_RX 566
-#define MCLK_I2S10_8CH_RX 567
-#define HCLK_I2S7_8CH 568
-#define CLK_I2S7_8CH_RX_SRC 569
-#define CLK_I2S7_8CH_RX_FRAC 570
-#define CLK_I2S7_8CH_RX 571
-#define MCLK_I2S7_8CH_RX 572
-#define HCLK_I2S9_8CH 574
-#define CLK_I2S9_8CH_RX_SRC 575
-#define CLK_I2S9_8CH_RX_FRAC 576
-#define CLK_I2S9_8CH_RX 577
-#define MCLK_I2S9_8CH_RX 578
-#define CLK_I2S5_8CH_TX_SRC 579
-#define CLK_I2S5_8CH_TX_FRAC 580
-#define CLK_I2S5_8CH_TX 581
-#define MCLK_I2S5_8CH_TX 582
-#define HCLK_I2S5_8CH 584
-#define CLK_I2S6_8CH_TX_SRC 585
-#define CLK_I2S6_8CH_TX_FRAC 586
-#define CLK_I2S6_8CH_TX 587
-#define MCLK_I2S6_8CH_TX 588
-#define CLK_I2S6_8CH_RX_SRC 589
-#define CLK_I2S6_8CH_RX_FRAC 590
-#define CLK_I2S6_8CH_RX 591
-#define MCLK_I2S6_8CH_RX 592
-#define I2S6_8CH_MCLKOUT 593
-#define HCLK_I2S6_8CH 594
-#define HCLK_SPDIF3 595
-#define CLK_SPDIF3_SRC 596
-#define CLK_SPDIF3_FRAC 597
-#define CLK_SPDIF3 598
-#define MCLK_SPDIF3 599
-#define HCLK_SPDIF4 600
-#define CLK_SPDIF4_SRC 601
-#define CLK_SPDIF4_FRAC 602
-#define CLK_SPDIF4 603
-#define MCLK_SPDIF4 604
-#define HCLK_SPDIFRX0 605
-#define MCLK_SPDIFRX0 606
-#define HCLK_SPDIFRX1 607
-#define MCLK_SPDIFRX1 608
-#define HCLK_SPDIFRX2 609
-#define MCLK_SPDIFRX2 610
-#define ACLK_VO1USB_TOP_ROOT 611
-#define HCLK_VO1USB_TOP_ROOT 612
-#define CLK_HDMIHDP0 613
-#define CLK_HDMIHDP1 614
-#define PCLK_HDPTX0 615
-#define PCLK_HDPTX1 616
-#define PCLK_USBDPPHY0 617
-#define PCLK_USBDPPHY1 618
-#define ACLK_VOP_ROOT 619
-#define ACLK_VOP_LOW_ROOT 620
-#define HCLK_VOP_ROOT 621
-#define PCLK_VOP_ROOT 622
-#define HCLK_VOP 623
-#define ACLK_VOP 624
-#define DCLK_VOP0_SRC 625
-#define DCLK_VOP1_SRC 626
-#define DCLK_VOP2_SRC 627
-#define DCLK_VOP0 628
-#define DCLK_VOP1 629
-#define DCLK_VOP2 630
-#define DCLK_VOP3 631
-#define PCLK_DSIHOST0 632
-#define PCLK_DSIHOST1 633
-#define CLK_DSIHOST0 634
-#define CLK_DSIHOST1 635
-#define CLK_VOP_PMU 636
-#define ACLK_VOP_DOBY 637
-#define ACLK_VOP_DIV2_SRC 638
-#define CLK_USBDP_PHY0_IMMORTAL 639
-#define CLK_USBDP_PHY1_IMMORTAL 640
-#define CLK_PMU0 641
-#define PCLK_PMU0 642
-#define PCLK_PMU0IOC 643
-#define PCLK_GPIO0 644
-#define DBCLK_GPIO0 645
-#define PCLK_I2C0 646
-#define CLK_I2C0 647
-#define HCLK_I2S1_8CH 648
-#define CLK_I2S1_8CH_TX_SRC 649
-#define CLK_I2S1_8CH_TX_FRAC 650
-#define CLK_I2S1_8CH_TX 651
-#define MCLK_I2S1_8CH_TX 652
-#define CLK_I2S1_8CH_RX_SRC 653
-#define CLK_I2S1_8CH_RX_FRAC 654
-#define CLK_I2S1_8CH_RX 655
-#define MCLK_I2S1_8CH_RX 656
-#define I2S1_8CH_MCLKOUT 657
-#define CLK_PMU1_50M_SRC 658
-#define CLK_PMU1_100M_SRC 659
-#define CLK_PMU1_200M_SRC 660
-#define CLK_PMU1_300M_SRC 661
-#define CLK_PMU1_400M_SRC 662
-#define HCLK_PMU1_ROOT 663
-#define PCLK_PMU1_ROOT 664
-#define PCLK_PMU0_ROOT 665
-#define HCLK_PMU_CM0_ROOT 666
-#define PCLK_PMU1 667
-#define CLK_DDR_FAIL_SAFE 668
-#define CLK_PMU1 669
-#define HCLK_PDM0 670
-#define MCLK_PDM0 671
-#define HCLK_VAD 672
-#define FCLK_PMU_CM0_CORE 673
-#define CLK_PMU_CM0_RTC 674
-#define PCLK_PMU1_IOC 675
-#define PCLK_PMU1PWM 676
-#define CLK_PMU1PWM 677
-#define CLK_PMU1PWM_CAPTURE 678
-#define PCLK_PMU1TIMER 679
-#define CLK_PMU1TIMER_ROOT 680
-#define CLK_PMU1TIMER0 681
-#define CLK_PMU1TIMER1 682
-#define CLK_UART0_SRC 683
-#define CLK_UART0_FRAC 684
-#define CLK_UART0 685
-#define SCLK_UART0 686
-#define PCLK_UART0 687
-#define PCLK_PMU1WDT 688
-#define TCLK_PMU1WDT 689
-#define CLK_CR_PARA 690
-#define CLK_USB2PHY_HDPTXRXPHY_REF 693
-#define CLK_USBDPPHY_MIPIDCPPHY_REF 694
-#define CLK_REF_PIPE_PHY0_OSC_SRC 695
-#define CLK_REF_PIPE_PHY1_OSC_SRC 696
-#define CLK_REF_PIPE_PHY2_OSC_SRC 697
-#define CLK_REF_PIPE_PHY0_PLL_SRC 698
-#define CLK_REF_PIPE_PHY1_PLL_SRC 699
-#define CLK_REF_PIPE_PHY2_PLL_SRC 700
-#define CLK_REF_PIPE_PHY0 701
-#define CLK_REF_PIPE_PHY1 702
-#define CLK_REF_PIPE_PHY2 703
-#define SCLK_SDIO_DRV 704
-#define SCLK_SDIO_SAMPLE 705
-#define SCLK_SDMMC_DRV 706
-#define SCLK_SDMMC_SAMPLE 707
-#define CLK_PCIE1L0_PIPE 708
-#define CLK_PCIE1L1_PIPE 709
-#define CLK_BIGCORE0_PVTM 710
-#define CLK_CORE_BIGCORE0_PVTM 711
-#define CLK_BIGCORE1_PVTM 712
-#define CLK_CORE_BIGCORE1_PVTM 713
-#define CLK_LITCORE_PVTM 714
-#define CLK_CORE_LITCORE_PVTM 715
-#define CLK_AUX16M_0 716
-#define CLK_AUX16M_1 717
-#define CLK_PHY0_REF_ALT_P 718
-#define CLK_PHY0_REF_ALT_M 719
-#define CLK_PHY1_REF_ALT_P 720
-#define CLK_PHY1_REF_ALT_M 721
-
-#define CLK_NR_CLKS (CLK_PHY1_REF_ALT_M + 1)
-
-/********Name=SOFTRST_CON01,Offset=0xA04********/
-#define SRST_A_TOP_BIU 19
-#define SRST_P_TOP_BIU 20
-#define SRST_P_CSIPHY0 22
-#define SRST_CSIPHY0 23
-#define SRST_P_CSIPHY1 24
-#define SRST_CSIPHY1 25
-#define SRST_A_TOP_M500_BIU 31
-/********Name=SOFTRST_CON02,Offset=0xA08********/
-#define SRST_A_TOP_M400_BIU 32
-#define SRST_A_TOP_S200_BIU 33
-#define SRST_A_TOP_S400_BIU 34
-#define SRST_A_TOP_M300_BIU 35
-#define SRST_USBDP_COMBO_PHY0_INIT 40
-#define SRST_USBDP_COMBO_PHY0_CMN 41
-#define SRST_USBDP_COMBO_PHY0_LANE 42
-#define SRST_USBDP_COMBO_PHY0_PCS 43
-#define SRST_USBDP_COMBO_PHY1_INIT 47
-/********Name=SOFTRST_CON03,Offset=0xA0C********/
-#define SRST_USBDP_COMBO_PHY1_CMN 48
-#define SRST_USBDP_COMBO_PHY1_LANE 49
-#define SRST_USBDP_COMBO_PHY1_PCS 50
-#define SRST_DCPHY0 59
-#define SRST_P_MIPI_DCPHY0 62
-#define SRST_P_MIPI_DCPHY0_GRF 63
-/********Name=SOFTRST_CON04,Offset=0xA10********/
-#define SRST_DCPHY1 64
-#define SRST_P_MIPI_DCPHY1 67
-#define SRST_P_MIPI_DCPHY1_GRF 68
-#define SRST_P_APB2ASB_SLV_CDPHY 69
-#define SRST_P_APB2ASB_SLV_CSIPHY 70
-#define SRST_P_APB2ASB_SLV_VCCIO3_5 71
-#define SRST_P_APB2ASB_SLV_VCCIO6 72
-#define SRST_P_APB2ASB_SLV_EMMCIO 73
-#define SRST_P_APB2ASB_SLV_IOC_TOP 74
-#define SRST_P_APB2ASB_SLV_IOC_RIGHT 75
-/********Name=SOFTRST_CON05,Offset=0xA14********/
-#define SRST_P_CRU 80
-#define SRST_A_CHANNEL_SECURE2VO1USB 87
-#define SRST_A_CHANNEL_SECURE2CENTER 88
-#define SRST_H_CHANNEL_SECURE2VO1USB 94
-#define SRST_H_CHANNEL_SECURE2CENTER 95
-/********Name=SOFTRST_CON06,Offset=0xA18********/
-#define SRST_P_CHANNEL_SECURE2VO1USB 96
-#define SRST_P_CHANNEL_SECURE2CENTER 97
-/********Name=SOFTRST_CON07,Offset=0xA1C********/
-#define SRST_H_AUDIO_BIU 114
-#define SRST_P_AUDIO_BIU 115
-#define SRST_H_I2S0_8CH 116
-#define SRST_M_I2S0_8CH_TX 119
-#define SRST_M_I2S0_8CH_RX 122
-#define SRST_P_ACDCDIG 123
-#define SRST_H_I2S2_2CH 124
-#define SRST_H_I2S3_2CH 125
-/********Name=SOFTRST_CON08,Offset=0xA20********/
-#define SRST_M_I2S2_2CH 128
-#define SRST_M_I2S3_2CH 131
-#define SRST_DAC_ACDCDIG 132
-#define SRST_H_SPDIF0 142
-/********Name=SOFTRST_CON09,Offset=0xA24********/
-#define SRST_M_SPDIF0 145
-#define SRST_H_SPDIF1 146
-#define SRST_M_SPDIF1 149
-#define SRST_H_PDM1 150
-#define SRST_PDM1 151
-/********Name=SOFTRST_CON10,Offset=0xA28********/
-#define SRST_A_BUS_BIU 161
-#define SRST_P_BUS_BIU 162
-#define SRST_A_GIC 163
-#define SRST_A_GIC_DBG 164
-#define SRST_A_DMAC0 165
-#define SRST_A_DMAC1 166
-#define SRST_A_DMAC2 167
-#define SRST_P_I2C1 168
-#define SRST_P_I2C2 169
-#define SRST_P_I2C3 170
-#define SRST_P_I2C4 171
-#define SRST_P_I2C5 172
-#define SRST_P_I2C6 173
-#define SRST_P_I2C7 174
-#define SRST_P_I2C8 175
-/********Name=SOFTRST_CON11,Offset=0xA2C********/
-#define SRST_I2C1 176
-#define SRST_I2C2 177
-#define SRST_I2C3 178
-#define SRST_I2C4 179
-#define SRST_I2C5 180
-#define SRST_I2C6 181
-#define SRST_I2C7 182
-#define SRST_I2C8 183
-#define SRST_P_CAN0 184
-#define SRST_CAN0 185
-#define SRST_P_CAN1 186
-#define SRST_CAN1 187
-#define SRST_P_CAN2 188
-#define SRST_CAN2 189
-#define SRST_P_SARADC 190
-/********Name=SOFTRST_CON12,Offset=0xA30********/
-#define SRST_P_TSADC 192
-#define SRST_TSADC 193
-#define SRST_P_UART1 194
-#define SRST_P_UART2 195
-#define SRST_P_UART3 196
-#define SRST_P_UART4 197
-#define SRST_P_UART5 198
-#define SRST_P_UART6 199
-#define SRST_P_UART7 200
-#define SRST_P_UART8 201
-#define SRST_P_UART9 202
-#define SRST_S_UART1 205
-/********Name=SOFTRST_CON13,Offset=0xA34********/
-#define SRST_S_UART2 208
-#define SRST_S_UART3 211
-#define SRST_S_UART4 214
-#define SRST_S_UART5 217
-#define SRST_S_UART6 220
-#define SRST_S_UART7 223
-/********Name=SOFTRST_CON14,Offset=0xA38********/
-#define SRST_S_UART8 226
-#define SRST_S_UART9 229
-#define SRST_P_SPI0 230
-#define SRST_P_SPI1 231
-#define SRST_P_SPI2 232
-#define SRST_P_SPI3 233
-#define SRST_P_SPI4 234
-#define SRST_SPI0 235
-#define SRST_SPI1 236
-#define SRST_SPI2 237
-#define SRST_SPI3 238
-#define SRST_SPI4 239
-/********Name=SOFTRST_CON15,Offset=0xA3C********/
-#define SRST_P_WDT0 240
-#define SRST_T_WDT0 241
-#define SRST_P_SYS_GRF 242
-#define SRST_P_PWM1 243
-#define SRST_PWM1 244
-#define SRST_P_PWM2 246
-#define SRST_PWM2 247
-#define SRST_P_PWM3 249
-#define SRST_PWM3 250
-#define SRST_P_BUSTIMER0 252
-#define SRST_P_BUSTIMER1 253
-#define SRST_BUSTIMER0 255
-/********Name=SOFTRST_CON16,Offset=0xA40********/
-#define SRST_BUSTIMER1 256
-#define SRST_BUSTIMER2 257
-#define SRST_BUSTIMER3 258
-#define SRST_BUSTIMER4 259
-#define SRST_BUSTIMER5 260
-#define SRST_BUSTIMER6 261
-#define SRST_BUSTIMER7 262
-#define SRST_BUSTIMER8 263
-#define SRST_BUSTIMER9 264
-#define SRST_BUSTIMER10 265
-#define SRST_BUSTIMER11 266
-#define SRST_P_MAILBOX0 267
-#define SRST_P_MAILBOX1 268
-#define SRST_P_MAILBOX2 269
-#define SRST_P_GPIO1 270
-#define SRST_GPIO1 271
-/********Name=SOFTRST_CON17,Offset=0xA44********/
-#define SRST_P_GPIO2 272
-#define SRST_GPIO2 273
-#define SRST_P_GPIO3 274
-#define SRST_GPIO3 275
-#define SRST_P_GPIO4 276
-#define SRST_GPIO4 277
-#define SRST_A_DECOM 278
-#define SRST_P_DECOM 279
-#define SRST_D_DECOM 280
-#define SRST_P_TOP 281
-#define SRST_A_GICADB_GIC2CORE_BUS 283
-#define SRST_P_DFT2APB 284
-#define SRST_P_APB2ASB_MST_TOP 285
-#define SRST_P_APB2ASB_MST_CDPHY 286
-#define SRST_P_APB2ASB_MST_BOT_RIGHT 287
-/********Name=SOFTRST_CON18,Offset=0xA48********/
-#define SRST_P_APB2ASB_MST_IOC_TOP 288
-#define SRST_P_APB2ASB_MST_IOC_RIGHT 289
-#define SRST_P_APB2ASB_MST_CSIPHY 290
-#define SRST_P_APB2ASB_MST_VCCIO3_5 291
-#define SRST_P_APB2ASB_MST_VCCIO6 292
-#define SRST_P_APB2ASB_MST_EMMCIO 293
-#define SRST_A_SPINLOCK 294
-#define SRST_P_OTPC_NS 297
-#define SRST_OTPC_NS 298
-#define SRST_OTPC_ARB 299
-/********Name=SOFTRST_CON19,Offset=0xA4C********/
-#define SRST_P_BUSIOC 304
-#define SRST_P_PMUCM0_INTMUX 308
-#define SRST_P_DDRCM0_INTMUX 309
-/********Name=SOFTRST_CON20,Offset=0xA50********/
-#define SRST_P_DDR_DFICTL_CH0 320
-#define SRST_P_DDR_MON_CH0 321
-#define SRST_P_DDR_STANDBY_CH0 322
-#define SRST_P_DDR_UPCTL_CH0 323
-#define SRST_TM_DDR_MON_CH0 324
-#define SRST_P_DDR_GRF_CH01 325
-#define SRST_DFI_CH0 326
-#define SRST_SBR_CH0 327
-#define SRST_DDR_UPCTL_CH0 328
-#define SRST_DDR_DFICTL_CH0 329
-#define SRST_DDR_MON_CH0 330
-#define SRST_DDR_STANDBY_CH0 331
-#define SRST_A_DDR_UPCTL_CH0 332
-#define SRST_P_DDR_DFICTL_CH1 333
-#define SRST_P_DDR_MON_CH1 334
-#define SRST_P_DDR_STANDBY_CH1 335
-/********Name=SOFTRST_CON21,Offset=0xA54********/
-#define SRST_P_DDR_UPCTL_CH1 336
-#define SRST_TM_DDR_MON_CH1 337
-#define SRST_DFI_CH1 338
-#define SRST_SBR_CH1 339
-#define SRST_DDR_UPCTL_CH1 340
-#define SRST_DDR_DFICTL_CH1 341
-#define SRST_DDR_MON_CH1 342
-#define SRST_DDR_STANDBY_CH1 343
-#define SRST_A_DDR_UPCTL_CH1 344
-#define SRST_A_DDR01_MSCH0 349
-#define SRST_A_DDR01_RS_MSCH0 350
-#define SRST_A_DDR01_FRS_MSCH0 351
-/********Name=SOFTRST_CON22,Offset=0xA58********/
-#define SRST_A_DDR01_SCRAMBLE0 352
-#define SRST_A_DDR01_FRS_SCRAMBLE0 353
-#define SRST_A_DDR01_MSCH1 354
-#define SRST_A_DDR01_RS_MSCH1 355
-#define SRST_A_DDR01_FRS_MSCH1 356
-#define SRST_A_DDR01_SCRAMBLE1 357
-#define SRST_A_DDR01_FRS_SCRAMBLE1 358
-#define SRST_P_DDR01_MSCH0 359
-#define SRST_P_DDR01_MSCH1 360
-/********Name=SOFTRST_CON23,Offset=0xA5C********/
-#define SRST_P_DDR_DFICTL_CH2 368
-#define SRST_P_DDR_MON_CH2 369
-#define SRST_P_DDR_STANDBY_CH2 370
-#define SRST_P_DDR_UPCTL_CH2 371
-#define SRST_TM_DDR_MON_CH2 372
-#define SRST_P_DDR_GRF_CH23 373
-#define SRST_DFI_CH2 374
-#define SRST_SBR_CH2 375
-#define SRST_DDR_UPCTL_CH2 376
-#define SRST_DDR_DFICTL_CH2 377
-#define SRST_DDR_MON_CH2 378
-#define SRST_DDR_STANDBY_CH2 379
-#define SRST_A_DDR_UPCTL_CH2 380
-#define SRST_P_DDR_DFICTL_CH3 381
-#define SRST_P_DDR_MON_CH3 382
-#define SRST_P_DDR_STANDBY_CH3 383
-/********Name=SOFTRST_CON24,Offset=0xA60********/
-#define SRST_P_DDR_UPCTL_CH3 384
-#define SRST_TM_DDR_MON_CH3 385
-#define SRST_DFI_CH3 386
-#define SRST_SBR_CH3 387
-#define SRST_DDR_UPCTL_CH3 388
-#define SRST_DDR_DFICTL_CH3 389
-#define SRST_DDR_MON_CH3 390
-#define SRST_DDR_STANDBY_CH3 391
-#define SRST_A_DDR_UPCTL_CH3 392
-#define SRST_A_DDR23_MSCH2 397
-#define SRST_A_DDR23_RS_MSCH2 398
-#define SRST_A_DDR23_FRS_MSCH2 399
-/********Name=SOFTRST_CON25,Offset=0xA64********/
-#define SRST_A_DDR23_SCRAMBLE2 400
-#define SRST_A_DDR23_FRS_SCRAMBLE2 401
-#define SRST_A_DDR23_MSCH3 402
-#define SRST_A_DDR23_RS_MSCH3 403
-#define SRST_A_DDR23_FRS_MSCH3 404
-#define SRST_A_DDR23_SCRAMBLE3 405
-#define SRST_A_DDR23_FRS_SCRAMBLE3 406
-#define SRST_P_DDR23_MSCH2 407
-#define SRST_P_DDR23_MSCH3 408
-/********Name=SOFTRST_CON26,Offset=0xA68********/
-#define SRST_ISP1 419
-#define SRST_ISP1_VICAP 420
-#define SRST_A_ISP1_BIU 422
-#define SRST_H_ISP1_BIU 424
-/********Name=SOFTRST_CON27,Offset=0xA6C********/
-#define SRST_A_RKNN1 432
-#define SRST_A_RKNN1_BIU 433
-#define SRST_H_RKNN1 434
-#define SRST_H_RKNN1_BIU 435
-/********Name=SOFTRST_CON28,Offset=0xA70********/
-#define SRST_A_RKNN2 448
-#define SRST_A_RKNN2_BIU 449
-#define SRST_H_RKNN2 450
-#define SRST_H_RKNN2_BIU 451
-/********Name=SOFTRST_CON29,Offset=0xA74********/
-#define SRST_A_RKNN_DSU0 467
-#define SRST_P_NPUTOP_BIU 469
-#define SRST_P_NPU_TIMER 470
-#define SRST_NPUTIMER0 472
-#define SRST_NPUTIMER1 473
-#define SRST_P_NPU_WDT 474
-#define SRST_T_NPU_WDT 475
-#define SRST_P_NPU_PVTM 476
-#define SRST_P_NPU_GRF 477
-#define SRST_NPU_PVTM 478
-/********Name=SOFTRST_CON30,Offset=0xA78********/
-#define SRST_NPU_PVTPLL 480
-#define SRST_H_NPU_CM0_BIU 482
-#define SRST_F_NPU_CM0_CORE 483
-#define SRST_T_NPU_CM0_JTAG 484
-#define SRST_A_RKNN0 486
-#define SRST_A_RKNN0_BIU 487
-#define SRST_H_RKNN0 488
-#define SRST_H_RKNN0_BIU 489
-/********Name=SOFTRST_CON31,Offset=0xA7C********/
-#define SRST_H_NVM_BIU 498
-#define SRST_A_NVM_BIU 499
-#define SRST_H_EMMC 500
-#define SRST_A_EMMC 501
-#define SRST_C_EMMC 502
-#define SRST_B_EMMC 503
-#define SRST_T_EMMC 504
-#define SRST_S_SFC 505
-#define SRST_H_SFC 506
-#define SRST_H_SFC_XIP 507
-/********Name=SOFTRST_CON32,Offset=0xA80********/
-#define SRST_P_GRF 513
-#define SRST_P_DEC_BIU 514
-#define SRST_P_PHP_BIU 517
-#define SRST_A_PCIE_GRIDGE 520
-#define SRST_A_PHP_BIU 521
-#define SRST_A_GMAC0 522
-#define SRST_A_GMAC1 523
-#define SRST_A_PCIE_BIU 524
-#define SRST_PCIE0_POWER_UP 525
-#define SRST_PCIE1_POWER_UP 526
-#define SRST_PCIE2_POWER_UP 527
-/********Name=SOFTRST_CON33,Offset=0xA84********/
-#define SRST_PCIE3_POWER_UP 528
-#define SRST_PCIE4_POWER_UP 529
-#define SRST_P_PCIE0 540
-#define SRST_P_PCIE1 541
-#define SRST_P_PCIE2 542
-#define SRST_P_PCIE3 543
-/********Name=SOFTRST_CON34,Offset=0xA88********/
-#define SRST_P_PCIE4 544
-#define SRST_A_PHP_GIC_ITS 550
-#define SRST_A_MMU_PCIE 551
-#define SRST_A_MMU_PHP 552
-#define SRST_A_MMU_BIU 553
-/********Name=SOFTRST_CON35,Offset=0xA8C********/
-#define SRST_A_USB3OTG2 567
-/********Name=SOFTRST_CON37,Offset=0xA94********/
-#define SRST_PMALIVE0 596
-#define SRST_PMALIVE1 597
-#define SRST_PMALIVE2 598
-#define SRST_A_SATA0 599
-#define SRST_A_SATA1 600
-#define SRST_A_SATA2 601
-#define SRST_RXOOB0 602
-#define SRST_RXOOB1 603
-#define SRST_RXOOB2 604
-#define SRST_ASIC0 605
-#define SRST_ASIC1 606
-#define SRST_ASIC2 607
-/********Name=SOFTRST_CON40,Offset=0xAA0********/
-#define SRST_A_RKVDEC_CCU 642
-#define SRST_H_RKVDEC0 643
-#define SRST_A_RKVDEC0 644
-#define SRST_H_RKVDEC0_BIU 645
-#define SRST_A_RKVDEC0_BIU 646
-#define SRST_RKVDEC0_CA 647
-#define SRST_RKVDEC0_HEVC_CA 648
-#define SRST_RKVDEC0_CORE 649
-/********Name=SOFTRST_CON41,Offset=0xAA4********/
-#define SRST_H_RKVDEC1 658
-#define SRST_A_RKVDEC1 659
-#define SRST_H_RKVDEC1_BIU 660
-#define SRST_A_RKVDEC1_BIU 661
-#define SRST_RKVDEC1_CA 662
-#define SRST_RKVDEC1_HEVC_CA 663
-#define SRST_RKVDEC1_CORE 664
-/********Name=SOFTRST_CON42,Offset=0xAA8********/
-#define SRST_A_USB_BIU 674
-#define SRST_H_USB_BIU 675
-#define SRST_A_USB3OTG0 676
-#define SRST_A_USB3OTG1 679
-#define SRST_H_HOST0 682
-#define SRST_H_HOST_ARB0 683
-#define SRST_H_HOST1 684
-#define SRST_H_HOST_ARB1 685
-#define SRST_A_USB_GRF 686
-#define SRST_C_USB2P0_HOST0 687
-/********Name=SOFTRST_CON43,Offset=0xAAC********/
-#define SRST_C_USB2P0_HOST1 688
-#define SRST_HOST_UTMI0 689
-#define SRST_HOST_UTMI1 690
-/********Name=SOFTRST_CON44,Offset=0xAB0********/
-#define SRST_A_VDPU_BIU 708
-#define SRST_A_VDPU_LOW_BIU 709
-#define SRST_H_VDPU_BIU 710
-#define SRST_A_JPEG_DECODER_BIU 711
-#define SRST_A_VPU 712
-#define SRST_H_VPU 713
-#define SRST_A_JPEG_ENCODER0 714
-#define SRST_H_JPEG_ENCODER0 715
-#define SRST_A_JPEG_ENCODER1 716
-#define SRST_H_JPEG_ENCODER1 717
-#define SRST_A_JPEG_ENCODER2 718
-#define SRST_H_JPEG_ENCODER2 719
-/********Name=SOFTRST_CON45,Offset=0xAB4********/
-#define SRST_A_JPEG_ENCODER3 720
-#define SRST_H_JPEG_ENCODER3 721
-#define SRST_A_JPEG_DECODER 722
-#define SRST_H_JPEG_DECODER 723
-#define SRST_H_IEP2P0 724
-#define SRST_A_IEP2P0 725
-#define SRST_IEP2P0_CORE 726
-#define SRST_H_RGA2 727
-#define SRST_A_RGA2 728
-#define SRST_RGA2_CORE 729
-#define SRST_H_RGA3_0 730
-#define SRST_A_RGA3_0 731
-#define SRST_RGA3_0_CORE 732
-/********Name=SOFTRST_CON47,Offset=0xABC********/
-#define SRST_H_RKVENC0_BIU 754
-#define SRST_A_RKVENC0_BIU 755
-#define SRST_H_RKVENC0 756
-#define SRST_A_RKVENC0 757
-#define SRST_RKVENC0_CORE 758
-/********Name=SOFTRST_CON48,Offset=0xAC0********/
-#define SRST_H_RKVENC1_BIU 770
-#define SRST_A_RKVENC1_BIU 771
-#define SRST_H_RKVENC1 772
-#define SRST_A_RKVENC1 773
-#define SRST_RKVENC1_CORE 774
-/********Name=SOFTRST_CON49,Offset=0xAC4********/
-#define SRST_A_VI_BIU 787
-#define SRST_H_VI_BIU 788
-#define SRST_P_VI_BIU 789
-#define SRST_D_VICAP 790
-#define SRST_A_VICAP 791
-#define SRST_H_VICAP 792
-#define SRST_ISP0 794
-#define SRST_ISP0_VICAP 795
-/********Name=SOFTRST_CON50,Offset=0xAC8********/
-#define SRST_FISHEYE0 800
-#define SRST_FISHEYE1 803
-#define SRST_P_CSI_HOST_0 804
-#define SRST_P_CSI_HOST_1 805
-#define SRST_P_CSI_HOST_2 806
-#define SRST_P_CSI_HOST_3 807
-#define SRST_P_CSI_HOST_4 808
-#define SRST_P_CSI_HOST_5 809
-/********Name=SOFTRST_CON51,Offset=0xACC********/
-#define SRST_CSIHOST0_VICAP 820
-#define SRST_CSIHOST1_VICAP 821
-#define SRST_CSIHOST2_VICAP 822
-#define SRST_CSIHOST3_VICAP 823
-#define SRST_CSIHOST4_VICAP 824
-#define SRST_CSIHOST5_VICAP 825
-#define SRST_CIFIN 829
-/********Name=SOFTRST_CON52,Offset=0xAD0********/
-#define SRST_A_VOP_BIU 836
-#define SRST_A_VOP_LOW_BIU 837
-#define SRST_H_VOP_BIU 838
-#define SRST_P_VOP_BIU 839
-#define SRST_H_VOP 840
-#define SRST_A_VOP 841
-#define SRST_D_VOP0 845
-#define SRST_D_VOP2HDMI_BRIDGE0 846
-#define SRST_D_VOP2HDMI_BRIDGE1 847
-/********Name=SOFTRST_CON53,Offset=0xAD4********/
-#define SRST_D_VOP1 848
-#define SRST_D_VOP2 849
-#define SRST_D_VOP3 850
-#define SRST_P_VOPGRF 851
-#define SRST_P_DSIHOST0 852
-#define SRST_P_DSIHOST1 853
-#define SRST_DSIHOST0 854
-#define SRST_DSIHOST1 855
-#define SRST_VOP_PMU 856
-#define SRST_P_VOP_CHANNEL_BIU 857
-/********Name=SOFTRST_CON55,Offset=0xADC********/
-#define SRST_H_VO0_BIU 885
-#define SRST_H_VO0_S_BIU 886
-#define SRST_P_VO0_BIU 887
-#define SRST_P_VO0_S_BIU 888
-#define SRST_A_HDCP0_BIU 889
-#define SRST_P_VO0GRF 890
-#define SRST_H_HDCP_KEY0 891
-#define SRST_A_HDCP0 892
-#define SRST_H_HDCP0 893
-#define SRST_HDCP0 895
-/********Name=SOFTRST_CON56,Offset=0xAE0********/
-#define SRST_P_TRNG0 897
-#define SRST_DP0 904
-#define SRST_DP1 905
-#define SRST_H_I2S4_8CH 906
-#define SRST_M_I2S4_8CH_TX 909
-#define SRST_H_I2S8_8CH 910
-/********Name=SOFTRST_CON57,Offset=0xAE4********/
-#define SRST_M_I2S8_8CH_TX 913
-#define SRST_H_SPDIF2_DP0 914
-#define SRST_M_SPDIF2_DP0 918
-#define SRST_H_SPDIF5_DP1 919
-#define SRST_M_SPDIF5_DP1 923
-/********Name=SOFTRST_CON59,Offset=0xAEC********/
-#define SRST_A_HDCP1_BIU 950
-#define SRST_A_HDMIRX_BIU 951
-#define SRST_A_VO1_BIU 952
-#define SRST_H_VOP1_BIU 953
-#define SRST_H_VOP1_S_BIU 954
-#define SRST_P_VOP1_BIU 955
-#define SRST_P_VO1GRF 956
-#define SRST_P_VO1_S_BIU 957
-/********Name=SOFTRST_CON60,Offset=0xAF0********/
-#define SRST_H_I2S7_8CH 960
-#define SRST_M_I2S7_8CH_RX 963
-#define SRST_H_HDCP_KEY1 964
-#define SRST_A_HDCP1 965
-#define SRST_H_HDCP1 966
-#define SRST_HDCP1 968
-#define SRST_P_TRNG1 970
-#define SRST_P_HDMITX0 971
-/********Name=SOFTRST_CON61,Offset=0xAF4********/
-#define SRST_HDMITX0_REF 976
-#define SRST_P_HDMITX1 978
-#define SRST_HDMITX1_REF 983
-#define SRST_A_HDMIRX 985
-#define SRST_P_HDMIRX 986
-#define SRST_HDMIRX_REF 987
-/********Name=SOFTRST_CON62,Offset=0xAF8********/
-#define SRST_P_EDP0 992
-#define SRST_EDP0_24M 993
-#define SRST_P_EDP1 995
-#define SRST_EDP1_24M 996
-#define SRST_M_I2S5_8CH_TX 1000
-#define SRST_H_I2S5_8CH 1004
-#define SRST_M_I2S6_8CH_TX 1007
-/********Name=SOFTRST_CON63,Offset=0xAFC********/
-#define SRST_M_I2S6_8CH_RX 1010
-#define SRST_H_I2S6_8CH 1011
-#define SRST_H_SPDIF3 1012
-#define SRST_M_SPDIF3 1015
-#define SRST_H_SPDIF4 1016
-#define SRST_M_SPDIF4 1019
-#define SRST_H_SPDIFRX0 1020
-#define SRST_M_SPDIFRX0 1021
-#define SRST_H_SPDIFRX1 1022
-#define SRST_M_SPDIFRX1 1023
-/********Name=SOFTRST_CON64,Offset=0xB00********/
-#define SRST_H_SPDIFRX2 1024
-#define SRST_M_SPDIFRX2 1025
-#define SRST_LINKSYM_HDMITXPHY0 1036
-#define SRST_LINKSYM_HDMITXPHY1 1037
-#define SRST_VO1_BRIDGE0 1038
-#define SRST_VO1_BRIDGE1 1039
-/********Name=SOFTRST_CON65,Offset=0xB04********/
-#define SRST_H_I2S9_8CH 1040
-#define SRST_M_I2S9_8CH_RX 1043
-#define SRST_H_I2S10_8CH 1044
-#define SRST_M_I2S10_8CH_RX 1047
-#define SRST_P_S_HDMIRX 1048
-/********Name=SOFTRST_CON66,Offset=0xB08********/
-#define SRST_GPU 1060
-#define SRST_SYS_GPU 1061
-#define SRST_A_S_GPU_BIU 1064
-#define SRST_A_M0_GPU_BIU 1065
-#define SRST_A_M1_GPU_BIU 1066
-#define SRST_A_M2_GPU_BIU 1067
-#define SRST_A_M3_GPU_BIU 1068
-#define SRST_P_GPU_BIU 1070
-#define SRST_P_GPU_PVTM 1071
-/********Name=SOFTRST_CON67,Offset=0xB0C********/
-#define SRST_GPU_PVTM 1072
-#define SRST_P_GPU_GRF 1074
-#define SRST_GPU_PVTPLL 1075
-#define SRST_GPU_JTAG 1076
-/********Name=SOFTRST_CON68,Offset=0xB10********/
-#define SRST_A_AV1_BIU 1089
-#define SRST_A_AV1 1090
-#define SRST_P_AV1_BIU 1092
-#define SRST_P_AV1 1093
-/********Name=SOFTRST_CON69,Offset=0xB14********/
-#define SRST_A_DDR_BIU 1108
-#define SRST_A_DMA2DDR 1109
-#define SRST_A_DDR_SHAREMEM 1110
-#define SRST_A_DDR_SHAREMEM_BIU 1111
-#define SRST_A_CENTER_S200_BIU 1114
-#define SRST_A_CENTER_S400_BIU 1115
-#define SRST_H_AHB2APB 1116
-#define SRST_H_CENTER_BIU 1117
-#define SRST_F_DDR_CM0_CORE 1118
-/********Name=SOFTRST_CON70,Offset=0xB18********/
-#define SRST_DDR_TIMER0 1120
-#define SRST_DDR_TIMER1 1121
-#define SRST_T_WDT_DDR 1122
-#define SRST_T_DDR_CM0_JTAG 1123
-#define SRST_P_CENTER_GRF 1125
-#define SRST_P_AHB2APB 1126
-#define SRST_P_WDT 1127
-#define SRST_P_TIMER 1128
-#define SRST_P_DMA2DDR 1129
-#define SRST_P_SHAREMEM 1130
-#define SRST_P_CENTER_BIU 1131
-#define SRST_P_CENTER_CHANNEL_BIU 1132
-/********Name=SOFTRST_CON72,Offset=0xB20********/
-#define SRST_P_USBDPGRF0 1153
-#define SRST_P_USBDPPHY0 1154
-#define SRST_P_USBDPGRF1 1155
-#define SRST_P_USBDPPHY1 1156
-#define SRST_P_HDPTX0 1157
-#define SRST_P_HDPTX1 1158
-#define SRST_P_APB2ASB_SLV_BOT_RIGHT 1159
-#define SRST_P_USB2PHY_U3_0_GRF0 1160
-#define SRST_P_USB2PHY_U3_1_GRF0 1161
-#define SRST_P_USB2PHY_U2_0_GRF0 1162
-#define SRST_P_USB2PHY_U2_1_GRF0 1163
-#define SRST_HDPTX0_ROPLL 1164
-#define SRST_HDPTX0_LCPLL 1165
-#define SRST_HDPTX0 1166
-#define SRST_HDPTX1_ROPLL 1167
-/********Name=SOFTRST_CON73,Offset=0xB24********/
-#define SRST_HDPTX1_LCPLL 1168
-#define SRST_HDPTX1 1169
-#define SRST_HDPTX0_HDMIRXPHY_SET 1170
-#define SRST_USBDP_COMBO_PHY0 1171
-#define SRST_USBDP_COMBO_PHY0_LCPLL 1172
-#define SRST_USBDP_COMBO_PHY0_ROPLL 1173
-#define SRST_USBDP_COMBO_PHY0_PCS_HS 1174
-#define SRST_USBDP_COMBO_PHY1 1175
-#define SRST_USBDP_COMBO_PHY1_LCPLL 1176
-#define SRST_USBDP_COMBO_PHY1_ROPLL 1177
-#define SRST_USBDP_COMBO_PHY1_PCS_HS 1178
-#define SRST_HDMIHDP0 1180
-#define SRST_HDMIHDP1 1181
-/********Name=SOFTRST_CON74,Offset=0xB28********/
-#define SRST_A_VO1USB_TOP_BIU 1185
-#define SRST_H_VO1USB_TOP_BIU 1187
-/********Name=SOFTRST_CON75,Offset=0xB2C********/
-#define SRST_H_SDIO_BIU 1201
-#define SRST_H_SDIO 1202
-#define SRST_SDIO 1203
-/********Name=SOFTRST_CON76,Offset=0xB30********/
-#define SRST_H_RGA3_BIU 1218
-#define SRST_A_RGA3_BIU 1219
-#define SRST_H_RGA3_1 1220
-#define SRST_A_RGA3_1 1221
-#define SRST_RGA3_1_CORE 1222
-/********Name=SOFTRST_CON77,Offset=0xB34********/
-#define SRST_REF_PIPE_PHY0 1238
-#define SRST_REF_PIPE_PHY1 1239
-#define SRST_REF_PIPE_PHY2 1240
-
-/********Name=PHPTOPSOFTRST_CON0,Offset=0x8A00********/
-#define SRST_P_PHPTOP_CRU 131073
-#define SRST_P_PCIE2_GRF0 131074
-#define SRST_P_PCIE2_GRF1 131075
-#define SRST_P_PCIE2_GRF2 131076
-#define SRST_P_PCIE2_PHY0 131077
-#define SRST_P_PCIE2_PHY1 131078
-#define SRST_P_PCIE2_PHY2 131079
-#define SRST_P_PCIE3_PHY 131080
-#define SRST_P_APB2ASB_SLV_CHIP_TOP 131081
-#define SRST_PCIE30_PHY 131082
-
-/********Name=PMU1SOFTRST_CON00,Offset=0x30A00********/
-#define SRST_H_PMU1_BIU 786442
-#define SRST_P_PMU1_BIU 786443
-#define SRST_H_PMU_CM0_BIU 786444
-#define SRST_F_PMU_CM0_CORE 786445
-#define SRST_T_PMU1_CM0_JTAG 786446
-
-/********Name=PMU1SOFTRST_CON01,Offset=0x30A04********/
-#define SRST_DDR_FAIL_SAFE 786449
-#define SRST_P_CRU_PMU1 786450
-#define SRST_P_PMU1_GRF 786452
-#define SRST_P_PMU1_IOC 786453
-#define SRST_P_PMU1WDT 786454
-#define SRST_T_PMU1WDT 786455
-#define SRST_P_PMU1TIMER 786456
-#define SRST_PMU1TIMER0 786458
-#define SRST_PMU1TIMER1 786459
-#define SRST_P_PMU1PWM 786460
-#define SRST_PMU1PWM 786461
-
-/********Name=PMU1SOFTRST_CON02,Offset=0x30A08********/
-#define SRST_P_I2C0 786465
-#define SRST_I2C0 786466
-#define SRST_S_UART0 786469
-#define SRST_P_UART0 786470
-#define SRST_H_I2S1_8CH 786471
-#define SRST_M_I2S1_8CH_TX 786474
-#define SRST_M_I2S1_8CH_RX 786477
-#define SRST_H_PDM0 786478
-#define SRST_PDM0 786479
-
-/********Name=PMU1SOFTRST_CON03,Offset=0x30A0C********/
-#define SRST_H_VAD 786480
-#define SRST_HDPTX0_INIT 786491
-#define SRST_HDPTX0_CMN 786492
-#define SRST_HDPTX0_LANE 786493
-#define SRST_HDPTX1_INIT 786495
-
-/********Name=PMU1SOFTRST_CON04,Offset=0x30A10********/
-#define SRST_HDPTX1_CMN 786496
-#define SRST_HDPTX1_LANE 786497
-#define SRST_M_MIPI_DCPHY0 786499
-#define SRST_S_MIPI_DCPHY0 786500
-#define SRST_M_MIPI_DCPHY1 786501
-#define SRST_S_MIPI_DCPHY1 786502
-#define SRST_OTGPHY_U3_0 786503
-#define SRST_OTGPHY_U3_1 786504
-#define SRST_OTGPHY_U2_0 786505
-#define SRST_OTGPHY_U2_1 786506
-
-/********Name=PMU1SOFTRST_CON05,Offset=0x30A14********/
-#define SRST_P_PMU0GRF 786515
-#define SRST_P_PMU0IOC 786516
-#define SRST_P_GPIO0 786517
-#define SRST_GPIO0 786518
-
-/* scmi-clocks indices */
-
-#define SCMI_CLK_CPUL 0
-#define SCMI_CLK_DSU 1
-#define SCMI_CLK_CPUB01 2
-#define SCMI_CLK_CPUB23 3
-#define SCMI_CLK_DDR 4
-#define SCMI_CLK_GPU 5
-#define SCMI_CLK_NPU 6
-#define SCMI_CLK_SBUS 7
-#define SCMI_PCLK_SBUS 8
-#define SCMI_CCLK_SD 9
-#define SCMI_DCLK_SD 10
-#define SCMI_ACLK_SECURE_NS 11
-#define SCMI_HCLK_SECURE_NS 12
-#define SCMI_TCLK_WDT 13
-#define SCMI_KEYLADDER_CORE 14
-#define SCMI_KEYLADDER_RNG 15
-#define SCMI_ACLK_SECURE_S 16
-#define SCMI_HCLK_SECURE_S 17
-#define SCMI_PCLK_SECURE_S 18
-#define SCMI_CRYPTO_RNG 19
-#define SCMI_CRYPTO_CORE 20
-#define SCMI_CRYPTO_PKA 21
-#define SCMI_SPLL 22
-#define SCMI_HCLK_SD 23
-
-/********Name=SECURE_SOFTRST_CON00,Offset=0xA00********/
-#define SRST_A_SECURE_NS_BIU 10
-#define SRST_H_SECURE_NS_BIU 11
-#define SRST_A_SECURE_S_BIU 12
-#define SRST_H_SECURE_S_BIU 13
-#define SRST_P_SECURE_S_BIU 14
-#define SRST_CRYPTO_CORE 15
-/********Name=SECURE_SOFTRST_CON01,Offset=0xA04********/
-#define SRST_CRYPTO_PKA 16
-#define SRST_CRYPTO_RNG 17
-#define SRST_A_CRYPTO 18
-#define SRST_H_CRYPTO 19
-#define SRST_KEYLADDER_CORE 25
-#define SRST_KEYLADDER_RNG 26
-#define SRST_A_KEYLADDER 27
-#define SRST_H_KEYLADDER 28
-#define SRST_P_OTPC_S 29
-#define SRST_OTPC_S 30
-#define SRST_WDT_S 31
-/********Name=SECURE_SOFTRST_CON02,Offset=0xA08********/
-#define SRST_T_WDT_S 32
-#define SRST_H_BOOTROM 33
-#define SRST_A_DCF 34
-#define SRST_P_DCF 35
-#define SRST_H_BOOTROM_NS 37
-#define SRST_P_KEYLADDER 46
-#define SRST_H_TRNG_S 47
-/********Name=SECURE_SOFTRST_CON03,Offset=0xA0C********/
-#define SRST_H_TRNG_NS 48
-#define SRST_D_SDMMC_BUFFER 49
-#define SRST_H_SDMMC 50
-#define SRST_H_SDMMC_BUFFER 51
-#define SRST_SDMMC 52
-#define SRST_P_TRNG_CHK 53
-#define SRST_TRNG_S 54
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/input/rk-input.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/input/rk-input.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/input/rk-input.h (nonexistent)
@@ -1,814 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Device properties and quirks
- */
-
-#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
-#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
-#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
-#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
-
-#define INPUT_PROP_MAX 0x1f
-#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
-
-/*
- * Event types
- */
-
-#define EV_SYN 0x00
-#define EV_KEY 0x01
-#define EV_REL 0x02
-#define EV_ABS 0x03
-#define EV_MSC 0x04
-#define EV_SW 0x05
-#define EV_LED 0x11
-#define EV_SND 0x12
-#define EV_REP 0x14
-#define EV_FF 0x15
-#define EV_PWR 0x16
-#define EV_FF_STATUS 0x17
-#define EV_MAX 0x1f
-#define EV_CNT (EV_MAX+1)
-
-/*
- * Synchronization events.
- */
-
-#define SYN_REPORT 0
-#define SYN_CONFIG 1
-#define SYN_MT_REPORT 2
-#define SYN_DROPPED 3
-
-/*
- * Keys and buttons
- *
- * Most of the keys/buttons are modeled after USB HUT 1.12
- * (see http://www.usb.org/developers/hidpage).
- * Abbreviations in the comments:
- * AC - Application Control
- * AL - Application Launch Button
- * SC - System Control
- */
-
-#define KEY_RESERVED 0
-#define KEY_ESC 1
-#define KEY_1 2
-#define KEY_2 3
-#define KEY_3 4
-#define KEY_4 5
-#define KEY_5 6
-#define KEY_6 7
-#define KEY_7 8
-#define KEY_8 9
-#define KEY_9 10
-#define KEY_0 11
-#define KEY_MINUS 12
-#define KEY_EQUAL 13
-#define KEY_BACKSPACE 14
-#define KEY_TAB 15
-#define KEY_Q 16
-#define KEY_W 17
-#define KEY_E 18
-#define KEY_R 19
-#define KEY_T 20
-#define KEY_Y 21
-#define KEY_U 22
-#define KEY_I 23
-#define KEY_O 24
-#define KEY_P 25
-#define KEY_LEFTBRACE 26
-#define KEY_RIGHTBRACE 27
-#define KEY_ENTER 28
-#define KEY_LEFTCTRL 29
-#define KEY_A 30
-#define KEY_S 31
-#define KEY_D 32
-#define KEY_F 33
-#define KEY_G 34
-#define KEY_H 35
-#define KEY_J 36
-#define KEY_K 37
-#define KEY_L 38
-#define KEY_SEMICOLON 39
-#define KEY_APOSTROPHE 40
-#define KEY_GRAVE 41
-#define KEY_LEFTSHIFT 42
-#define KEY_BACKSLASH 43
-#define KEY_Z 44
-#define KEY_X 45
-#define KEY_C 46
-#define KEY_V 47
-#define KEY_B 48
-#define KEY_N 49
-#define KEY_M 50
-#define KEY_COMMA 51
-#define KEY_DOT 52
-#define KEY_SLASH 53
-#define KEY_RIGHTSHIFT 54
-#define KEY_KPASTERISK 55
-#define KEY_LEFTALT 56
-#define KEY_SPACE 57
-#define KEY_CAPSLOCK 58
-#define KEY_F1 59
-#define KEY_F2 60
-#define KEY_F3 61
-#define KEY_F4 62
-#define KEY_F5 63
-#define KEY_F6 64
-#define KEY_F7 65
-#define KEY_F8 66
-#define KEY_F9 67
-#define KEY_F10 68
-#define KEY_NUMLOCK 69
-#define KEY_SCROLLLOCK 70
-#define KEY_KP7 71
-#define KEY_KP8 72
-#define KEY_KP9 73
-#define KEY_KPMINUS 74
-#define KEY_KP4 75
-#define KEY_KP5 76
-#define KEY_KP6 77
-#define KEY_KPPLUS 78
-#define KEY_KP1 79
-#define KEY_KP2 80
-#define KEY_KP3 81
-#define KEY_KP0 82
-#define KEY_KPDOT 83
-
-#define KEY_ZENKAKUHANKAKU 85
-#define KEY_102ND 86
-#define KEY_F11 87
-#define KEY_F12 88
-#define KEY_RO 89
-#define KEY_KATAKANA 90
-#define KEY_HIRAGANA 91
-#define KEY_HENKAN 92
-#define KEY_KATAKANAHIRAGANA 93
-#define KEY_MUHENKAN 94
-#define KEY_KPJPCOMMA 95
-#define KEY_KPENTER 96
-#define KEY_RIGHTCTRL 97
-#define KEY_KPSLASH 98
-#define KEY_SYSRQ 99
-#define KEY_RIGHTALT 100
-#define KEY_LINEFEED 101
-#define KEY_HOME 102
-#define KEY_UP 103
-#define KEY_PAGEUP 104
-#define KEY_LEFT 105
-#define KEY_RIGHT 106
-#define KEY_END 107
-#define KEY_DOWN 108
-#define KEY_PAGEDOWN 109
-#define KEY_INSERT 110
-#define KEY_DELETE 111
-#define KEY_MACRO 112
-#define KEY_MUTE 113
-#define KEY_VOLUMEDOWN 114
-#define KEY_VOLUMEUP 115
-#define KEY_POWER 116 /* SC System Power Down */
-#define KEY_KPEQUAL 117
-#define KEY_KPPLUSMINUS 118
-#define KEY_PAUSE 119
-#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
-
-#define KEY_KPCOMMA 121
-#define KEY_HANGEUL 122
-#define KEY_HANGUEL KEY_HANGEUL
-#define KEY_HANJA 123
-#define KEY_YEN 124
-#define KEY_LEFTMETA 125
-#define KEY_RIGHTMETA 126
-#define KEY_COMPOSE 127
-
-#define KEY_STOP 128 /* AC Stop */
-#define KEY_AGAIN 129
-#define KEY_PROPS 130 /* AC Properties */
-#define KEY_UNDO 131 /* AC Undo */
-#define KEY_FRONT 132
-#define KEY_COPY 133 /* AC Copy */
-#define KEY_OPEN 134 /* AC Open */
-#define KEY_PASTE 135 /* AC Paste */
-#define KEY_FIND 136 /* AC Search */
-#define KEY_CUT 137 /* AC Cut */
-#define KEY_HELP 138 /* AL Integrated Help Center */
-#define KEY_MENU 139 /* Menu (show menu) */
-#define KEY_CALC 140 /* AL Calculator */
-#define KEY_SETUP 141
-#define KEY_SLEEP 142 /* SC System Sleep */
-#define KEY_WAKEUP 143 /* System Wake Up */
-#define KEY_FILE 144 /* AL Local Machine Browser */
-#define KEY_SENDFILE 145
-#define KEY_DELETEFILE 146
-#define KEY_XFER 147
-#define KEY_PROG1 148
-#define KEY_PROG2 149
-#define KEY_WWW 150 /* AL Internet Browser */
-#define KEY_MSDOS 151
-#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
-#define KEY_SCREENLOCK KEY_COFFEE
-#define KEY_DIRECTION 153
-#define KEY_CYCLEWINDOWS 154
-#define KEY_MAIL 155
-#define KEY_BOOKMARKS 156 /* AC Bookmarks */
-#define KEY_COMPUTER 157
-#define KEY_BACK 158 /* AC Back */
-#define KEY_FORWARD 159 /* AC Forward */
-#define KEY_CLOSECD 160
-#define KEY_EJECTCD 161
-#define KEY_EJECTCLOSECD 162
-#define KEY_NEXTSONG 163
-#define KEY_PLAYPAUSE 164
-#define KEY_PREVIOUSSONG 165
-#define KEY_STOPCD 166
-#define KEY_RECORD 167
-#define KEY_REWIND 168
-#define KEY_PHONE 169 /* Media Select Telephone */
-#define KEY_ISO 170
-#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
-#define KEY_HOMEPAGE 172 /* AC Home */
-#define KEY_REFRESH 173 /* AC Refresh */
-#define KEY_EXIT 174 /* AC Exit */
-#define KEY_MOVE 175
-#define KEY_EDIT 176
-#define KEY_SCROLLUP 177
-#define KEY_SCROLLDOWN 178
-#define KEY_KPLEFTPAREN 179
-#define KEY_KPRIGHTPAREN 180
-#define KEY_NEW 181 /* AC New */
-#define KEY_REDO 182 /* AC Redo/Repeat */
-
-#define KEY_F13 183
-#define KEY_F14 184
-#define KEY_F15 185
-#define KEY_F16 186
-#define KEY_F17 187
-#define KEY_F18 188
-#define KEY_F19 189
-#define KEY_F20 190
-#define KEY_F21 191
-#define KEY_F22 192
-#define KEY_F23 193
-#define KEY_F24 194
-
-#define KEY_PLAYCD 200
-#define KEY_PAUSECD 201
-#define KEY_PROG3 202
-#define KEY_PROG4 203
-#define KEY_DASHBOARD 204 /* AL Dashboard */
-#define KEY_SUSPEND 205
-#define KEY_CLOSE 206 /* AC Close */
-#define KEY_PLAY 207
-#define KEY_FASTFORWARD 208
-#define KEY_BASSBOOST 209
-#define KEY_PRINT 210 /* AC Print */
-#define KEY_HP 211
-#define KEY_CAMERA 212
-#define KEY_SOUND 213
-#define KEY_QUESTION 214
-#define KEY_EMAIL 215
-#define KEY_CHAT 216
-#define KEY_SEARCH 217
-#define KEY_CONNECT 218
-#define KEY_FINANCE 219 /* AL Checkbook/Finance */
-#define KEY_SPORT 220
-#define KEY_SHOP 221
-#define KEY_ALTERASE 222
-#define KEY_CANCEL 223 /* AC Cancel */
-#define KEY_BRIGHTNESSDOWN 224
-#define KEY_BRIGHTNESSUP 225
-#define KEY_MEDIA 226
-
-#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
- outputs (Monitor/LCD/TV-out/etc) */
-#define KEY_KBDILLUMTOGGLE 228
-#define KEY_KBDILLUMDOWN 229
-#define KEY_KBDILLUMUP 230
-
-#define KEY_SEND 231 /* AC Send */
-#define KEY_REPLY 232 /* AC Reply */
-#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
-#define KEY_SAVE 234 /* AC Save */
-#define KEY_DOCUMENTS 235
-
-#define KEY_BATTERY 236
-
-#define KEY_BLUETOOTH 237
-#define KEY_WLAN 238
-#define KEY_UWB 239
-
-#define KEY_UNKNOWN 240
-
-#define KEY_VIDEO_NEXT 241 /* drive next video source */
-#define KEY_VIDEO_PREV 242 /* drive previous video source */
-#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
-#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
- brightness control is off,
- rely on ambient */
-#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
-#define KEY_DISPLAY_OFF 245 /* display device to off state */
-
-#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
-#define KEY_WIMAX KEY_WWAN
-#define KEY_RFKILL 247 /* Key that controls all radios */
-
-#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
-
-/* Code 255 is reserved for special needs of AT keyboard driver */
-
-#define BTN_MISC 0x100
-#define BTN_0 0x100
-#define BTN_1 0x101
-#define BTN_2 0x102
-#define BTN_3 0x103
-#define BTN_4 0x104
-#define BTN_5 0x105
-#define BTN_6 0x106
-#define BTN_7 0x107
-#define BTN_8 0x108
-#define BTN_9 0x109
-
-#define BTN_MOUSE 0x110
-#define BTN_LEFT 0x110
-#define BTN_RIGHT 0x111
-#define BTN_MIDDLE 0x112
-#define BTN_SIDE 0x113
-#define BTN_EXTRA 0x114
-#define BTN_FORWARD 0x115
-#define BTN_BACK 0x116
-#define BTN_TASK 0x117
-
-#define BTN_JOYSTICK 0x120
-#define BTN_TRIGGER 0x120
-#define BTN_THUMB 0x121
-#define BTN_THUMB2 0x122
-#define BTN_TOP 0x123
-#define BTN_TOP2 0x124
-#define BTN_PINKIE 0x125
-#define BTN_BASE 0x126
-#define BTN_BASE2 0x127
-#define BTN_BASE3 0x128
-#define BTN_BASE4 0x129
-#define BTN_BASE5 0x12a
-#define BTN_BASE6 0x12b
-#define BTN_DEAD 0x12f
-
-#define BTN_GAMEPAD 0x130
-#define BTN_SOUTH 0x130
-#define BTN_A BTN_SOUTH
-#define BTN_EAST 0x131
-#define BTN_B BTN_EAST
-#define BTN_C 0x132
-#define BTN_NORTH 0x133
-#define BTN_X BTN_NORTH
-#define BTN_WEST 0x134
-#define BTN_Y BTN_WEST
-#define BTN_Z 0x135
-#define BTN_TL 0x136
-#define BTN_TR 0x137
-#define BTN_TL2 0x138
-#define BTN_TR2 0x139
-#define BTN_SELECT 0x13a
-#define BTN_START 0x13b
-#define BTN_MODE 0x13c
-#define BTN_THUMBL 0x13d
-#define BTN_THUMBR 0x13e
-
-#define BTN_DIGI 0x140
-#define BTN_TOOL_PEN 0x140
-#define BTN_TOOL_RUBBER 0x141
-#define BTN_TOOL_BRUSH 0x142
-#define BTN_TOOL_PENCIL 0x143
-#define BTN_TOOL_AIRBRUSH 0x144
-#define BTN_TOOL_FINGER 0x145
-#define BTN_TOOL_MOUSE 0x146
-#define BTN_TOOL_LENS 0x147
-#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
-#define BTN_TOUCH 0x14a
-#define BTN_STYLUS 0x14b
-#define BTN_STYLUS2 0x14c
-#define BTN_TOOL_DOUBLETAP 0x14d
-#define BTN_TOOL_TRIPLETAP 0x14e
-#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
-
-#define BTN_WHEEL 0x150
-#define BTN_GEAR_DOWN 0x150
-#define BTN_GEAR_UP 0x151
-
-#define KEY_OK 0x160
-#define KEY_SELECT 0x161
-#define KEY_GOTO 0x162
-#define KEY_CLEAR 0x163
-#define KEY_POWER2 0x164
-#define KEY_OPTION 0x165
-#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
-#define KEY_TIME 0x167
-#define KEY_VENDOR 0x168
-#define KEY_ARCHIVE 0x169
-#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
-#define KEY_CHANNEL 0x16b
-#define KEY_FAVORITES 0x16c
-#define KEY_EPG 0x16d
-#define KEY_PVR 0x16e /* Media Select Home */
-#define KEY_MHP 0x16f
-#define KEY_LANGUAGE 0x170
-#define KEY_TITLE 0x171
-#define KEY_SUBTITLE 0x172
-#define KEY_ANGLE 0x173
-#define KEY_ZOOM 0x174
-#define KEY_MODE 0x175
-#define KEY_KEYBOARD 0x176
-#define KEY_SCREEN 0x177
-#define KEY_PC 0x178 /* Media Select Computer */
-#define KEY_TV 0x179 /* Media Select TV */
-#define KEY_TV2 0x17a /* Media Select Cable */
-#define KEY_VCR 0x17b /* Media Select VCR */
-#define KEY_VCR2 0x17c /* VCR Plus */
-#define KEY_SAT 0x17d /* Media Select Satellite */
-#define KEY_SAT2 0x17e
-#define KEY_CD 0x17f /* Media Select CD */
-#define KEY_TAPE 0x180 /* Media Select Tape */
-#define KEY_RADIO 0x181
-#define KEY_TUNER 0x182 /* Media Select Tuner */
-#define KEY_PLAYER 0x183
-#define KEY_TEXT 0x184
-#define KEY_DVD 0x185 /* Media Select DVD */
-#define KEY_AUX 0x186
-#define KEY_MP3 0x187
-#define KEY_AUDIO 0x188 /* AL Audio Browser */
-#define KEY_VIDEO 0x189 /* AL Movie Browser */
-#define KEY_DIRECTORY 0x18a
-#define KEY_LIST 0x18b
-#define KEY_MEMO 0x18c /* Media Select Messages */
-#define KEY_CALENDAR 0x18d
-#define KEY_RED 0x18e
-#define KEY_GREEN 0x18f
-#define KEY_YELLOW 0x190
-#define KEY_BLUE 0x191
-#define KEY_CHANNELUP 0x192 /* Channel Increment */
-#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
-#define KEY_FIRST 0x194
-#define KEY_LAST 0x195 /* Recall Last */
-#define KEY_AB 0x196
-#define KEY_NEXT 0x197
-#define KEY_RESTART 0x198
-#define KEY_SLOW 0x199
-#define KEY_SHUFFLE 0x19a
-#define KEY_BREAK 0x19b
-#define KEY_PREVIOUS 0x19c
-#define KEY_DIGITS 0x19d
-#define KEY_TEEN 0x19e
-#define KEY_TWEN 0x19f
-#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
-#define KEY_GAMES 0x1a1 /* Media Select Games */
-#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
-#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
-#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
-#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
-#define KEY_EDITOR 0x1a6 /* AL Text Editor */
-#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
-#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
-#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
-#define KEY_DATABASE 0x1aa /* AL Database App */
-#define KEY_NEWS 0x1ab /* AL Newsreader */
-#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
-#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
-#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
-#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
-#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
-#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
-#define KEY_LOGOFF 0x1b1 /* AL Logoff */
-
-#define KEY_DOLLAR 0x1b2
-#define KEY_EURO 0x1b3
-
-#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
-#define KEY_FRAMEFORWARD 0x1b5
-#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
-#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
-#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
-#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
-#define KEY_IMAGES 0x1ba /* AL Image Browser */
-
-#define KEY_DEL_EOL 0x1c0
-#define KEY_DEL_EOS 0x1c1
-#define KEY_INS_LINE 0x1c2
-#define KEY_DEL_LINE 0x1c3
-
-#define KEY_FN 0x1d0
-#define KEY_FN_ESC 0x1d1
-#define KEY_FN_F1 0x1d2
-#define KEY_FN_F2 0x1d3
-#define KEY_FN_F3 0x1d4
-#define KEY_FN_F4 0x1d5
-#define KEY_FN_F5 0x1d6
-#define KEY_FN_F6 0x1d7
-#define KEY_FN_F7 0x1d8
-#define KEY_FN_F8 0x1d9
-#define KEY_FN_F9 0x1da
-#define KEY_FN_F10 0x1db
-#define KEY_FN_F11 0x1dc
-#define KEY_FN_F12 0x1dd
-#define KEY_FN_1 0x1de
-#define KEY_FN_2 0x1df
-#define KEY_FN_D 0x1e0
-#define KEY_FN_E 0x1e1
-#define KEY_FN_F 0x1e2
-#define KEY_FN_S 0x1e3
-#define KEY_FN_B 0x1e4
-
-#define KEY_BRL_DOT1 0x1f1
-#define KEY_BRL_DOT2 0x1f2
-#define KEY_BRL_DOT3 0x1f3
-#define KEY_BRL_DOT4 0x1f4
-#define KEY_BRL_DOT5 0x1f5
-#define KEY_BRL_DOT6 0x1f6
-#define KEY_BRL_DOT7 0x1f7
-#define KEY_BRL_DOT8 0x1f8
-#define KEY_BRL_DOT9 0x1f9
-#define KEY_BRL_DOT10 0x1fa
-
-#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
-#define KEY_NUMERIC_1 0x201 /* and other keypads */
-#define KEY_NUMERIC_2 0x202
-#define KEY_NUMERIC_3 0x203
-#define KEY_NUMERIC_4 0x204
-#define KEY_NUMERIC_5 0x205
-#define KEY_NUMERIC_6 0x206
-#define KEY_NUMERIC_7 0x207
-#define KEY_NUMERIC_8 0x208
-#define KEY_NUMERIC_9 0x209
-#define KEY_NUMERIC_STAR 0x20a
-#define KEY_NUMERIC_POUND 0x20b
-
-#define KEY_CAMERA_FOCUS 0x210
-#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
-
-#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
-#define KEY_TOUCHPAD_ON 0x213
-#define KEY_TOUCHPAD_OFF 0x214
-
-#define KEY_CAMERA_ZOOMIN 0x215
-#define KEY_CAMERA_ZOOMOUT 0x216
-#define KEY_CAMERA_UP 0x217
-#define KEY_CAMERA_DOWN 0x218
-#define KEY_CAMERA_LEFT 0x219
-#define KEY_CAMERA_RIGHT 0x21a
-
-#define KEY_ATTENDANT_ON 0x21b
-#define KEY_ATTENDANT_OFF 0x21c
-#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
-#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
-
-#define BTN_DPAD_UP 0x220
-#define BTN_DPAD_DOWN 0x221
-#define BTN_DPAD_LEFT 0x222
-#define BTN_DPAD_RIGHT 0x223
-
-#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
-
-#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
-#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
-#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
-#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
-#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
-#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
-#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
-
-#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
-#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
-
-#define BTN_TRIGGER_HAPPY 0x2c0
-#define BTN_TRIGGER_HAPPY1 0x2c0
-#define BTN_TRIGGER_HAPPY2 0x2c1
-#define BTN_TRIGGER_HAPPY3 0x2c2
-#define BTN_TRIGGER_HAPPY4 0x2c3
-#define BTN_TRIGGER_HAPPY5 0x2c4
-#define BTN_TRIGGER_HAPPY6 0x2c5
-#define BTN_TRIGGER_HAPPY7 0x2c6
-#define BTN_TRIGGER_HAPPY8 0x2c7
-#define BTN_TRIGGER_HAPPY9 0x2c8
-#define BTN_TRIGGER_HAPPY10 0x2c9
-#define BTN_TRIGGER_HAPPY11 0x2ca
-#define BTN_TRIGGER_HAPPY12 0x2cb
-#define BTN_TRIGGER_HAPPY13 0x2cc
-#define BTN_TRIGGER_HAPPY14 0x2cd
-#define BTN_TRIGGER_HAPPY15 0x2ce
-#define BTN_TRIGGER_HAPPY16 0x2cf
-#define BTN_TRIGGER_HAPPY17 0x2d0
-#define BTN_TRIGGER_HAPPY18 0x2d1
-#define BTN_TRIGGER_HAPPY19 0x2d2
-#define BTN_TRIGGER_HAPPY20 0x2d3
-#define BTN_TRIGGER_HAPPY21 0x2d4
-#define BTN_TRIGGER_HAPPY22 0x2d5
-#define BTN_TRIGGER_HAPPY23 0x2d6
-#define BTN_TRIGGER_HAPPY24 0x2d7
-#define BTN_TRIGGER_HAPPY25 0x2d8
-#define BTN_TRIGGER_HAPPY26 0x2d9
-#define BTN_TRIGGER_HAPPY27 0x2da
-#define BTN_TRIGGER_HAPPY28 0x2db
-#define BTN_TRIGGER_HAPPY29 0x2dc
-#define BTN_TRIGGER_HAPPY30 0x2dd
-#define BTN_TRIGGER_HAPPY31 0x2de
-#define BTN_TRIGGER_HAPPY32 0x2df
-#define BTN_TRIGGER_HAPPY33 0x2e0
-#define BTN_TRIGGER_HAPPY34 0x2e1
-#define BTN_TRIGGER_HAPPY35 0x2e2
-#define BTN_TRIGGER_HAPPY36 0x2e3
-#define BTN_TRIGGER_HAPPY37 0x2e4
-#define BTN_TRIGGER_HAPPY38 0x2e5
-#define BTN_TRIGGER_HAPPY39 0x2e6
-#define BTN_TRIGGER_HAPPY40 0x2e7
-
-/* We avoid low common keys in module aliases so they don't get huge. */
-#define KEY_MIN_INTERESTING KEY_MUTE
-#define KEY_MAX 0x2ff
-#define KEY_CNT (KEY_MAX+1)
-
-/*
- * Relative axes
- */
-
-#define REL_X 0x00
-#define REL_Y 0x01
-#define REL_Z 0x02
-#define REL_RX 0x03
-#define REL_RY 0x04
-#define REL_RZ 0x05
-#define REL_HWHEEL 0x06
-#define REL_DIAL 0x07
-#define REL_WHEEL 0x08
-#define REL_MISC 0x09
-#define REL_MAX 0x0f
-#define REL_CNT (REL_MAX+1)
-
-/*
- * Absolute axes
- */
-
-#define ABS_X 0x00
-#define ABS_Y 0x01
-#define ABS_Z 0x02
-#define ABS_RX 0x03
-#define ABS_RY 0x04
-#define ABS_RZ 0x05
-#define ABS_THROTTLE 0x06
-#define ABS_RUDDER 0x07
-#define ABS_WHEEL 0x08
-#define ABS_GAS 0x09
-#define ABS_BRAKE 0x0a
-#define ABS_HAT0X 0x10
-#define ABS_HAT0Y 0x11
-#define ABS_HAT1X 0x12
-#define ABS_HAT1Y 0x13
-#define ABS_HAT2X 0x14
-#define ABS_HAT2Y 0x15
-#define ABS_HAT3X 0x16
-#define ABS_HAT3Y 0x17
-#define ABS_PRESSURE 0x18
-#define ABS_DISTANCE 0x19
-#define ABS_TILT_X 0x1a
-#define ABS_TILT_Y 0x1b
-#define ABS_TOOL_WIDTH 0x1c
-
-#define ABS_VOLUME 0x20
-
-#define ABS_MISC 0x28
-
-#define ABS_MT_SLOT 0x2f /* MT slot being modified */
-#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
-#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
-#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
-#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
-#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
-#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
-#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
-#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
-#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
-#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
-#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
-#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
-#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
-#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
-
-
-#define ABS_MAX 0x3f
-#define ABS_CNT (ABS_MAX+1)
-
-/*
- * Switch events
- */
-
-#define SW_LID 0x00 /* set = lid shut */
-#define SW_TABLET_MODE 0x01 /* set = tablet mode */
-#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
-#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
- set = radio enabled */
-#define SW_RADIO SW_RFKILL_ALL /* deprecated */
-#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
-#define SW_DOCK 0x05 /* set = plugged into dock */
-#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
-#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
-#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
-#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
-#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
-#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
-#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
-#define SW_LINEIN_INSERT 0x0d /* set = inserted */
-#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
-#define SW_MAX 0x0f
-#define SW_CNT (SW_MAX+1)
-
-/*
- * Misc events
- */
-
-#define MSC_SERIAL 0x00
-#define MSC_PULSELED 0x01
-#define MSC_GESTURE 0x02
-#define MSC_RAW 0x03
-#define MSC_SCAN 0x04
-#define MSC_TIMESTAMP 0x05
-#define MSC_MAX 0x07
-#define MSC_CNT (MSC_MAX+1)
-
-/*
- * LEDs
- */
-
-#define LED_NUML 0x00
-#define LED_CAPSL 0x01
-#define LED_SCROLLL 0x02
-#define LED_COMPOSE 0x03
-#define LED_KANA 0x04
-#define LED_SLEEP 0x05
-#define LED_SUSPEND 0x06
-#define LED_MUTE 0x07
-#define LED_MISC 0x08
-#define LED_MAIL 0x09
-#define LED_CHARGING 0x0a
-#define LED_MAX 0x0f
-#define LED_CNT (LED_MAX+1)
-
-/*
- * Autorepeat values
- */
-
-#define REP_DELAY 0x00
-#define REP_PERIOD 0x01
-#define REP_MAX 0x01
-#define REP_CNT (REP_MAX+1)
-
-/*
- * Sounds
- */
-
-#define SND_CLICK 0x00
-#define SND_BELL 0x01
-#define SND_TONE 0x02
-#define SND_MAX 0x07
-#define SND_CNT (SND_MAX+1)
-
-/*
- * IDs.
- */
-
-#define ID_BUS 0
-#define ID_VENDOR 1
-#define ID_PRODUCT 2
-#define ID_VERSION 3
-
-#define BUS_PCI 0x01
-#define BUS_ISAPNP 0x02
-#define BUS_USB 0x03
-#define BUS_HIL 0x04
-#define BUS_BLUETOOTH 0x05
-#define BUS_VIRTUAL 0x06
-
-#define BUS_ISA 0x10
-#define BUS_I8042 0x11
-#define BUS_XTKBD 0x12
-#define BUS_RS232 0x13
-#define BUS_GAMEPORT 0x14
-#define BUS_PARPORT 0x15
-#define BUS_AMIGA 0x16
-#define BUS_ADB 0x17
-#define BUS_I2C 0x18
-#define BUS_HOST 0x19
-#define BUS_GSC 0x1A
-#define BUS_ATARI 0x1B
-#define BUS_SPI 0x1C
-
-/*
- * MT_TOOL types
- */
-#define MT_TOOL_FINGER 0
-#define MT_TOOL_PEN 1
-#define MT_TOOL_MAX 1
-
-/*
- * Values describing the status of a force-feedback effect
- */
-#define FF_STATUS_STOPPED 0x00
-#define FF_STATUS_PLAYING 0x01
-#define FF_STATUS_MAX 0x01
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip,boot-mode.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip,boot-mode.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip,boot-mode.h (nonexistent)
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ROCKCHIP_BOOT_MODE_H
-#define __ROCKCHIP_BOOT_MODE_H
-
-/*high 24 bits is tag, low 8 bits is type*/
-#define REBOOT_FLAG 0x5242C300
-/* normal boot */
-#define BOOT_NORMAL (REBOOT_FLAG + 0)
-/* enter bootloader rockusb mode */
-#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
-/* enter recovery */
-#define BOOT_RECOVERY (REBOOT_FLAG + 3)
-/* reboot by panic */
-#define BOOT_PANIC (REBOOT_FLAG + 7)
-/* reboot by watchdog */
-#define BOOT_WATCHDOG (REBOOT_FLAG + 8)
-/* enter fastboot mode */
-#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
-/* enter charging mode */
-#define BOOT_CHARGING (REBOOT_FLAG + 11)
-/* enter usb mass storage mode */
-#define BOOT_UMS (REBOOT_FLAG + 12)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip-system-status.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip-system-status.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip-system-status.h (nonexistent)
@@ -1,50 +0,0 @@
-/*
- *
- * Copyright (C) 2017 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H
-#define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H
-
-#define SYS_STATUS_NORMAL (1 << 0)
-#define SYS_STATUS_SUSPEND (1 << 1)
-#define SYS_STATUS_IDLE (1 << 2)
-#define SYS_STATUS_REBOOT (1 << 3)
-#define SYS_STATUS_VIDEO_4K (1 << 4)
-#define SYS_STATUS_VIDEO_1080P (1 << 5)
-#define SYS_STATUS_GPU (1 << 6)
-#define SYS_STATUS_RGA (1 << 7)
-#define SYS_STATUS_CIF0 (1 << 8)
-#define SYS_STATUS_CIF1 (1 << 9)
-#define SYS_STATUS_LCDC0 (1 << 10)
-#define SYS_STATUS_LCDC1 (1 << 11)
-#define SYS_STATUS_BOOST (1 << 12)
-#define SYS_STATUS_PERFORMANCE (1 << 13)
-#define SYS_STATUS_ISP (1 << 14)
-#define SYS_STATUS_HDMI (1 << 15)
-#define SYS_STATUS_VIDEO_4K_10B (1 << 16)
-#define SYS_STATUS_LOW_POWER (1 << 17)
-#define SYS_STATUS_HDMIRX (1 << 18)
-#define SYS_STATUS_VIDEO_SVEP (1 << 19)
-
-#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \
- SYS_STATUS_VIDEO_1080P | \
- SYS_STATUS_VIDEO_4K_10B)
-#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1)
-
-#define DMC_FREQ_LEVEL_LOW (0x1 << 0)
-#define DMC_FREQ_LEVEL_MID_LOW (0x1 << 1)
-#define DMC_FREQ_LEVEL_MID_HIGH (0x1 << 2)
-#define DMC_FREQ_LEVEL_HIGH (0x1 << 3)
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/sensor-dev.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/sensor-dev.h (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/sensor-dev.h (nonexistent)
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__
-#define __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__
-
-#define SENSOR_TYPE_NULL 0
-#define SENSOR_TYPE_ANGLE 1
-#define SENSOR_TYPE_ACCEL 2
-#define SENSOR_TYPE_COMPASS 3
-#define SENSOR_TYPE_GYROSCOPE 4
-#define SENSOR_TYPE_LIGHT 5
-#define SENSOR_TYPE_PROXIMITY 6
-#define SENSOR_TYPE_TEMPERATURE 7
-#define SENSOR_TYPE_PRESSURE 8
-#define SENSOR_TYPE_HALL 9
-#define SENSOR_NUM_TYPES 10
-
-#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtsi (nonexistent)
@@ -1,770 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include "dt-bindings/usb/pd.h"
-#include "rk3588.dtsi"
-#include "rk3588-orangepi.dtsi"
-#include "rk3588-rk806-single.dtsi"
-
-/ {
- /* If hdmirx node is disabled, delete the reserved-memory node here. */
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* Reserve 128MB memory for hdmirx-controller@fdee0000 */
- cma {
- compatible = "shared-dma-pool";
- reusable;
- reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>;
- linux,cma-default;
- };
- };
-
- hdmiin_dc: hdmiin-dc {
- compatible = "rockchip,dummy-codec";
- #sound-dai-cells = <0>;
- };
-
- es8388_sound: es8388-sound {
- status = "okay";
- compatible = "rockchip,multicodecs-card";
- rockchip,card-name = "rockchip,es8388";
- hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
- io-channels = <&saradc 3>;
- io-channel-names = "adc-detect";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
- spk-con-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- hp-con-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
- rockchip,format = "i2s";
- rockchip,mclk-fs = <256>;
- rockchip,cpu = <&i2s0_8ch>;
- rockchip,codec = <&es8388>;
- rockchip,audio-routing =
- "Headphone", "LOUT1",
- "Headphone", "ROUT1",
- "Speaker", "LOUT2",
- "Speaker", "ROUT2",
- "Headphone", "Headphone Power",
- "Headphone", "Headphone Power",
- "Speaker", "Speaker Power",
- "Speaker", "Speaker Power",
- "LINPUT1", "Main Mic",
- "LINPUT2", "Main Mic",
- "RINPUT1", "Headset Mic",
- "RINPUT2", "Headset Mic";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det>;
- play-pause-key {
- label = "playpause";
- linux,code = <KEY_PLAYPAUSE>;
- press-threshold-microvolt = <2000>;
- };
- };
-
- hdmiin-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "rockchip,hdmiin";
- simple-audio-card,bitclock-master = <&dailink0_master>;
- simple-audio-card,frame-master = <&dailink0_master>;
- status = "okay";
- simple-audio-card,cpu {
- sound-dai = <&i2s7_8ch>;
- };
- dailink0_master: simple-audio-card,codec {
- sound-dai = <&hdmiin_dc>;
- };
- };
-
- pcie20_avdd0v85: pcie20-avdd0v85 {
- compatible = "regulator-fixed";
- regulator-name = "pcie20_avdd0v85";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- vin-supply = <&vdd_0v85_s0>;
- };
-
- pcie20_avdd1v8: pcie20-avdd1v8 {
- compatible = "regulator-fixed";
- regulator-name = "pcie20_avdd1v8";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&avcc_1v8_s0>;
- };
-
- pcie30_avdd0v75: pcie30-avdd0v75 {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v75";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- vin-supply = <&avdd_0v75_s0>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8 {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&avcc_1v8_s0>;
- };
-
- rk_headset: rk-headset {
- status = "disabled";
- compatible = "rockchip_headset";
- headset_gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det>;
- io-channels = <&saradc 3>;
- };
-
- vbus5v0_typec: vbus5v0-typec {
- compatible = "regulator-fixed";
- regulator-name = "vbus5v0_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_usb>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host: vcc5v0-host {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_usb>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- };
-
- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie2x1l0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_pcie_eth: vcc3v3-pcie-eth {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie_eth";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- enable-active-low;
- gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_mipicsi0: vcc-mipicsi0-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_mipicsi0";
- enable-active-high;
- };
-
- vcc_mipicsi1: vcc-mipicsi1-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_mipicsi1";
- enable-active-high;
- };
-
- vcc_mipidcphy0: vcc-mipidcphy0-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_mipicsi1";
- enable-active-high;
- };
-
- wireless_bluetooth: wireless-bluetooth {
- compatible = "bluetooth-platdata";
- clocks = <&hym8563>;
- clock-names = "ext_clock";
- uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "rts_gpio";
- pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
- pinctrl-1 = <&uart9_gpios>;
- BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
- BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- status = "disabled";
- };
-
- wireless_wlan: wireless-wlan {
- compatible = "wlan-platdata";
- wifi_chip_type = "ap6275p";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_irq>;
- WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
- status = "disabled";
- };
-
- wifi_disable: wifi-diable-gpio-regulator {
- compatible = "regulator-fixed";
- regulator-name = "wifi_disable";
- enable-active-high;
- gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&backlight {
- pwms = <&pwm2 0 25000 0>;
- status = "okay";
-};
-
-&can2 {
- status = "disabled";
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy1_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&dp0 {
- status = "okay";
-};
-
-&dp0_in_vp0 {
- status = "disabled";
-};
-
-&dp0_in_vp1 {
- status = "disabled";
-};
-
-&dp0_in_vp2 {
- status = "okay";
-};
-
-&dp0_sound{
- status = "okay";
-};
-
-&spdif_tx2{
- status = "okay";
-};
-
-/*
- * mipi_dcphy0 needs to be enabled
- * when dsi0 is enabled
- */
-&dsi0 {
- status = "disabled";
-};
-
-&dsi0_in_vp2 {
- status = "disabled";
-};
-
-&dsi0_in_vp3 {
- status = "disabled";
-};
-
-&dsi0_panel {
- status = "disabled";
-};
-
-/*
- * mipi_dcphy1 needs to be enabled
- * when dsi1 is enabled
- */
-&dsi1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&mipi_te1>;
-};
-
-&dsi1_in_vp2 {
- status = "disabled";
-};
-
-&dsi1_in_vp3 {
- status = "disabled";
-};
-
-&dsi1_panel {
- status = "disabled";
-};
-
-&gmac0 {
- status = "disabled";
-};
-
-&hdmi0 {
- status = "okay";
- enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
- cec-enable = "true";
-};
-
-&hdmi0_in_vp0 {
- status = "okay";
-};
-
-&hdmi0_in_vp1 {
- status = "disabled";
-};
-
-&hdmi0_in_vp2 {
- status = "disabled";
-};
-
-&hdmi0_sound {
- status = "okay";
-};
-
-&hdmi1 {
- status = "okay";
- enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
- cec-enable = "true";
-};
-
-&hdmi1_in_vp0 {
- status = "disabled";
-};
-
-&hdmi1_in_vp1 {
- status = "okay";
-};
-
-&hdmi1_in_vp2 {
- status = "disabled";
-};
-
-&hdmi1_sound {
- status = "okay";
-};
-
-/* Should work with at least 128MB cma reserved above. */
-&hdmirx_ctrler {
- status = "disabled";
-
- /* Effective level used to trigger HPD: 0-low, 1-high */
- hpd-trigger-level = <1>;
- hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>;
-};
-
-&hdptxphy_hdmi0 {
- status = "okay";
-};
-
-&hdptxphy_hdmi1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
-
- vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_cpu_big0_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
- compatible = "rockchip,rk8603";
- reg = <0x43>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_cpu_big1_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- status = "okay";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6m0_xfer>;
-
- usbc0: fusb302@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&usbc0_int>;
- vbus-supply = <&vbus5v0_typec>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_role_sw: endpoint@0 {
- remote-endpoint = <&dwc3_0_role_switch>;
- };
- };
- };
-
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
- power-role = "dual";
- try-power-role = "sink";
- op-sink-microwatt = <1000000>;
- sink-pdos =
- <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-
- altmodes {
- #address-cells = <1>;
- #size-cells = <0>;
-
- altmode@0 {
- reg = <0>;
- svid = <0xff01>;
- vdo = <0xffffffff>;
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_orien_sw: endpoint {
- remote-endpoint = <&usbdp_phy0_orientation_switch>;
- };
- };
-
- port@1 {
- reg = <1>;
- dp_altmode_mux: endpoint {
- remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
- };
- };
- };
- };
- };
-
- hym8563: hym8563@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
- status = "okay";
- };
-
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1m2_xfer>;
-
- vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_npu_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c7 {
- status = "okay";
- es8388: es8388@11 {
- status = "okay";
- #sound-dai-cells = <0>;
- compatible = "everest,es8388", "everest,es8323";
- reg = <0x11>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_mclk>;
- };
-};
-
-&i2s5_8ch {
- status = "okay";
-};
-
-&i2s6_8ch {
- status = "okay";
-};
-
-&i2s7_8ch {
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy: phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- };
-};
-
-&mipi_dcphy0 {
- status = "disabled";
-};
-
-&mipi_dcphy1 {
- status = "disabled";
-};
-
-//phy1
-&pcie2x1l0 {
- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
- rockchip,skip-scan-in-resume;
- status = "okay";
-};
-
-//phy2
-&pcie2x1l1 {
- reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-//phy0
-&pcie2x1l2 {
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie30phy {
- rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
- status = "okay";
-};
-
-&pcie3x4 {
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&pinctrl {
- hdmi {
- hdmirx_det: hdmirx-det {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- lcd {
- lcd_rst_gpio: lcd-rst-gpio {
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- usbc0_int: usbc0-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wireless-bluetooth {
- uart9_gpios: uart9-gpios {
- rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_reset_gpio: bt-reset-gpio {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_gpio: bt-wake-gpio {
- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_irq_gpio: bt-irq-gpio {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- wireless-wlan {
- wifi_host_wake_irq: wifi-host-wake-irq {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdmmc {
- sdmmc_pwr: sdmmc_pwr {
- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-};
-
-&pwm2 {
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2m2_pins>;
- status = "okay";
-};
-
-&sata0 {
- status = "disabled";
-};
-
-&u2phy1_otg {
- phy-supply = <&vcc5v0_host>;
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
-};
-
-&uart9 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
-};
-
-&usbdp_phy0 {
- orientation-switch;
- svid = <0xff01>;
- sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
- sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- usbdp_phy0_orientation_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_orien_sw>;
- };
-
- usbdp_phy0_dp_altmode_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dp_altmode_mux>;
- };
- };
-};
-
-&usbdp_phy1 {
- rockchip,dp-lane-mux = <2 3>;
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
- usb-role-switch;
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- dwc3_0_role_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_role_sw>;
- };
- };
-};
-
-&usbhost3_0 {
- status = "disabled";
-};
-
-&usbhost_dwc3_0 {
- status = "disabled";
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi (nonexistent)
@@ -1,417 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020~2021 Rockchip Electronics Co., Ltd.
- */
-
-&pinctrl {
-
- /omit-if-no-ref/
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
- bias-disable;
- drive-strength = <0>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
- bias-disable;
- drive-strength = <1>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
- bias-disable;
- drive-strength = <2>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
- bias-disable;
- drive-strength = <3>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
- bias-disable;
- drive-strength = <4>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
- bias-disable;
- drive-strength = <5>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
- bias-disable;
- drive-strength = <6>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
- bias-disable;
- drive-strength = <7>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
- bias-disable;
- drive-strength = <8>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
- bias-disable;
- drive-strength = <9>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
- bias-disable;
- drive-strength = <10>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
- bias-disable;
- drive-strength = <11>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
- bias-disable;
- drive-strength = <12>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
- bias-disable;
- drive-strength = <13>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
- bias-disable;
- drive-strength = <14>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
- bias-disable;
- drive-strength = <15>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
- bias-pull-up;
- drive-strength = <0>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
- bias-pull-up;
- drive-strength = <1>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
- bias-pull-up;
- drive-strength = <2>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
- bias-pull-up;
- drive-strength = <3>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
- bias-pull-up;
- drive-strength = <4>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
- bias-pull-up;
- drive-strength = <5>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
- bias-pull-up;
- drive-strength = <6>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
- bias-pull-up;
- drive-strength = <7>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
- bias-pull-up;
- drive-strength = <9>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
- bias-pull-up;
- drive-strength = <10>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
- bias-pull-up;
- drive-strength = <11>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
- bias-pull-up;
- drive-strength = <12>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
- bias-pull-up;
- drive-strength = <13>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
- bias-pull-up;
- drive-strength = <14>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
- bias-pull-up;
- drive-strength = <15>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
- bias-pull-down;
- drive-strength = <0>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
- bias-pull-down;
- drive-strength = <1>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
- bias-pull-down;
- drive-strength = <2>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
- bias-pull-down;
- drive-strength = <3>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
- bias-pull-down;
- drive-strength = <4>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
- bias-pull-down;
- drive-strength = <5>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
- bias-pull-down;
- drive-strength = <6>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
- bias-pull-down;
- drive-strength = <7>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
- bias-pull-down;
- drive-strength = <8>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
- bias-pull-down;
- drive-strength = <9>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
- bias-pull-down;
- drive-strength = <10>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
- bias-pull-down;
- drive-strength = <11>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
- bias-pull-down;
- drive-strength = <12>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
- bias-pull-down;
- drive-strength = <13>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
- bias-pull-down;
- drive-strength = <14>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
- bias-pull-down;
- drive-strength = <15>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_smt: pcfg-pull-up-smt {
- bias-pull-up;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_smt: pcfg-pull-down-smt {
- bias-pull-down;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_smt: pcfg-pull-none-smt {
- bias-disable;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
- bias-disable;
- drive-strength = <0>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
- bias-disable;
- drive-strength = <1>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
- bias-disable;
- drive-strength = <2>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
- bias-disable;
- drive-strength = <3>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
- bias-disable;
- drive-strength = <4>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
- bias-disable;
- drive-strength = <5>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- /omit-if-no-ref/
- pcfg_output_high_pull_up: pcfg-output-high-pull-up {
- output-high;
- bias-pull-up;
- };
-
- /omit-if-no-ref/
- pcfg_output_high_pull_down: pcfg-output-high-pull-down {
- output-high;
- bias-pull-down;
- };
-
- /omit-if-no-ref/
- pcfg_output_high_pull_none: pcfg-output-high-pull-none {
- output-high;
- bias-disable;
- };
-
- /omit-if-no-ref/
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- /omit-if-no-ref/
- pcfg_output_low_pull_up: pcfg-output-low-pull-up {
- output-low;
- bias-pull-up;
- };
-
- /omit-if-no-ref/
- pcfg_output_low_pull_down: pcfg-output-low-pull-down {
- output-low;
- bias-pull-down;
- };
-
- /omit-if-no-ref/
- pcfg_output_low_pull_none: pcfg-output-low-pull-none {
- output-low;
- bias-disable;
- };
-};
-
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi (nonexistent)
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-&dsi0 {
- status = "disabled";
-};
-
-&dsi0_panel {
- status = "disabled";
- reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
- enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd0_rst_gpio>;
-};
-
-&dsi0_in_vp2 {
- status = "disabled";
-};
-
-&dsi0_in_vp3 {
- status = "disabled";
-};
-
-&route_dsi0 {
- status = "disabled";
- connect = <&vp3_out_dsi0>;
-};
-
-&mipi_dcphy0 {
- status = "okay";
-};
-
-&i2c7 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7m0_xfer>;
-
- gt9xx_1: touchscreen@14 {
- compatible = "goodix,gt9271";
- reg = <0x14>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
- irq-gpios = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
- touchscreen-inverted-x;
- //touchscreen-inverted-y;
- touchscreen-swapped-x-y;
- touchscreen-size-x = <1280>;
- touchscreen-size-y = <800>;
- status = "okay";
- };
-};
-
-
-
-&dsi1 {
- status = "disabled";
-};
-
-&dsi1_panel {
- status = "disabled";
- reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
- enable-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd1_rst_gpio>;
-};
-
-&dsi1_in_vp2 {
- status = "disabled";
-};
-
-&dsi1_in_vp3 {
- status = "disabled";
-};
-
-&route_dsi1 {
- status = "disabled";
- connect = <&vp3_out_dsi1>;
-};
-
-&mipi_dcphy1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-
- gt9xx_0: touchscreen@14 {
- compatible = "goodix,gt9271";
- reg = <0x14>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
- irq-gpios = <&gpio1 RK_PA7 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
- touchscreen-inverted-x;
- //touchscreen-inverted-y;
- touchscreen-swapped-x-y;
- touchscreen-size-x = <1280>;
- touchscreen-size-y = <800>;
- status = "okay";
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588.dtsi (nonexistent)
@@ -1,966 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/phy/phy-snps-pcie3.h>
-#include "rk3588s.dtsi"
-#include "rk3588-vccio3-pinctrl.dtsi"
-
-/ {
- aliases {
- csi2dphy3 = &csi2_dphy3;
- csi2dphy4 = &csi2_dphy4;
- csi2dphy5 = &csi2_dphy5;
- dp0 = &dp0;
- dp1 = &dp1;
- edp0 = &edp0;
- edp1 = &edp1;
- ethernet0 = &gmac0;
- hdptx0 = &hdptxphy0;
- hdptx1 = &hdptxphy1;
- hdptxhdmi0 = &hdptxphy_hdmi0;
- hdptxhdmi1 = &hdptxphy_hdmi1;
- hdmi0 = &hdmi0;
- hdmi1 = &hdmi1;
- rkcif_mipi_lvds4= &rkcif_mipi_lvds4;
- rkcif_mipi_lvds5= &rkcif_mipi_lvds5;
- usbdp0 = &usbdp_phy0;
- usbdp1 = &usbdp_phy1;
- };
-
- /* dphy1 full mode */
- csi2_dphy3: csi2-dphy3 {
- compatible = "rockchip,rk3568-csi2-dphy";
- rockchip,hw = <&csi2_dphy1_hw>;
- status = "disabled";
- };
-
- /* dphy1 split mode 01 */
- csi2_dphy4: csi2-dphy4 {
- compatible = "rockchip,rk3568-csi2-dphy";
- rockchip,hw = <&csi2_dphy1_hw>;
- status = "disabled";
- };
-
- /* dphy1 split mode 23 */
- csi2_dphy5: csi2-dphy5 {
- compatible = "rockchip,rk3568-csi2-dphy";
- rockchip,hw = <&csi2_dphy1_hw>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
- compatible = "rockchip,rkcif-mipi-lvds";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds4>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds4>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds4>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds4>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds5: rkcif-mipi-lvds5 {
- compatible = "rockchip,rkcif-mipi-lvds";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds5_sditf: rkcif-mipi-lvds5-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds5>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds5_sditf_vir1: rkcif-mipi-lvds5-sditf-vir1 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds5>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds5_sditf_vir2: rkcif-mipi-lvds5-sditf-vir2 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds5>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds5_sditf_vir3: rkcif-mipi-lvds5-sditf-vir3 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds5>;
- status = "disabled";
- };
-
- usbdrd3_1: usbdrd3_1 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
- <&cru ACLK_USB3OTG1>;
- clock-names = "ref", "suspend", "bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- usbdrd_dwc3_1: usb@fc400000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfc400000 0x0 0x400000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG1>;
- reset-names = "usb3-otg";
- dr_mode = "host";
- phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,parkmode-disable-ss-quirk;
- status = "disabled";
- };
- };
-
- pcie30_phy_grf: syscon@fd5b8000 {
- compatible = "rockchip,pcie30-phy-grf", "syscon";
- reg = <0x0 0xfd5b8000 0x0 0x10000>;
- };
-
- pipe_phy1_grf: syscon@fd5c0000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5c0000 0x0 0x100>;
- };
-
- usbdpphy1_grf: syscon@fd5cc000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5cc000 0x0 0x4000>;
- };
-
- usb2phy1_grf: syscon@fd5d4000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xfd5d4000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy1: usb2-phy@4000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x4000 0x10>;
- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
- reset-names = "phy", "apb";
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy1";
- #clock-cells = <0>;
- rockchip,usbctrl-grf = <&usb_grf>;
- status = "disabled";
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- hdptxphy1_grf: syscon@fd5e4000 {
- compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
- reg = <0x0 0xfd5e4000 0x0 0x100>;
- };
-
- mipi4_csi2: mipi4-csi2@fdd50000 {
- compatible = "rockchip,rk3588-mipi-csi2";
- reg = <0x0 0xfdd50000 0x0 0x10000>;
- reg-names = "csihost_regs";
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "csi-intr1", "csi-intr2";
- clocks = <&cru PCLK_CSI_HOST_4>;
- clock-names = "pclk_csi2host";
- resets = <&cru SRST_P_CSI_HOST_4>, <&cru SRST_CSIHOST4_VICAP>;
- reset-names = "srst_csihost_p", "srst_csihost_vicap";
- status = "disabled";
- };
-
- mipi5_csi2: mipi5-csi2@fdd60000 {
- compatible = "rockchip,rk3588-mipi-csi2";
- reg = <0x0 0xfdd60000 0x0 0x10000>;
- reg-names = "csihost_regs";
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "csi-intr1", "csi-intr2";
- clocks = <&cru PCLK_CSI_HOST_5>;
- clock-names = "pclk_csi2host";
- resets = <&cru SRST_P_CSI_HOST_5>, <&cru SRST_CSIHOST5_VICAP>;
- reset-names = "srst_csihost_p", "srst_csihost_vicap";
- status = "disabled";
- };
-
- spdif_tx5: spdif-tx@fddb8000 {
- compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
- reg = <0x0 0xfddb8000 0x0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac1 22>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
- assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- power-domains = <&power RK3588_PD_VO0>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s8_8ch: i2s@fddc8000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddc8000 0x0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
- clock-names = "mclk_tx", "hclk";
- assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 22>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO0>;
- resets = <&cru SRST_M_I2S8_8CH_TX>;
- reset-names = "tx-m";
- rockchip,playback-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_tx4: spdif-tx@fdde8000 {
- compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
- reg = <0x0 0xfdde8000 0x0 0x1000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac1 8>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
- assigned-clocks = <&cru CLK_SPDIF4_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- power-domains = <&power RK3588_PD_VO1>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s6_8ch: i2s@fddf4000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddf4000 0x0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 4>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S6_8CH_TX>;
- reset-names = "tx-m";
- rockchip,always-on;
- rockchip,hdmi-path;
- rockchip,playback-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s7_8ch: i2s@fddf8000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddf8000 0x0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 21>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S7_8CH_RX>;
- reset-names = "rx-m";
- rockchip,capture-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s10_8ch: i2s@fde00000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfde00000 0x0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 24>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S10_8CH_RX>;
- reset-names = "rx-m";
- rockchip,capture-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_rx1: spdif-rx@fde10000 {
- compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
- reg = <0x0 0xfde10000 0x0 0x1000>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>;
- clock-names = "mclk", "hclk";
- assigned-clocks = <&cru MCLK_SPDIFRX1>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac0 22>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_SPDIFRX1>;
- reset-names = "spdifrx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_rx2: spdif-rx@fde18000 {
- compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
- reg = <0x0 0xfde18000 0x0 0x1000>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>;
- clock-names = "mclk", "hclk";
- assigned-clocks = <&cru MCLK_SPDIFRX2>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac0 23>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_SPDIFRX2>;
- reset-names = "spdifrx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- dp1: dp@fde60000 {
- compatible = "rockchip,rk3588-dp";
- reg = <0x0 0xfde60000 0x0 0x4000>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>,
- <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_SPDIF5_DP1>,
- <&hclk_vo0>;
- clock-names = "apb", "aux", "i2s", "spdif", "hclk";
- assigned-clocks = <&cru CLK_AUX16M_1>;
- assigned-clock-rates = <16000000>;
- resets = <&cru SRST_DP1>;
- phys = <&usbdp_phy1_dp>;
- power-domains = <&power RK3588_PD_VO0>;
- #sound-dai-cells = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dp1_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dp1_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_dp1>;
- status = "disabled";
- };
-
- dp1_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_dp1>;
- status = "disabled";
- };
-
- dp1_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_dp1>;
- status = "disabled";
- };
- };
- };
- };
-
- hdmi1: hdmi@fdea0000 {
- compatible = "rockchip,rk3588-dw-hdmi";
- reg = <0x0 0xfdea0000 0x0 0x20000>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMITX1>,
- <&cru CLK_HDMIHDP1>,
- <&cru CLK_HDMITX1_EARC>,
- <&cru CLK_HDMITX1_REF>,
- <&cru MCLK_I2S6_8CH_TX>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
- <&hclk_vo1>,
- <&hdptxphy_hdmi_clk1>;
- clock-names = "pclk",
- "hpd",
- "earc",
- "hdmitx_ref",
- "aud",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
- "hclk_vo1",
- "link_clk";
- resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
- reset-names = "ref", "hdp";
- power-domains = <&power RK3588_PD_VO1>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>;
- reg-io-width = <4>;
- rockchip,grf = <&sys_grf>;
- rockchip,vo1_grf = <&vo1_grf>;
- phys = <&hdptxphy_hdmi1>;
- phy-names = "hdmi";
- #sound-dai-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi1_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi1_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_hdmi1>;
- status = "disabled";
- };
-
- hdmi1_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_hdmi1>;
- status = "disabled";
- };
-
- hdmi1_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_hdmi1>;
- status = "disabled";
- };
- };
- };
- };
-
- edp1: edp@fded0000 {
- compatible = "rockchip,rk3588-edp";
- reg = <0x0 0xfded0000 0x0 0x1000>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>,
- <&cru CLK_EDP1_200M>, <&hclk_vo1>;
- clock-names = "dp", "pclk", "spdif", "hclk";
- resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
- reset-names = "dp", "apb";
- phys = <&hdptxphy1>;
- phy-names = "dp";
- power-domains = <&power RK3588_PD_VO1>;
- rockchip,grf = <&vo1_grf>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp1_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp1_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_edp1>;
- status = "disabled";
- };
-
- edp1_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_edp1>;
- status = "disabled";
- };
-
- edp1_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_edp1>;
- status = "disabled";
- };
- };
- };
- };
-
- hdmirx_ctrler: hdmirx-controller@fdee0000 {
- compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler";
- reg = <0x0 0xfdee0000 0x0 0x6000>;
- reg-names = "hdmirx_regs";
- power-domains = <&power RK3588_PD_VO1>;
- rockchip,grf = <&sys_grf>;
- rockchip,vo1_grf = <&vo1_grf>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cec", "hdmi", "dma";
- clocks = <&cru ACLK_HDMIRX>,
- <&cru CLK_HDMIRX_AUD>,
- <&cru CLK_CR_PARA>,
- <&cru PCLK_HDMIRX>,
- <&cru CLK_HDMIRX_REF>,
- <&cru PCLK_S_HDMIRX>,
- <&hclk_vo1>;
- clock-names = "aclk",
- "audio",
- "cr_para",
- "pclk",
- "ref",
- "hclk_s_hdmirx",
- "hclk_vo1";
- resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
- <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
- reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu";
- pinctrl-0 = <&hdmim1_rx>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- pcie3x4: pcie@fe150000 {
- compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0x0f>;
- clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
- <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
- <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
- <0 0 0 2 &pcie3x4_intc 1>,
- <0 0 0 3 &pcie3x4_intc 2>,
- <0 0 0 4 &pcie3x4_intc 3>;
- linux,pci-domain = <0>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- num-viewport = <8>;
- max-link-speed = <3>;
- msi-map = <0x0000 &its1 0x0000 0x1000>;
- num-lanes = <4>;
- phys = <&pcie30phy>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
- 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
- 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000
- 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
- reg = <0x0 0xfe150000 0x0 0x10000>,
- <0xa 0x40000000 0x0 0x400000>;
- reg-names = "pcie-apb", "pcie-dbi";
- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
- reset-names = "pcie", "periph";
- rockchip,pipe-grf = <&php_grf>;
- status = "disabled";
-
- pcie3x4_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- pcie3x2: pcie@fe160000 {
- compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x10 0x1f>;
- clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
- <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
- <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
- <0 0 0 2 &pcie3x2_intc 1>,
- <0 0 0 3 &pcie3x2_intc 2>,
- <0 0 0 4 &pcie3x2_intc 3>;
- linux,pci-domain = <1>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- num-viewport = <8>;
- max-link-speed = <3>;
- msi-map = <0x1000 &its1 0x1000 0x1000>;
- num-lanes = <2>;
- phys = <&pcie30phy>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000
- 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000
- 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000
- 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
- reg = <0x0 0xfe160000 0x0 0x10000>,
- <0xa 0x40400000 0x0 0x400000>;
- reg-names = "pcie-apb", "pcie-dbi";
- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
- reset-names = "pcie", "periph";
- rockchip,pipe-grf = <&php_grf>;
- status = "disabled";
-
- pcie3x2_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- pcie2x1l0: pcie@fe170000 {
- compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x20 0x2f>;
- clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
- <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
- <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
- <0 0 0 2 &pcie2x1l0_intc 1>,
- <0 0 0 3 &pcie2x1l0_intc 2>,
- <0 0 0 4 &pcie2x1l0_intc 3>;
- linux,pci-domain = <2>;
- num-ib-windows = <8>;
- num-ob-windows = <8>;
- num-viewport = <4>;
- max-link-speed = <2>;
- msi-map = <0x2000 &its0 0x2000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy1_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
- 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
- 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000
- 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
- reg = <0x0 0xfe170000 0x0 0x10000>,
- <0xa 0x40800000 0x0 0x400000>;
- reg-names = "pcie-apb", "pcie-dbi";
- resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
- reset-names = "pcie", "periph";
- rockchip,pipe-grf = <&php_grf>;
- status = "disabled";
-
- pcie2x1l0_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- gmac0: ethernet@fe1b0000 {
- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe1b0000 0x0 0x10000>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- rockchip,grf = <&sys_grf>;
- rockchip,php_grf = <&php_grf>;
- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
- <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
- <&cru CLK_GMAC0_PTP_REF>;
- clock-names = "stmmaceth", "clk_mac_ref",
- "pclk_mac", "aclk_mac",
- "ptp_ref";
- resets = <&cru SRST_A_GMAC0>;
- reset-names = "stmmaceth";
- power-domains = <&power RK3588_PD_GMAC>;
-
- snps,mixed-burst;
- snps,tso;
-
- snps,axi-config = <&gmac0_stmmac_axi_setup>;
- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
- status = "disabled";
-
- mdio0: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- gmac0_stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <4>;
- snps,rd_osr_lmt = <8>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
- gmac0_mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
-
- gmac0_mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
- };
-
- sata1: sata@fe220000 {
- compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
- reg = <0 0xfe220000 0 0x1000>;
- clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
- <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
- <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
- phys = <&combphy1_ps PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- status = "disabled";
- };
-
- hdptxphy1: phy@fed70000 {
- compatible = "rockchip,rk3588-hdptx-phy";
- reg = <0x0 0xfed70000 0x0 0x2000>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
- clock-names = "ref", "apb";
- resets = <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>,
- <&cru SRST_HDPTX1_CMN>, <&cru SRST_HDPTX1_LANE>;
- reset-names = "apb", "init", "cmn", "lane";
- rockchip,grf = <&hdptxphy1_grf>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- hdptxphy_hdmi1: hdmiphy@fed70000 {
- compatible = "rockchip,rk3588-hdptx-phy-hdmi";
- reg = <0x0 0xfed70000 0x0 0x2000>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
- clock-names = "ref", "apb";
- resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
- <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
- <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
- <&cru SRST_HDPTX1_LCPLL>;
- reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
- "lcpll";
- rockchip,grf = <&hdptxphy1_grf>;
- #phy-cells = <0>;
- status = "disabled";
-
- hdptxphy_hdmi_clk1: clk-port {
- #clock-cells = <0>;
- status = "okay";
- };
- };
-
-
- usbdp_phy1: phy@fed90000 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed90000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy1_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
- <&cru CLK_USBDP_PHY1_IMMORTAL>,
- <&cru PCLK_USBDPPHY1>,
- <&u2phy1>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
- <&cru SRST_USBDP_COMBO_PHY1_CMN>,
- <&cru SRST_USBDP_COMBO_PHY1_LANE>,
- <&cru SRST_USBDP_COMBO_PHY1_PCS>,
- <&cru SRST_P_USBDPPHY1>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- status = "disabled";
-
- usbdp_phy1_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy1_u3: u3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
-
- csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 {
- compatible = "rockchip,rk3588-csi2-dphy-hw";
- reg = <0x0 0xfedc8000 0x0 0x8000>;
- clocks = <&cru PCLK_CSIPHY1>;
- clock-names = "pclk";
- resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>;
- reset-names = "srst_csiphy1", "srst_p_csiphy1";
- rockchip,grf = <&mipidphy1_grf>;
- rockchip,sys_grf = <&sys_grf>;
- status = "disabled";
- };
-
- combphy1_ps: phy@fee10000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee10000 0x0 0x100>;
- #phy-cells = <1>;
- clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "refclk", "apbclk", "phpclk";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>;
- reset-names = "combphy-apb", "combphy";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
- rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
- status = "disabled";
- };
-
- pcie30phy: phy@fee80000 {
- compatible = "rockchip,rk3588-pcie3-phy";
- reg = <0x0 0xfee80000 0x0 0x20000>;
- #phy-cells = <0>;
- clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
- clock-names = "pclk";
- resets = <&cru SRST_PCIE30_PHY>;
- reset-names = "phy";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,phy-grf = <&pcie30_phy_grf>;
- status = "disabled";
- };
-
-};
-
-&display_subsystem {
- route {
- route_dp1: route-dp1 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp1_out_dp1>;
- };
-
- route_hdmi1: route-hdmi1 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp1_out_hdmi1>;
- };
- };
-};
-
-&vp0 {
- vp0_out_dp1: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&dp1_in_vp0>;
- };
-
- vp0_out_edp1: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&edp1_in_vp0>;
- };
-
- vp0_out_hdmi1: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&hdmi1_in_vp0>;
- };
-};
-
-&vp1 {
- vp1_out_dp1: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&dp1_in_vp1>;
- };
-
- vp1_out_edp1: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&edp1_in_vp1>;
- };
-
- vp1_out_hdmi1: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&hdmi1_in_vp1>;
- };
-};
-
-&vp2 {
- vp2_out_dp1: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&dp1_in_vp2>;
- };
-
- vp2_out_edp1: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&edp1_in_vp2>;
- };
-
- vp2_out_hdmi1: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&hdmi1_in_vp2>;
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi (nonexistent)
@@ -1,347 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include <dt-bindings/display/rockchip_vop.h>
-
-/ {
-
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <
- 0 20 20 21 21 22 22 23
- 23 24 24 25 25 26 26 27
- 27 28 28 29 29 30 30 31
- 31 32 32 33 33 34 34 35
- 35 36 36 37 37 38 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255
- >;
- default-brightness-level = <200>;
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usbdcin: vcc5v0-usbdcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usbdcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- mem-supply = <&vdd_cpu_big0_mem_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
- mem-supply = <&vdd_cpu_big1_mem_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
- mem-supply = <&vdd_cpu_lit_mem_s0>;
-};
-
-&dfi {
- status = "okay";
-};
-
-&dmc {
- center-supply = <&vdd_ddr_s0>;
- mem-supply = <&vdd_log_s0>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu_s0>;
- mem-supply = <&vdd_gpu_mem_s0>;
- status = "okay";
-};
-
-&gpu_opp_table {
- /delete-node/ opp-198000000;
- /delete-node/ opp-297000000;
- /delete-node/ opp-396000000;
- /delete-node/ opp-594000000;
-};
-
-&iep {
- status = "okay";
-};
-
-&iep_mmu {
- status = "okay";
-};
-
-&jpegd {
- status = "okay";
-};
-
-&jpegd_mmu {
- status = "okay";
-};
-
-&jpege_ccu {
- status = "okay";
-};
-
-&jpege0 {
- status = "okay";
-};
-
-&jpege0_mmu {
- status = "okay";
-};
-
-&jpege1 {
- status = "okay";
-};
-
-&jpege1_mmu {
- status = "okay";
-};
-
-&jpege2 {
- status = "okay";
-};
-
-&jpege2_mmu {
- status = "okay";
-};
-
-&jpege3 {
- status = "okay";
-};
-
-&jpege3_mmu {
- status = "okay";
-};
-
-&mpp_srv {
- status = "okay";
-};
-
-&rga2 {
- status = "okay";
-};
-
-&rga3_core0 {
- status = "okay";
-};
-
-&rga3_0_mmu {
- status = "okay";
-};
-
-&rga3_core1 {
- status = "okay";
-};
-
-&rga3_1_mmu {
- status = "okay";
-};
-
-&rknpu {
- rknpu-supply = <&vdd_npu_s0>;
- mem-supply = <&vdd_npu_mem_s0>;
- status = "okay";
-};
-
-&rknpu_mmu {
- status = "okay";
-};
-
-&rkvdec_ccu {
- status = "okay";
-};
-
-&rkvdec0 {
- status = "okay";
-};
-
-&rkvdec0_mmu {
- status = "okay";
-};
-
-&rkvdec1 {
- status = "okay";
-};
-
-&rkvdec1_mmu {
- status = "okay";
-};
-
-&rkvenc_ccu {
- status = "okay";
-};
-
-&rkvenc0 {
- status = "okay";
-};
-
-&rkvenc0_mmu {
- status = "okay";
-};
-
-&rkvenc1 {
- status = "okay";
-};
-
-&rkvenc1_mmu {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vcc_1v8_s0>;
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy1 {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdp_phy0 {
- status = "okay";
-};
-
-&usbdp_phy0_dp {
- status = "okay";
-};
-
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
-&usbdp_phy1_dp {
- status = "okay";
-};
-
-&usbdp_phy1_u3 {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&usbhost3_0 {
- status = "okay";
-};
-
-&usbhost_dwc3_0 {
- status = "okay";
-};
-
-&vdpu {
- status = "okay";
-};
-
-&vdpu_mmu {
- status = "okay";
-};
-
-&vepu {
- status = "okay";
-};
-
-&vop {
- disable-win-move;
- assigned-clocks = <&cru DCLK_VOP0_SRC>,
- <&cru DCLK_VOP1_SRC>,
- <&cru DCLK_VOP2_SRC>,
- <&cru DCLK_VOP3>;
- assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi (nonexistent)
@@ -1,3417 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- auddsm {
- /omit-if-no-ref/
- auddsm_pins: auddsm-pins {
- rockchip,pins =
- /* auddsm_ln */
- <3 RK_PA1 4 &pcfg_pull_none>,
- /* auddsm_lp */
- <3 RK_PA2 4 &pcfg_pull_none>,
- /* auddsm_rn */
- <3 RK_PA3 4 &pcfg_pull_none>,
- /* auddsm_rp */
- <3 RK_PA4 4 &pcfg_pull_none>;
- };
- };
-
- bt1120 {
- /omit-if-no-ref/
- bt1120_pins: bt1120-pins {
- rockchip,pins =
- /* bt1120_clkout */
- <4 RK_PB0 2 &pcfg_pull_none>,
- /* bt1120_d0 */
- <4 RK_PA0 2 &pcfg_pull_none>,
- /* bt1120_d1 */
- <4 RK_PA1 2 &pcfg_pull_none>,
- /* bt1120_d2 */
- <4 RK_PA2 2 &pcfg_pull_none>,
- /* bt1120_d3 */
- <4 RK_PA3 2 &pcfg_pull_none>,
- /* bt1120_d4 */
- <4 RK_PA4 2 &pcfg_pull_none>,
- /* bt1120_d5 */
- <4 RK_PA5 2 &pcfg_pull_none>,
- /* bt1120_d6 */
- <4 RK_PA6 2 &pcfg_pull_none>,
- /* bt1120_d7 */
- <4 RK_PA7 2 &pcfg_pull_none>,
- /* bt1120_d8 */
- <4 RK_PB2 2 &pcfg_pull_none>,
- /* bt1120_d9 */
- <4 RK_PB3 2 &pcfg_pull_none>,
- /* bt1120_d10 */
- <4 RK_PB4 2 &pcfg_pull_none>,
- /* bt1120_d11 */
- <4 RK_PB5 2 &pcfg_pull_none>,
- /* bt1120_d12 */
- <4 RK_PB6 2 &pcfg_pull_none>,
- /* bt1120_d13 */
- <4 RK_PB7 2 &pcfg_pull_none>,
- /* bt1120_d14 */
- <4 RK_PC0 2 &pcfg_pull_none>,
- /* bt1120_d15 */
- <4 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- can0 {
- /omit-if-no-ref/
- can0m0_pins: can0m0-pins {
- rockchip,pins =
- /* can0_rx_m0 */
- <0 RK_PC0 11 &pcfg_pull_none>,
- /* can0_tx_m0 */
- <0 RK_PB7 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can0m1_pins: can0m1-pins {
- rockchip,pins =
- /* can0_rx_m1 */
- <4 RK_PD5 9 &pcfg_pull_none>,
- /* can0_tx_m1 */
- <4 RK_PD4 9 &pcfg_pull_none>;
- };
- };
-
- can1 {
- /omit-if-no-ref/
- can1m0_pins: can1m0-pins {
- rockchip,pins =
- /* can1_rx_m0 */
- <3 RK_PB5 9 &pcfg_pull_none>,
- /* can1_tx_m0 */
- <3 RK_PB6 9 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can1m1_pins: can1m1-pins {
- rockchip,pins =
- /* can1_rx_m1 */
- <4 RK_PB2 12 &pcfg_pull_none>,
- /* can1_tx_m1 */
- <4 RK_PB3 12 &pcfg_pull_none>;
- };
- };
-
- can2 {
- /omit-if-no-ref/
- can2m0_pins: can2m0-pins {
- rockchip,pins =
- /* can2_rx_m0 */
- <3 RK_PC4 9 &pcfg_pull_none>,
- /* can2_tx_m0 */
- <3 RK_PC5 9 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can2m1_pins: can2m1-pins {
- rockchip,pins =
- /* can2_rx_m1 */
- <0 RK_PD4 10 &pcfg_pull_none>,
- /* can2_tx_m1 */
- <0 RK_PD5 10 &pcfg_pull_none>;
- };
- };
-
- cif {
- /omit-if-no-ref/
- cif_clk: cif-clk {
- rockchip,pins =
- /* cif_clkout */
- <4 RK_PB4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_clk: cif-dvp-clk {
- rockchip,pins =
- /* cif_clkin */
- <4 RK_PB0 1 &pcfg_pull_none>,
- /* cif_href */
- <4 RK_PB2 1 &pcfg_pull_none>,
- /* cif_vsync */
- <4 RK_PB3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_bus16: cif-dvp-bus16 {
- rockchip,pins =
- /* cif_d8 */
- <3 RK_PC4 1 &pcfg_pull_none>,
- /* cif_d9 */
- <3 RK_PC5 1 &pcfg_pull_none>,
- /* cif_d10 */
- <3 RK_PC6 1 &pcfg_pull_none>,
- /* cif_d11 */
- <3 RK_PC7 1 &pcfg_pull_none>,
- /* cif_d12 */
- <3 RK_PD0 1 &pcfg_pull_none>,
- /* cif_d13 */
- <3 RK_PD1 1 &pcfg_pull_none>,
- /* cif_d14 */
- <3 RK_PD2 1 &pcfg_pull_none>,
- /* cif_d15 */
- <3 RK_PD3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_bus8: cif-dvp-bus8 {
- rockchip,pins =
- /* cif_d0 */
- <4 RK_PA0 1 &pcfg_pull_none>,
- /* cif_d1 */
- <4 RK_PA1 1 &pcfg_pull_none>,
- /* cif_d2 */
- <4 RK_PA2 1 &pcfg_pull_none>,
- /* cif_d3 */
- <4 RK_PA3 1 &pcfg_pull_none>,
- /* cif_d4 */
- <4 RK_PA4 1 &pcfg_pull_none>,
- /* cif_d5 */
- <4 RK_PA5 1 &pcfg_pull_none>,
- /* cif_d6 */
- <4 RK_PA6 1 &pcfg_pull_none>,
- /* cif_d7 */
- <4 RK_PA7 1 &pcfg_pull_none>;
- };
- };
-
- clk32k {
- /omit-if-no-ref/
- clk32k_in: clk32k-in {
- rockchip,pins =
- /* clk32k_in */
- <0 RK_PB2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- clk32k_out0: clk32k-out0 {
- rockchip,pins =
- /* clk32k_out0 */
- <0 RK_PB2 2 &pcfg_pull_none>;
- };
- };
-
- cpu {
- /omit-if-no-ref/
- cpu_pins: cpu-pins {
- rockchip,pins =
- /* cpu_big0_avs */
- <0 RK_PD1 2 &pcfg_pull_none>,
- /* cpu_big1_avs */
- <0 RK_PD5 2 &pcfg_pull_none>;
- };
- };
-
- ddrphych0 {
- /omit-if-no-ref/
- ddrphych0_pins: ddrphych0-pins {
- rockchip,pins =
- /* ddrphych0_dtb0 */
- <4 RK_PA0 7 &pcfg_pull_none>,
- /* ddrphych0_dtb1 */
- <4 RK_PA1 7 &pcfg_pull_none>,
- /* ddrphych0_dtb2 */
- <4 RK_PA2 7 &pcfg_pull_none>,
- /* ddrphych0_dtb3 */
- <4 RK_PA3 7 &pcfg_pull_none>;
- };
- };
-
- ddrphych1 {
- /omit-if-no-ref/
- ddrphych1_pins: ddrphych1-pins {
- rockchip,pins =
- /* ddrphych1_dtb0 */
- <4 RK_PA4 7 &pcfg_pull_none>,
- /* ddrphych1_dtb1 */
- <4 RK_PA5 7 &pcfg_pull_none>,
- /* ddrphych1_dtb2 */
- <4 RK_PA6 7 &pcfg_pull_none>,
- /* ddrphych1_dtb3 */
- <4 RK_PA7 7 &pcfg_pull_none>;
- };
- };
-
- ddrphych2 {
- /omit-if-no-ref/
- ddrphych2_pins: ddrphych2-pins {
- rockchip,pins =
- /* ddrphych2_dtb0 */
- <4 RK_PB0 7 &pcfg_pull_none>,
- /* ddrphych2_dtb1 */
- <4 RK_PB1 7 &pcfg_pull_none>,
- /* ddrphych2_dtb2 */
- <4 RK_PB2 7 &pcfg_pull_none>,
- /* ddrphych2_dtb3 */
- <4 RK_PB3 7 &pcfg_pull_none>;
- };
- };
-
- ddrphych3 {
- /omit-if-no-ref/
- ddrphych3_pins: ddrphych3-pins {
- rockchip,pins =
- /* ddrphych3_dtb0 */
- <4 RK_PB4 7 &pcfg_pull_none>,
- /* ddrphych3_dtb1 */
- <4 RK_PB5 7 &pcfg_pull_none>,
- /* ddrphych3_dtb2 */
- <4 RK_PB6 7 &pcfg_pull_none>,
- /* ddrphych3_dtb3 */
- <4 RK_PB7 7 &pcfg_pull_none>;
- };
- };
-
- dp0 {
- /omit-if-no-ref/
- dp0m0_pins: dp0m0-pins {
- rockchip,pins =
- /* dp0_hpdin_m0 */
- <4 RK_PB4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp0m1_pins: dp0m1-pins {
- rockchip,pins =
- /* dp0_hpdin_m1 */
- <0 RK_PC4 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp0m2_pins: dp0m2-pins {
- rockchip,pins =
- /* dp0_hpdin_m2 */
- <1 RK_PA0 5 &pcfg_pull_none>;
- };
- };
-
- dp1 {
- /omit-if-no-ref/
- dp1m0_pins: dp1m0-pins {
- rockchip,pins =
- /* dp1_hpdin_m0 */
- <3 RK_PD5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp1m1_pins: dp1m1-pins {
- rockchip,pins =
- /* dp1_hpdin_m1 */
- <0 RK_PC5 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp1m2_pins: dp1m2-pins {
- rockchip,pins =
- /* dp1_hpdin_m2 */
- <1 RK_PA1 5 &pcfg_pull_none>;
- };
- };
-
- emmc {
- /omit-if-no-ref/
- emmc_rstnout: emmc-rstnout {
- rockchip,pins =
- /* emmc_rstn */
- <2 RK_PA3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- /* emmc_d0 */
- <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d1 */
- <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d2 */
- <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d3 */
- <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d4 */
- <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d5 */
- <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d6 */
- <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d7 */
- <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_clk: emmc-clk {
- rockchip,pins =
- /* emmc_clkout */
- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_cmd: emmc-cmd {
- rockchip,pins =
- /* emmc_cmd */
- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_data_strobe: emmc-data-strobe {
- rockchip,pins =
- /* emmc_data_strobe */
- <2 RK_PA2 1 &pcfg_pull_none>;
- };
- };
-
- eth1 {
- /omit-if-no-ref/
- eth1_pins: eth1-pins {
- rockchip,pins =
- /* eth1_refclko_25m */
- <3 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-
- fspi {
- /omit-if-no-ref/
- fspim0_pins: fspim0-pins {
- rockchip,pins =
- /* fspi_clk_m0 */
- <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_cs0n_m0 */
- <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d0_m0 */
- <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d1_m0 */
- <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d2_m0 */
- <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d3_m0 */
- <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim0_cs1: fspim0-cs1 {
- rockchip,pins =
- /* fspi_cs1n_m0 */
- <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim2_pins: fspim2-pins {
- rockchip,pins =
- /* fspi_clk_m2 */
- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_cs0n_m2 */
- <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d0_m2 */
- <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_d1_m2 */
- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_d2_m2 */
- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_d3_m2 */
- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim2_cs1: fspim2-cs1 {
- rockchip,pins =
- /* fspi_cs1n_m2 */
- <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
- };
- };
-
- gmac1 {
- /omit-if-no-ref/
- gmac1_miim: gmac1-miim {
- rockchip,pins =
- /* gmac1_mdc */
- <3 RK_PC2 1 &pcfg_pull_none>,
- /* gmac1_mdio */
- <3 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_clkinout: gmac1-clkinout {
- rockchip,pins =
- /* gmac1_mclkinout */
- <3 RK_PB6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_rx_bus2: gmac1-rx-bus2 {
- rockchip,pins =
- /* gmac1_rxd0 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* gmac1_rxd1 */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* gmac1_rxdv_crs */
- <3 RK_PB1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_tx_bus2: gmac1-tx-bus2 {
- rockchip,pins =
- /* gmac1_txd0 */
- <3 RK_PB3 1 &pcfg_pull_none>,
- /* gmac1_txd1 */
- <3 RK_PB4 1 &pcfg_pull_none>,
- /* gmac1_txen */
- <3 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_rgmii_clk: gmac1-rgmii-clk {
- rockchip,pins =
- /* gmac1_rxclk */
- <3 RK_PA5 1 &pcfg_pull_none>,
- /* gmac1_txclk */
- <3 RK_PA4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_rgmii_bus: gmac1-rgmii-bus {
- rockchip,pins =
- /* gmac1_rxd2 */
- <3 RK_PA2 1 &pcfg_pull_none>,
- /* gmac1_rxd3 */
- <3 RK_PA3 1 &pcfg_pull_none>,
- /* gmac1_txd2 */
- <3 RK_PA0 1 &pcfg_pull_none>,
- /* gmac1_txd3 */
- <3 RK_PA1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_ppsclk: gmac1-ppsclk {
- rockchip,pins =
- /* gmac1_ppsclk */
- <3 RK_PC1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_ppstrig: gmac1-ppstrig {
- rockchip,pins =
- /* gmac1_ppstrig */
- <3 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
- rockchip,pins =
- /* gmac1_ptp_ref_clk */
- <3 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_txer: gmac1-txer {
- rockchip,pins =
- /* gmac1_txer */
- <3 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- gpu {
- /omit-if-no-ref/
- gpu_pins: gpu-pins {
- rockchip,pins =
- /* gpu_avs */
- <0 RK_PC5 2 &pcfg_pull_none>;
- };
- };
-
- hdmi {
- /omit-if-no-ref/
- hdmim0_rx_cec: hdmim0-rx-cec {
- rockchip,pins =
- /* hdmim0_rx_cec */
- <4 RK_PB5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_rx_hpdin: hdmim0-rx-hpdin {
- rockchip,pins =
- /* hdmim0_rx_hpdin */
- <4 RK_PB6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_rx_scl: hdmim0-rx-scl {
- rockchip,pins =
- /* hdmim0_rx_scl */
- <0 RK_PD2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_rx_sda: hdmim0-rx-sda {
- rockchip,pins =
- /* hdmim0_rx_sda */
- <0 RK_PD1 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_cec: hdmim0-tx0-cec {
- rockchip,pins =
- /* hdmim0_tx0_cec */
- <4 RK_PC1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_hpd: hdmim0-tx0-hpd {
- rockchip,pins =
- /* hdmim0_tx0_hpd */
- <1 RK_PA5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_scl: hdmim0-tx0-scl {
- rockchip,pins =
- /* hdmim0_tx0_scl */
- <4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_sda: hdmim0-tx0-sda {
- rockchip,pins =
- /* hdmim0_tx0_sda */
- <4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx1_hpd: hdmim0-tx1-hpd {
- rockchip,pins =
- /* hdmim0_tx1_hpd */
- <1 RK_PA6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx: hdmim1-rx {
- rockchip,pins =
- /* hdmim1_rx_cec */
- <3 RK_PD1 5 &pcfg_pull_none>,
- /* hdmim1_rx_scl */
- <3 RK_PD2 5 &pcfg_pull_none_smt>,
- /* hdmim1_rx_sda */
- <3 RK_PD3 5 &pcfg_pull_none_smt>,
- /* hdmim1_rx_hpdin */
- <3 RK_PD4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_cec: hdmim1-rx-cec {
- rockchip,pins =
- /* hdmim1_rx_cec */
- <3 RK_PD1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_hpdin: hdmim1-rx-hpdin {
- rockchip,pins =
- /* hdmim1_rx_hpdin */
- <3 RK_PD4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_scl: hdmim1-rx-scl {
- rockchip,pins =
- /* hdmim1_rx_scl */
- <3 RK_PD2 5 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_sda: hdmim1-rx-sda {
- rockchip,pins =
- /* hdmim1_rx_sda */
- <3 RK_PD3 5 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_cec: hdmim1-tx0-cec {
- rockchip,pins =
- /* hdmim1_tx0_cec */
- <0 RK_PD1 13 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_hpd: hdmim1-tx0-hpd {
- rockchip,pins =
- /* hdmim1_tx0_hpd */
- <3 RK_PD4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_scl: hdmim1-tx0-scl {
- rockchip,pins =
- /* hdmim1_tx0_scl */
- <0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_sda: hdmim1-tx0-sda {
- rockchip,pins =
- /* hdmim1_tx0_sda */
- <0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_cec: hdmim1-tx1-cec {
- rockchip,pins =
- /* hdmim1_tx1_cec */
- <0 RK_PD2 13 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_hpd: hdmim1-tx1-hpd {
- rockchip,pins =
- /* hdmim1_tx1_hpd */
- <3 RK_PB7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_scl: hdmim1-tx1-scl {
- rockchip,pins =
- /* hdmim1_tx1_scl */
- <3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_sda: hdmim1-tx1-sda {
- rockchip,pins =
- /* hdmim1_tx1_sda */
- <3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
- };
- /omit-if-no-ref/
- hdmim2_rx_cec: hdmim2-rx-cec {
- rockchip,pins =
- /* hdmim2_rx_cec */
- <1 RK_PB7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_rx_hpdin: hdmim2-rx-hpdin {
- rockchip,pins =
- /* hdmim2_rx_hpdin */
- <1 RK_PB6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_rx_scl: hdmim2-rx-scl {
- rockchip,pins =
- /* hdmim2_rx_scl */
- <1 RK_PD6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_rx_sda: hdmim2-rx-sda {
- rockchip,pins =
- /* hdmim2_rx_sda */
- <1 RK_PD7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx0_scl: hdmim2-tx0-scl {
- rockchip,pins =
- /* hdmim2_tx0_scl */
- <3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx0_sda: hdmim2-tx0-sda {
- rockchip,pins =
- /* hdmim2_tx0_sda */
- <3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx1_cec: hdmim2-tx1-cec {
- rockchip,pins =
- /* hdmim2_tx1_cec */
- <3 RK_PC4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx1_scl: hdmim2-tx1-scl {
- rockchip,pins =
- /* hdmim2_tx1_scl */
- <1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx1_sda: hdmim2-tx1-sda {
- rockchip,pins =
- /* hdmim2_tx1_sda */
- <1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
- };
-
- /omit-if-no-ref/
- hdmi_debug0: hdmi-debug0 {
- rockchip,pins =
- /* hdmi_debug0 */
- <1 RK_PA7 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug1: hdmi-debug1 {
- rockchip,pins =
- /* hdmi_debug1 */
- <1 RK_PB0 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug2: hdmi-debug2 {
- rockchip,pins =
- /* hdmi_debug2 */
- <1 RK_PB1 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug3: hdmi-debug3 {
- rockchip,pins =
- /* hdmi_debug3 */
- <1 RK_PB2 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug4: hdmi-debug4 {
- rockchip,pins =
- /* hdmi_debug4 */
- <1 RK_PB3 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug5: hdmi-debug5 {
- rockchip,pins =
- /* hdmi_debug5 */
- <1 RK_PB4 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug6: hdmi-debug6 {
- rockchip,pins =
- /* hdmi_debug6 */
- <1 RK_PA0 7 &pcfg_pull_none>;
- };
- };
-
- i2c0 {
- /omit-if-no-ref/
- i2c0m0_xfer: i2c0m0-xfer {
- rockchip,pins =
- /* i2c0_scl_m0 */
- <0 RK_PB3 2 &pcfg_pull_none_smt>,
- /* i2c0_sda_m0 */
- <0 RK_PA6 2 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c0m2_xfer: i2c0m2-xfer {
- rockchip,pins =
- /* i2c0_scl_m2 */
- <0 RK_PD1 3 &pcfg_pull_none_smt>,
- /* i2c0_sda_m2 */
- <0 RK_PD2 3 &pcfg_pull_none_smt>;
- };
- };
-
- i2c1 {
- /omit-if-no-ref/
- i2c1m0_xfer: i2c1m0-xfer {
- rockchip,pins =
- /* i2c1_scl_m0 */
- <0 RK_PB5 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m0 */
- <0 RK_PB6 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m1_xfer: i2c1m1-xfer {
- rockchip,pins =
- /* i2c1_scl_m1 */
- <0 RK_PB0 2 &pcfg_pull_none_smt>,
- /* i2c1_sda_m1 */
- <0 RK_PB1 2 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m2_xfer: i2c1m2-xfer {
- rockchip,pins =
- /* i2c1_scl_m2 */
- <0 RK_PD4 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m2 */
- <0 RK_PD5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m3_xfer: i2c1m3-xfer {
- rockchip,pins =
- /* i2c1_scl_m3 */
- <2 RK_PD4 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m3 */
- <2 RK_PD5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m4_xfer: i2c1m4-xfer {
- rockchip,pins =
- /* i2c1_scl_m4 */
- <1 RK_PD2 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m4 */
- <1 RK_PD3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c2 {
- /omit-if-no-ref/
- i2c2m0_xfer: i2c2m0-xfer {
- rockchip,pins =
- /* i2c2_scl_m0 */
- <0 RK_PB7 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m0 */
- <0 RK_PC0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m2_xfer: i2c2m2-xfer {
- rockchip,pins =
- /* i2c2_scl_m2 */
- <2 RK_PA3 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m2 */
- <2 RK_PA2 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m3_xfer: i2c2m3-xfer {
- rockchip,pins =
- /* i2c2_scl_m3 */
- <1 RK_PC5 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m3 */
- <1 RK_PC4 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m4_xfer: i2c2m4-xfer {
- rockchip,pins =
- /* i2c2_scl_m4 */
- <1 RK_PA1 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m4 */
- <1 RK_PA0 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3 {
- /omit-if-no-ref/
- i2c3m0_xfer: i2c3m0-xfer {
- rockchip,pins =
- /* i2c3_scl_m0 */
- <1 RK_PC1 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m0 */
- <1 RK_PC0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m1_xfer: i2c3m1-xfer {
- rockchip,pins =
- /* i2c3_scl_m1 */
- <3 RK_PB7 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m1 */
- <3 RK_PC0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m2_xfer: i2c3m2-xfer {
- rockchip,pins =
- /* i2c3_scl_m2 */
- <4 RK_PA4 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m2 */
- <4 RK_PA5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m4_xfer: i2c3m4-xfer {
- rockchip,pins =
- /* i2c3_scl_m4 */
- <4 RK_PD0 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m4 */
- <4 RK_PD1 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c4 {
- /omit-if-no-ref/
- i2c4m0_xfer: i2c4m0-xfer {
- rockchip,pins =
- /* i2c4_scl_m0 */
- <3 RK_PA6 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m0 */
- <3 RK_PA5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m2_xfer: i2c4m2-xfer {
- rockchip,pins =
- /* i2c4_scl_m2 */
- <0 RK_PC5 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m2 */
- <0 RK_PC4 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m3_xfer: i2c4m3-xfer {
- rockchip,pins =
- /* i2c4_scl_m3 */
- <1 RK_PA3 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m3 */
- <1 RK_PA2 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m4_xfer: i2c4m4-xfer {
- rockchip,pins =
- /* i2c4_scl_m4 */
- <1 RK_PC7 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m4 */
- <1 RK_PC6 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c5 {
- /omit-if-no-ref/
- i2c5m0_xfer: i2c5m0-xfer {
- rockchip,pins =
- /* i2c5_scl_m0 */
- <3 RK_PC7 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m0 */
- <3 RK_PD0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m1_xfer: i2c5m1-xfer {
- rockchip,pins =
- /* i2c5_scl_m1 */
- <4 RK_PB6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m1 */
- <4 RK_PB7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m2_xfer: i2c5m2-xfer {
- rockchip,pins =
- /* i2c5_scl_m2 */
- <4 RK_PA6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m2 */
- <4 RK_PA7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m3_xfer: i2c5m3-xfer {
- rockchip,pins =
- /* i2c5_scl_m3 */
- <1 RK_PB6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m3 */
- <1 RK_PB7 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c6 {
- /omit-if-no-ref/
- i2c6m0_xfer: i2c6m0-xfer {
- rockchip,pins =
- /* i2c6_scl_m0 */
- <0 RK_PD0 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m0 */
- <0 RK_PC7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c6m1_xfer: i2c6m1-xfer {
- rockchip,pins =
- /* i2c6_scl_m1 */
- <1 RK_PC3 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m1 */
- <1 RK_PC2 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c6m3_xfer: i2c6m3-xfer {
- rockchip,pins =
- /* i2c6_scl_m3 */
- <4 RK_PB1 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m3 */
- <4 RK_PB0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c6m4_xfer: i2c6m4-xfer {
- rockchip,pins =
- /* i2c6_scl_m4 */
- <3 RK_PA1 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m4 */
- <3 RK_PA0 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c7 {
- /omit-if-no-ref/
- i2c7m0_xfer: i2c7m0-xfer {
- rockchip,pins =
- /* i2c7_scl_m0 */
- <1 RK_PD0 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m0 */
- <1 RK_PD1 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c7m2_xfer: i2c7m2-xfer {
- rockchip,pins =
- /* i2c7_scl_m2 */
- <3 RK_PD2 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m2 */
- <3 RK_PD3 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c7m3_xfer: i2c7m3-xfer {
- rockchip,pins =
- /* i2c7_scl_m3 */
- <4 RK_PB2 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m3 */
- <4 RK_PB3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c8 {
- /omit-if-no-ref/
- i2c8m0_xfer: i2c8m0-xfer {
- rockchip,pins =
- /* i2c8_scl_m0 */
- <4 RK_PD2 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m0 */
- <4 RK_PD3 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c8m2_xfer: i2c8m2-xfer {
- rockchip,pins =
- /* i2c8_scl_m2 */
- <1 RK_PD6 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m2 */
- <1 RK_PD7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c8m3_xfer: i2c8m3-xfer {
- rockchip,pins =
- /* i2c8_scl_m3 */
- <4 RK_PC0 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m3 */
- <4 RK_PC1 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c8m4_xfer: i2c8m4-xfer {
- rockchip,pins =
- /* i2c8_scl_m4 */
- <3 RK_PC2 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m4 */
- <3 RK_PC3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2s0 {
- /omit-if-no-ref/
- i2s0_lrck: i2s0-lrck {
- rockchip,pins =
- /* i2s0_lrck */
- <1 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_mclk: i2s0-mclk {
- rockchip,pins =
- /* i2s0_mclk */
- <1 RK_PC2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sclk: i2s0-sclk {
- rockchip,pins =
- /* i2s0_sclk */
- <1 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi0: i2s0-sdi0 {
- rockchip,pins =
- /* i2s0_sdi0 */
- <1 RK_PD4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi1: i2s0-sdi1 {
- rockchip,pins =
- /* i2s0_sdi1 */
- <1 RK_PD3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi2: i2s0-sdi2 {
- rockchip,pins =
- /* i2s0_sdi2 */
- <1 RK_PD2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi3: i2s0-sdi3 {
- rockchip,pins =
- /* i2s0_sdi3 */
- <1 RK_PD1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo0: i2s0-sdo0 {
- rockchip,pins =
- /* i2s0_sdo0 */
- <1 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo1: i2s0-sdo1 {
- rockchip,pins =
- /* i2s0_sdo1 */
- <1 RK_PD0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo2: i2s0-sdo2 {
- rockchip,pins =
- /* i2s0_sdo2 */
- <1 RK_PD1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo3: i2s0-sdo3 {
- rockchip,pins =
- /* i2s0_sdo3 */
- <1 RK_PD2 1 &pcfg_pull_none>;
- };
- };
-
- i2s1 {
- /omit-if-no-ref/
- i2s1m0_lrck: i2s1m0-lrck {
- rockchip,pins =
- /* i2s1m0_lrck */
- <4 RK_PA2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_mclk: i2s1m0-mclk {
- rockchip,pins =
- /* i2s1m0_mclk */
- <4 RK_PA0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sclk: i2s1m0-sclk {
- rockchip,pins =
- /* i2s1m0_sclk */
- <4 RK_PA1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi0: i2s1m0-sdi0 {
- rockchip,pins =
- /* i2s1m0_sdi0 */
- <4 RK_PA5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi1: i2s1m0-sdi1 {
- rockchip,pins =
- /* i2s1m0_sdi1 */
- <4 RK_PA6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi2: i2s1m0-sdi2 {
- rockchip,pins =
- /* i2s1m0_sdi2 */
- <4 RK_PA7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi3: i2s1m0-sdi3 {
- rockchip,pins =
- /* i2s1m0_sdi3 */
- <4 RK_PB0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo0: i2s1m0-sdo0 {
- rockchip,pins =
- /* i2s1m0_sdo0 */
- <4 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo1: i2s1m0-sdo1 {
- rockchip,pins =
- /* i2s1m0_sdo1 */
- <4 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo2: i2s1m0-sdo2 {
- rockchip,pins =
- /* i2s1m0_sdo2 */
- <4 RK_PB3 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo3: i2s1m0-sdo3 {
- rockchip,pins =
- /* i2s1m0_sdo3 */
- <4 RK_PB4 3 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- i2s1m1_lrck: i2s1m1-lrck {
- rockchip,pins =
- /* i2s1m1_lrck */
- <0 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_mclk: i2s1m1-mclk {
- rockchip,pins =
- /* i2s1m1_mclk */
- <0 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sclk: i2s1m1-sclk {
- rockchip,pins =
- /* i2s1m1_sclk */
- <0 RK_PB6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi0: i2s1m1-sdi0 {
- rockchip,pins =
- /* i2s1m1_sdi0 */
- <0 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi1: i2s1m1-sdi1 {
- rockchip,pins =
- /* i2s1m1_sdi1 */
- <0 RK_PC6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi2: i2s1m1-sdi2 {
- rockchip,pins =
- /* i2s1m1_sdi2 */
- <0 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi3: i2s1m1-sdi3 {
- rockchip,pins =
- /* i2s1m1_sdi3 */
- <0 RK_PD0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo0: i2s1m1-sdo0 {
- rockchip,pins =
- /* i2s1m1_sdo0 */
- <0 RK_PD1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo1: i2s1m1-sdo1 {
- rockchip,pins =
- /* i2s1m1_sdo1 */
- <0 RK_PD2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo2: i2s1m1-sdo2 {
- rockchip,pins =
- /* i2s1m1_sdo2 */
- <0 RK_PD4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo3: i2s1m1-sdo3 {
- rockchip,pins =
- /* i2s1m1_sdo3 */
- <0 RK_PD5 1 &pcfg_pull_none>;
- };
- };
-
- i2s2 {
- /omit-if-no-ref/
- i2s2m1_lrck: i2s2m1-lrck {
- rockchip,pins =
- /* i2s2m1_lrck */
- <3 RK_PB6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_mclk: i2s2m1-mclk {
- rockchip,pins =
- /* i2s2m1_mclk */
- <3 RK_PB4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sclk: i2s2m1-sclk {
- rockchip,pins =
- /* i2s2m1_sclk */
- <3 RK_PB5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sdi: i2s2m1-sdi {
- rockchip,pins =
- /* i2s2m1_sdi */
- <3 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sdo: i2s2m1-sdo {
- rockchip,pins =
- /* i2s2m1_sdo */
- <3 RK_PB3 3 &pcfg_pull_none>;
- };
- };
-
- i2s3 {
- /omit-if-no-ref/
- i2s3_lrck: i2s3-lrck {
- rockchip,pins =
- /* i2s3_lrck */
- <3 RK_PA2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_mclk: i2s3-mclk {
- rockchip,pins =
- /* i2s3_mclk */
- <3 RK_PA0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_sclk: i2s3-sclk {
- rockchip,pins =
- /* i2s3_sclk */
- <3 RK_PA1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_sdi: i2s3-sdi {
- rockchip,pins =
- /* i2s3_sdi */
- <3 RK_PA4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_sdo: i2s3-sdo {
- rockchip,pins =
- /* i2s3_sdo */
- <3 RK_PA3 3 &pcfg_pull_none>;
- };
- };
-
- jtag {
- /omit-if-no-ref/
- jtagm0_pins: jtagm0-pins {
- rockchip,pins =
- /* jtag_tck_m0 */
- <4 RK_PD2 5 &pcfg_pull_none>,
- /* jtag_tms_m0 */
- <4 RK_PD3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- jtagm1_pins: jtagm1-pins {
- rockchip,pins =
- /* jtag_tck_m1 */
- <4 RK_PD0 5 &pcfg_pull_none>,
- /* jtag_tms_m1 */
- <4 RK_PD1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- jtagm2_pins: jtagm2-pins {
- rockchip,pins =
- /* jtag_tck_m2 */
- <0 RK_PB5 2 &pcfg_pull_none>,
- /* jtag_tms_m2 */
- <0 RK_PB6 2 &pcfg_pull_none>;
- };
- };
-
- litcpu {
- /omit-if-no-ref/
- litcpu_pins: litcpu-pins {
- rockchip,pins =
- /* litcpu_avs */
- <0 RK_PD3 1 &pcfg_pull_none>;
- };
- };
-
- mcu {
- /omit-if-no-ref/
- mcum0_pins: mcum0-pins {
- rockchip,pins =
- /* mcu_jtag_tck_m0 */
- <4 RK_PD4 5 &pcfg_pull_none>,
- /* mcu_jtag_tms_m0 */
- <4 RK_PD5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mcum1_pins: mcum1-pins {
- rockchip,pins =
- /* mcu_jtag_tck_m1 */
- <3 RK_PD4 6 &pcfg_pull_none>,
- /* mcu_jtag_tms_m1 */
- <3 RK_PD5 6 &pcfg_pull_none>;
- };
- };
-
- mipi {
- /omit-if-no-ref/
- mipim0_camera0_clk: mipim0-camera0-clk {
- rockchip,pins =
- /* mipim0_camera0_clk */
- <4 RK_PB1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera1_clk: mipim0-camera1-clk {
- rockchip,pins =
- /* mipim0_camera1_clk */
- <1 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera2_clk: mipim0-camera2-clk {
- rockchip,pins =
- /* mipim0_camera2_clk */
- <1 RK_PB7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera3_clk: mipim0-camera3-clk {
- rockchip,pins =
- /* mipim0_camera3_clk */
- <1 RK_PD6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera4_clk: mipim0-camera4-clk {
- rockchip,pins =
- /* mipim0_camera4_clk */
- <1 RK_PD7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera0_clk: mipim1-camera0-clk {
- rockchip,pins =
- /* mipim1_camera0_clk */
- <3 RK_PA5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera1_clk: mipim1-camera1-clk {
- rockchip,pins =
- /* mipim1_camera1_clk */
- <3 RK_PA6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera2_clk: mipim1-camera2-clk {
- rockchip,pins =
- /* mipim1_camera2_clk */
- <3 RK_PA7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera3_clk: mipim1-camera3-clk {
- rockchip,pins =
- /* mipim1_camera3_clk */
- <3 RK_PB0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera4_clk: mipim1-camera4-clk {
- rockchip,pins =
- /* mipim1_camera4_clk */
- <3 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipi_te0: mipi-te0 {
- rockchip,pins =
- /* mipi_te0 */
- <3 RK_PC2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipi_te1: mipi-te1 {
- rockchip,pins =
- /* mipi_te1 */
- <3 RK_PC3 2 &pcfg_pull_none>;
- };
- };
-
- npu {
- /omit-if-no-ref/
- npu_pins: npu-pins {
- rockchip,pins =
- /* npu_avs */
- <0 RK_PC6 2 &pcfg_pull_none>;
- };
- };
-
- pcie20x1 {
- /omit-if-no-ref/
- pcie20x1m0_pins: pcie20x1m0-pins {
- rockchip,pins =
- /* pcie20x1_2_clkreqn_m0 */
- <3 RK_PC7 4 &pcfg_pull_none>,
- /* pcie20x1_2_perstn_m0 */
- <3 RK_PD1 4 &pcfg_pull_none>,
- /* pcie20x1_2_waken_m0 */
- <3 RK_PD0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20x1m1_pins: pcie20x1m1-pins {
- rockchip,pins =
- /* pcie20x1_2_clkreqn_m1 */
- <4 RK_PB7 4 &pcfg_pull_none>,
- /* pcie20x1_2_perstn_m1 */
- <4 RK_PC1 4 &pcfg_pull_none>,
- /* pcie20x1_2_waken_m1 */
- <4 RK_PC0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
- rockchip,pins =
- /* pcie20x1_2_button_rstn */
- <4 RK_PB3 4 &pcfg_pull_none>;
- };
- };
-
- pcie30phy {
- /omit-if-no-ref/
- pcie30phy_pins: pcie30phy-pins {
- rockchip,pins =
- /* pcie30phy_dtb0 */
- <1 RK_PC4 4 &pcfg_pull_none>,
- /* pcie30phy_dtb1 */
- <1 RK_PD1 4 &pcfg_pull_none>;
- };
- };
-
- pcie30x1 {
- /omit-if-no-ref/
- pcie30x1m0_pins: pcie30x1m0-pins {
- rockchip,pins =
- /* pcie30x1_0_clkreqn_m0 */
- <0 RK_PC0 12 &pcfg_pull_none>,
- /* pcie30x1_0_perstn_m0 */
- <0 RK_PC5 12 &pcfg_pull_none>,
- /* pcie30x1_0_waken_m0 */
- <0 RK_PC4 12 &pcfg_pull_none>,
- /* pcie30x1_1_clkreqn_m0 */
- <0 RK_PB5 12 &pcfg_pull_none>,
- /* pcie30x1_1_perstn_m0 */
- <0 RK_PB7 12 &pcfg_pull_none>,
- /* pcie30x1_1_waken_m0 */
- <0 RK_PB6 12 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1m1_pins: pcie30x1m1-pins {
- rockchip,pins =
- /* pcie30x1_0_clkreqn_m1 */
- <4 RK_PA3 4 &pcfg_pull_none>,
- /* pcie30x1_0_perstn_m1 */
- <4 RK_PA5 4 &pcfg_pull_none>,
- /* pcie30x1_0_waken_m1 */
- <4 RK_PA4 4 &pcfg_pull_none>,
- /* pcie30x1_1_clkreqn_m1 */
- <4 RK_PA0 4 &pcfg_pull_none>,
- /* pcie30x1_1_perstn_m1 */
- <4 RK_PA2 4 &pcfg_pull_none>,
- /* pcie30x1_1_waken_m1 */
- <4 RK_PA1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1m2_pins: pcie30x1m2-pins {
- rockchip,pins =
- /* pcie30x1_0_clkreqn_m2 */
- <1 RK_PB5 4 &pcfg_pull_none>,
- /* pcie30x1_0_perstn_m2 */
- <1 RK_PB4 4 &pcfg_pull_none>,
- /* pcie30x1_0_waken_m2 */
- <1 RK_PB3 4 &pcfg_pull_none>,
- /* pcie30x1_1_clkreqn_m2 */
- <1 RK_PA0 4 &pcfg_pull_none>,
- /* pcie30x1_1_perstn_m2 */
- <1 RK_PA7 4 &pcfg_pull_none>,
- /* pcie30x1_1_waken_m2 */
- <1 RK_PA1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
- rockchip,pins =
- /* pcie30x1_0_button_rstn */
- <4 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
- rockchip,pins =
- /* pcie30x1_1_button_rstn */
- <4 RK_PB2 4 &pcfg_pull_none>;
- };
- };
-
- pcie30x2 {
- /omit-if-no-ref/
- pcie30x2m0_pins: pcie30x2m0-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m0 */
- <0 RK_PD1 12 &pcfg_pull_none>,
- /* pcie30x2_perstn_m0 */
- <0 RK_PD4 12 &pcfg_pull_none>,
- /* pcie30x2_waken_m0 */
- <0 RK_PD2 12 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m1_pins: pcie30x2m1-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m1 */
- <4 RK_PA6 4 &pcfg_pull_none>,
- /* pcie30x2_perstn_m1 */
- <4 RK_PB0 4 &pcfg_pull_none>,
- /* pcie30x2_waken_m1 */
- <4 RK_PA7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m2_pins: pcie30x2m2-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m2 */
- <3 RK_PD2 4 &pcfg_pull_none>,
- /* pcie30x2_perstn_m2 */
- <3 RK_PD4 4 &pcfg_pull_none>,
- /* pcie30x2_waken_m2 */
- <3 RK_PD3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m3_pins: pcie30x2m3-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m3 */
- <1 RK_PD7 4 &pcfg_pull_none>,
- /* pcie30x2_perstn_m3 */
- <1 RK_PB7 4 &pcfg_pull_none>,
- /* pcie30x2_waken_m3 */
- <1 RK_PB6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2_button_rstn: pcie30x2-button-rstn {
- rockchip,pins =
- /* pcie30x2_button_rstn */
- <3 RK_PC1 4 &pcfg_pull_none>;
- };
- };
-
- pcie30x4 {
- /omit-if-no-ref/
- pcie30x4m0_pins: pcie30x4m0-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m0 */
- <0 RK_PC6 12 &pcfg_pull_none>,
- /* pcie30x4_perstn_m0 */
- <0 RK_PD0 12 &pcfg_pull_none>,
- /* pcie30x4_waken_m0 */
- <0 RK_PC7 12 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4m1_pins: pcie30x4m1-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m1 */
- <4 RK_PB4 4 &pcfg_pull_none>,
- /* pcie30x4_perstn_m1 */
- <4 RK_PB6 4 &pcfg_pull_none>,
- /* pcie30x4_waken_m1 */
- <4 RK_PB5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4m2_pins: pcie30x4m2-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m2 */
- <3 RK_PC4 4 &pcfg_pull_none>,
- /* pcie30x4_perstn_m2 */
- <3 RK_PC6 4 &pcfg_pull_none>,
- /* pcie30x4_waken_m2 */
- <3 RK_PC5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4m3_pins: pcie30x4m3-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m3 */
- <1 RK_PB0 4 &pcfg_pull_none>,
- /* pcie30x4_perstn_m3 */
- <1 RK_PB2 4 &pcfg_pull_none>,
- /* pcie30x4_waken_m3 */
- <1 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4_button_rstn: pcie30x4-button-rstn {
- rockchip,pins =
- /* pcie30x4_button_rstn */
- <3 RK_PD5 4 &pcfg_pull_none>;
- };
- };
-
- pdm0 {
- /omit-if-no-ref/
- pdm0m0_clk: pdm0m0-clk {
- rockchip,pins =
- /* pdm0_clk0_m0 */
- <1 RK_PC6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_clk1: pdm0m0-clk1 {
- rockchip,pins =
- /* pdm0m0_clk1 */
- <1 RK_PC4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi0: pdm0m0-sdi0 {
- rockchip,pins =
- /* pdm0m0_sdi0 */
- <1 RK_PD5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi1: pdm0m0-sdi1 {
- rockchip,pins =
- /* pdm0m0_sdi1 */
- <1 RK_PD1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi2: pdm0m0-sdi2 {
- rockchip,pins =
- /* pdm0m0_sdi2 */
- <1 RK_PD2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi3: pdm0m0-sdi3 {
- rockchip,pins =
- /* pdm0m0_sdi3 */
- <1 RK_PD3 3 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- pdm0m1_clk: pdm0m1-clk {
- rockchip,pins =
- /* pdm0_clk0_m1 */
- <0 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_clk1: pdm0m1-clk1 {
- rockchip,pins =
- /* pdm0m1_clk1 */
- <0 RK_PC4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi0: pdm0m1-sdi0 {
- rockchip,pins =
- /* pdm0m1_sdi0 */
- <0 RK_PC7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi1: pdm0m1-sdi1 {
- rockchip,pins =
- /* pdm0m1_sdi1 */
- <0 RK_PD0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi2: pdm0m1-sdi2 {
- rockchip,pins =
- /* pdm0m1_sdi2 */
- <0 RK_PD4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi3: pdm0m1-sdi3 {
- rockchip,pins =
- /* pdm0m1_sdi3 */
- <0 RK_PD6 2 &pcfg_pull_none>;
- };
- };
-
- pdm1 {
- /omit-if-no-ref/
- pdm1m0_clk: pdm1m0-clk {
- rockchip,pins =
- /* pdm1_clk0_m0 */
- <4 RK_PD5 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_clk1: pdm1m0-clk1 {
- rockchip,pins =
- /* pdm1m0_clk1 */
- <4 RK_PD4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi0: pdm1m0-sdi0 {
- rockchip,pins =
- /* pdm1m0_sdi0 */
- <4 RK_PD3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi1: pdm1m0-sdi1 {
- rockchip,pins =
- /* pdm1m0_sdi1 */
- <4 RK_PD2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi2: pdm1m0-sdi2 {
- rockchip,pins =
- /* pdm1m0_sdi2 */
- <4 RK_PD1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi3: pdm1m0-sdi3 {
- rockchip,pins =
- /* pdm1m0_sdi3 */
- <4 RK_PD0 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- pdm1m1_clk: pdm1m1-clk {
- rockchip,pins =
- /* pdm1_clk0_m1 */
- <1 RK_PB4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_clk1: pdm1m1-clk1 {
- rockchip,pins =
- /* pdm1m1_clk1 */
- <1 RK_PB3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi0: pdm1m1-sdi0 {
- rockchip,pins =
- /* pdm1m1_sdi0 */
- <1 RK_PA7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi1: pdm1m1-sdi1 {
- rockchip,pins =
- /* pdm1m1_sdi1 */
- <1 RK_PB0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi2: pdm1m1-sdi2 {
- rockchip,pins =
- /* pdm1m1_sdi2 */
- <1 RK_PB1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi3: pdm1m1-sdi3 {
- rockchip,pins =
- /* pdm1m1_sdi3 */
- <1 RK_PB2 2 &pcfg_pull_none>;
- };
- };
-
- pmic {
- /omit-if-no-ref/
- pmic_pins: pmic-pins {
- rockchip,pins =
- /* pmic_int_l */
- <0 RK_PA7 0 &pcfg_pull_up>,
- /* pmic_sleep1 */
- <0 RK_PA2 1 &pcfg_pull_down>,
- /* pmic_sleep2 */
- <0 RK_PA3 1 &pcfg_pull_none>,
- /* pmic_sleep3 */
- <0 RK_PC1 1 &pcfg_pull_none>,
- /* pmic_sleep4 */
- <0 RK_PC2 1 &pcfg_pull_none>,
- /* pmic_sleep5 */
- <0 RK_PC3 1 &pcfg_pull_none>,
- /* pmic_sleep6 */
- <0 RK_PD6 1 &pcfg_pull_none>;
- };
- };
-
- pmu {
- /omit-if-no-ref/
- pmu_pins: pmu-pins {
- rockchip,pins =
- /* pmu_debug */
- <0 RK_PA5 3 &pcfg_pull_none>;
- };
- };
-
- pwm0 {
- /omit-if-no-ref/
- pwm0m0_pins: pwm0m0-pins {
- rockchip,pins =
- /* pwm0_m0 */
- <0 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm0m1_pins: pwm0m1-pins {
- rockchip,pins =
- /* pwm0_m1 */
- <1 RK_PD2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm0m2_pins: pwm0m2-pins {
- rockchip,pins =
- /* pwm0_m2 */
- <1 RK_PA2 11 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- /omit-if-no-ref/
- pwm1m0_pins: pwm1m0-pins {
- rockchip,pins =
- /* pwm1_m0 */
- <0 RK_PC0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm1m1_pins: pwm1m1-pins {
- rockchip,pins =
- /* pwm1_m1 */
- <1 RK_PD3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm1m2_pins: pwm1m2-pins {
- rockchip,pins =
- /* pwm1_m2 */
- <1 RK_PA3 11 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- /omit-if-no-ref/
- pwm2m0_pins: pwm2m0-pins {
- rockchip,pins =
- /* pwm2_m0 */
- <0 RK_PC4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm2m1_pins: pwm2m1-pins {
- rockchip,pins =
- /* pwm2_m1 */
- <3 RK_PB1 11 &pcfg_pull_none>;
- };
- };
-
- pwm3 {
- /omit-if-no-ref/
- pwm3m0_pins: pwm3m0-pins {
- rockchip,pins =
- /* pwm3_ir_m0 */
- <0 RK_PD4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm3m1_pins: pwm3m1-pins {
- rockchip,pins =
- /* pwm3_ir_m1 */
- <3 RK_PB2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm3m2_pins: pwm3m2-pins {
- rockchip,pins =
- /* pwm3_ir_m2 */
- <1 RK_PC2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm3m3_pins: pwm3m3-pins {
- rockchip,pins =
- /* pwm3_ir_m3 */
- <1 RK_PA7 11 &pcfg_pull_none>;
- };
- };
-
- pwm4 {
- /omit-if-no-ref/
- pwm4m0_pins: pwm4m0-pins {
- rockchip,pins =
- /* pwm4_m0 */
- <0 RK_PC5 11 &pcfg_pull_none>;
- };
- };
-
- pwm5 {
- /omit-if-no-ref/
- pwm5m0_pins: pwm5m0-pins {
- rockchip,pins =
- /* pwm5_m0 */
- <0 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm5m1_pins: pwm5m1-pins {
- rockchip,pins =
- /* pwm5_m1 */
- <0 RK_PC6 11 &pcfg_pull_none>;
- };
- };
-
- pwm6 {
- /omit-if-no-ref/
- pwm6m0_pins: pwm6m0-pins {
- rockchip,pins =
- /* pwm6_m0 */
- <0 RK_PC7 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm6m1_pins: pwm6m1-pins {
- rockchip,pins =
- /* pwm6_m1 */
- <4 RK_PC1 11 &pcfg_pull_none>;
- };
- };
-
- pwm7 {
- /omit-if-no-ref/
- pwm7m0_pins: pwm7m0-pins {
- rockchip,pins =
- /* pwm7_ir_m0 */
- <0 RK_PD0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm7m1_pins: pwm7m1-pins {
- rockchip,pins =
- /* pwm7_ir_m1 */
- <4 RK_PD4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm7m2_pins: pwm7m2-pins {
- rockchip,pins =
- /* pwm7_ir_m2 */
- <1 RK_PC3 11 &pcfg_pull_none>;
- };
- };
-
- pwm8 {
- /omit-if-no-ref/
- pwm8m0_pins: pwm8m0-pins {
- rockchip,pins =
- /* pwm8_m0 */
- <3 RK_PA7 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm8m1_pins: pwm8m1-pins {
- rockchip,pins =
- /* pwm8_m1 */
- <4 RK_PD0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm8m2_pins: pwm8m2-pins {
- rockchip,pins =
- /* pwm8_m2 */
- <3 RK_PD0 11 &pcfg_pull_none>;
- };
- };
-
- pwm9 {
- /omit-if-no-ref/
- pwm9m0_pins: pwm9m0-pins {
- rockchip,pins =
- /* pwm9_m0 */
- <3 RK_PB0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm9m1_pins: pwm9m1-pins {
- rockchip,pins =
- /* pwm9_m1 */
- <4 RK_PD1 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm9m2_pins: pwm9m2-pins {
- rockchip,pins =
- /* pwm9_m2 */
- <3 RK_PD1 11 &pcfg_pull_none>;
- };
- };
-
- pwm10 {
- /omit-if-no-ref/
- pwm10m0_pins: pwm10m0-pins {
- rockchip,pins =
- /* pwm10_m0 */
- <3 RK_PA0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm10m1_pins: pwm10m1-pins {
- rockchip,pins =
- /* pwm10_m1 */
- <4 RK_PD3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm10m2_pins: pwm10m2-pins {
- rockchip,pins =
- /* pwm10_m2 */
- <3 RK_PD3 11 &pcfg_pull_none>;
- };
- };
-
- pwm11 {
- /omit-if-no-ref/
- pwm11m0_pins: pwm11m0-pins {
- rockchip,pins =
- /* pwm11_ir_m0 */
- <3 RK_PA1 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m1_pins: pwm11m1-pins {
- rockchip,pins =
- /* pwm11_ir_m1 */
- <4 RK_PB4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m2_pins: pwm11m2-pins {
- rockchip,pins =
- /* pwm11_ir_m2 */
- <1 RK_PC4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m3_pins: pwm11m3-pins {
- rockchip,pins =
- /* pwm11_ir_m3 */
- <3 RK_PD5 11 &pcfg_pull_none>;
- };
- };
-
- pwm12 {
- /omit-if-no-ref/
- pwm12m0_pins: pwm12m0-pins {
- rockchip,pins =
- /* pwm12_m0 */
- <3 RK_PB5 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm12m1_pins: pwm12m1-pins {
- rockchip,pins =
- /* pwm12_m1 */
- <4 RK_PB5 11 &pcfg_pull_none>;
- };
- };
-
- pwm13 {
- /omit-if-no-ref/
- pwm13m0_pins: pwm13m0-pins {
- rockchip,pins =
- /* pwm13_m0 */
- <3 RK_PB6 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm13m1_pins: pwm13m1-pins {
- rockchip,pins =
- /* pwm13_m1 */
- <4 RK_PB6 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm13m2_pins: pwm13m2-pins {
- rockchip,pins =
- /* pwm13_m2 */
- <1 RK_PB7 11 &pcfg_pull_none>;
- };
- };
-
- pwm14 {
- /omit-if-no-ref/
- pwm14m0_pins: pwm14m0-pins {
- rockchip,pins =
- /* pwm14_m0 */
- <3 RK_PC2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm14m1_pins: pwm14m1-pins {
- rockchip,pins =
- /* pwm14_m1 */
- <4 RK_PB2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm14m2_pins: pwm14m2-pins {
- rockchip,pins =
- /* pwm14_m2 */
- <1 RK_PD6 11 &pcfg_pull_none>;
- };
- };
-
- pwm15 {
- /omit-if-no-ref/
- pwm15m0_pins: pwm15m0-pins {
- rockchip,pins =
- /* pwm15_ir_m0 */
- <3 RK_PC3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m1_pins: pwm15m1-pins {
- rockchip,pins =
- /* pwm15_ir_m1 */
- <4 RK_PB3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m2_pins: pwm15m2-pins {
- rockchip,pins =
- /* pwm15_ir_m2 */
- <1 RK_PC6 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m3_pins: pwm15m3-pins {
- rockchip,pins =
- /* pwm15_ir_m3 */
- <1 RK_PD7 11 &pcfg_pull_none>;
- };
- };
-
- refclk {
- /omit-if-no-ref/
- refclk_pins: refclk-pins {
- rockchip,pins =
- /* refclk_out */
- <0 RK_PA0 1 &pcfg_pull_none>;
- };
- };
-
- sata {
- /omit-if-no-ref/
- sata_pins: sata-pins {
- rockchip,pins =
- /* sata_cp_pod */
- <0 RK_PC6 13 &pcfg_pull_none>,
- /* sata_cpdet */
- <0 RK_PD4 13 &pcfg_pull_none>,
- /* sata_mp_switch */
- <0 RK_PD5 13 &pcfg_pull_none>;
- };
- };
-
- sata0 {
- /omit-if-no-ref/
- sata0m0_pins: sata0m0-pins {
- rockchip,pins =
- /* sata0_act_led_m0 */
- <4 RK_PB6 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sata0m1_pins: sata0m1-pins {
- rockchip,pins =
- /* sata0_act_led_m1 */
- <1 RK_PB3 6 &pcfg_pull_none>;
- };
- };
-
- sata1 {
- /omit-if-no-ref/
- sata1m0_pins: sata1m0-pins {
- rockchip,pins =
- /* sata1_act_led_m0 */
- <4 RK_PB5 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sata1m1_pins: sata1m1-pins {
- rockchip,pins =
- /* sata1_act_led_m1 */
- <1 RK_PA1 6 &pcfg_pull_none>;
- };
- };
-
- sata2 {
- /omit-if-no-ref/
- sata2m0_pins: sata2m0-pins {
- rockchip,pins =
- /* sata2_act_led_m0 */
- <4 RK_PB1 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sata2m1_pins: sata2m1-pins {
- rockchip,pins =
- /* sata2_act_led_m1 */
- <1 RK_PB7 6 &pcfg_pull_none>;
- };
- };
-
- sdio {
- /omit-if-no-ref/
- sdiom1_pins: sdiom1-pins {
- rockchip,pins =
- /* sdio_clk_m1 */
- <3 RK_PA5 2 &pcfg_pull_none>,
- /* sdio_cmd_m1 */
- <3 RK_PA4 2 &pcfg_pull_up>,
- /* sdio_d0_m1 */
- <3 RK_PA0 2 &pcfg_pull_up>,
- /* sdio_d1_m1 */
- <3 RK_PA1 2 &pcfg_pull_up>,
- /* sdio_d2_m1 */
- <3 RK_PA2 2 &pcfg_pull_up>,
- /* sdio_d3_m1 */
- <3 RK_PA3 2 &pcfg_pull_up>;
- };
- };
-
- sdmmc {
- /omit-if-no-ref/
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- /* sdmmc_d0 */
- <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc_d1 */
- <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc_d2 */
- <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc_d3 */
- <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc_clk: sdmmc-clk {
- rockchip,pins =
- /* sdmmc_clk */
- <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins =
- /* sdmmc_cmd */
- <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc_det: sdmmc-det {
- rockchip,pins =
- /* sdmmc_det */
- <0 RK_PA4 1 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- sdmmc_pwren: sdmmc-pwren {
- rockchip,pins =
- /* sdmmc_pwren */
- <0 RK_PA5 2 &pcfg_pull_none>;
- };
- };
-
- spdif0 {
- /omit-if-no-ref/
- spdif0m0_tx: spdif0m0-tx {
- rockchip,pins =
- /* spdif0m0_tx */
- <1 RK_PB6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdif0m1_tx: spdif0m1-tx {
- rockchip,pins =
- /* spdif0m1_tx */
- <4 RK_PB4 6 &pcfg_pull_none>;
- };
- };
-
- spdif1 {
- /omit-if-no-ref/
- spdif1m0_tx: spdif1m0-tx {
- rockchip,pins =
- /* spdif1m0_tx */
- <1 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdif1m1_tx: spdif1m1-tx {
- rockchip,pins =
- /* spdif1m1_tx */
- <4 RK_PB1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdif1m2_tx: spdif1m2-tx {
- rockchip,pins =
- /* spdif1m2_tx */
- <4 RK_PC1 3 &pcfg_pull_none>;
- };
- };
-
- spi0 {
- /omit-if-no-ref/
- spi0m0_pins: spi0m0-pins {
- rockchip,pins =
- /* spi0_clk_m0 */
- <0 RK_PC6 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_miso_m0 */
- <0 RK_PC7 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_mosi_m0 */
- <0 RK_PC0 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs0: spi0m0-cs0 {
- rockchip,pins =
- /* spi0_cs0_m0 */
- <0 RK_PD1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs1: spi0m0-cs1 {
- rockchip,pins =
- /* spi0_cs1_m0 */
- <0 RK_PB7 8 &pcfg_pull_up_drv_level_6>;
- };
- /omit-if-no-ref/
- spi0m1_pins: spi0m1-pins {
- rockchip,pins =
- /* spi0_clk_m1 */
- <4 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_miso_m1 */
- <4 RK_PA0 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_mosi_m1 */
- <4 RK_PA1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m1_cs0: spi0m1-cs0 {
- rockchip,pins =
- /* spi0_cs0_m1 */
- <4 RK_PB2 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m1_cs1: spi0m1-cs1 {
- rockchip,pins =
- /* spi0_cs1_m1 */
- <4 RK_PB1 8 &pcfg_pull_up_drv_level_6>;
- };
- /omit-if-no-ref/
- spi0m2_pins: spi0m2-pins {
- rockchip,pins =
- /* spi0_clk_m2 */
- <1 RK_PB3 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_miso_m2 */
- <1 RK_PB1 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_mosi_m2 */
- <1 RK_PB2 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m2_cs0: spi0m2-cs0 {
- rockchip,pins =
- /* spi0_cs0_m2 */
- <1 RK_PB4 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m2_cs1: spi0m2-cs1 {
- rockchip,pins =
- /* spi0_cs1_m2 */
- <1 RK_PB5 8 &pcfg_pull_up_drv_level_6>;
- };
- /omit-if-no-ref/
- spi0m3_pins: spi0m3-pins {
- rockchip,pins =
- /* spi0_clk_m3 */
- <3 RK_PD3 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_miso_m3 */
- <3 RK_PD1 8 &pcfg_pull_up_drv_level_6>,
- /* spi0_mosi_m3 */
- <3 RK_PD2 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m3_cs0: spi0m3-cs0 {
- rockchip,pins =
- /* spi0_cs0_m3 */
- <3 RK_PD4 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi0m3_cs1: spi0m3-cs1 {
- rockchip,pins =
- /* spi0_cs1_m3 */
- <3 RK_PD5 8 &pcfg_pull_up_drv_level_6>;
- };
- };
-
- spi1 {
- /omit-if-no-ref/
- spi1m1_pins: spi1m1-pins {
- rockchip,pins =
- /* spi1_clk_m1 */
- <3 RK_PC1 8 &pcfg_pull_up_drv_level_6>,
- /* spi1_miso_m1 */
- <3 RK_PC0 8 &pcfg_pull_up_drv_level_6>,
- /* spi1_mosi_m1 */
- <3 RK_PB7 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi1m1_cs0: spi1m1-cs0 {
- rockchip,pins =
- /* spi1_cs0_m1 */
- <3 RK_PC2 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi1m1_cs1: spi1m1-cs1 {
- rockchip,pins =
- /* spi1_cs1_m1 */
- <3 RK_PC3 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi1m2_pins: spi1m2-pins {
- rockchip,pins =
- /* spi1_clk_m2 */
- <1 RK_PD2 8 &pcfg_pull_up_drv_level_6>,
- /* spi1_miso_m2 */
- <1 RK_PD0 8 &pcfg_pull_up_drv_level_6>,
- /* spi1_mosi_m2 */
- <1 RK_PD1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi1m2_cs0: spi1m2-cs0 {
- rockchip,pins =
- /* spi1_cs0_m2 */
- <1 RK_PD3 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi1m2_cs1: spi1m2-cs1 {
- rockchip,pins =
- /* spi1_cs1_m2 */
- <1 RK_PD5 8 &pcfg_pull_up_drv_level_6>;
- };
- };
-
- spi2 {
- /omit-if-no-ref/
- spi2m0_pins: spi2m0-pins {
- rockchip,pins =
- /* spi2_clk_m0 */
- <1 RK_PA6 8 &pcfg_pull_up_drv_level_6>,
- /* spi2_miso_m0 */
- <1 RK_PA4 8 &pcfg_pull_up_drv_level_6>,
- /* spi2_mosi_m0 */
- <1 RK_PA5 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs0: spi2m0-cs0 {
- rockchip,pins =
- /* spi2_cs0_m0 */
- <1 RK_PA7 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs1: spi2m0-cs1 {
- rockchip,pins =
- /* spi2_cs1_m0 */
- <1 RK_PB0 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi2m1_pins: spi2m1-pins {
- rockchip,pins =
- /* spi2_clk_m1 */
- <4 RK_PA6 8 &pcfg_pull_up_drv_level_6>,
- /* spi2_miso_m1 */
- <4 RK_PA4 8 &pcfg_pull_up_drv_level_6>,
- /* spi2_mosi_m1 */
- <4 RK_PA5 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs0: spi2m1-cs0 {
- rockchip,pins =
- /* spi2_cs0_m1 */
- <4 RK_PA7 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs1: spi2m1-cs1 {
- rockchip,pins =
- /* spi2_cs1_m1 */
- <4 RK_PB0 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi2m2_pins: spi2m2-pins {
- rockchip,pins =
- /* spi2_clk_m2 */
- <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
- /* spi2_miso_m2 */
- <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
- /* spi2_mosi_m2 */
- <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m2_cs0: spi2m2-cs0 {
- rockchip,pins =
- /* spi2_cs0_m2 */
- <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m2_cs1: spi2m2-cs1 {
- rockchip,pins =
- /* spi2_cs1_m2 */
- <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi3 {
- /omit-if-no-ref/
- spi3m1_pins: spi3m1-pins {
- rockchip,pins =
- /* spi3_clk_m1 */
- <4 RK_PB7 8 &pcfg_pull_up_drv_level_6>,
- /* spi3_miso_m1 */
- <4 RK_PB5 8 &pcfg_pull_up_drv_level_6>,
- /* spi3_mosi_m1 */
- <4 RK_PB6 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs0: spi3m1-cs0 {
- rockchip,pins =
- /* spi3_cs0_m1 */
- <4 RK_PC0 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs1: spi3m1-cs1 {
- rockchip,pins =
- /* spi3_cs1_m1 */
- <4 RK_PC1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m2_pins: spi3m2-pins {
- rockchip,pins =
- /* spi3_clk_m2 */
- <0 RK_PD3 8 &pcfg_pull_up_drv_level_6>,
- /* spi3_miso_m2 */
- <0 RK_PD0 8 &pcfg_pull_up_drv_level_6>,
- /* spi3_mosi_m2 */
- <0 RK_PD2 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m2_cs0: spi3m2-cs0 {
- rockchip,pins =
- /* spi3_cs0_m2 */
- <0 RK_PD4 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m2_cs1: spi3m2-cs1 {
- rockchip,pins =
- /* spi3_cs1_m2 */
- <0 RK_PD5 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m3_pins: spi3m3-pins {
- rockchip,pins =
- /* spi3_clk_m3 */
- <3 RK_PD0 8 &pcfg_pull_up_drv_level_6>,
- /* spi3_miso_m3 */
- <3 RK_PC6 8 &pcfg_pull_up_drv_level_6>,
- /* spi3_mosi_m3 */
- <3 RK_PC7 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m3_cs0: spi3m3-cs0 {
- rockchip,pins =
- /* spi3_cs0_m3 */
- <3 RK_PC4 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi3m3_cs1: spi3m3-cs1 {
- rockchip,pins =
- /* spi3_cs1_m3 */
- <3 RK_PC5 8 &pcfg_pull_up_drv_level_6>;
- };
- };
-
- spi4 {
- /omit-if-no-ref/
- spi4m0_pins: spi4m0-pins {
- rockchip,pins =
- /* spi4_clk_m0 */
- <1 RK_PC2 8 &pcfg_pull_up_drv_level_6>,
- /* spi4_miso_m0 */
- <1 RK_PC0 8 &pcfg_pull_up_drv_level_6>,
- /* spi4_mosi_m0 */
- <1 RK_PC1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m0_cs0: spi4m0-cs0 {
- rockchip,pins =
- /* spi4_cs0_m0 */
- <1 RK_PC3 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m0_cs1: spi4m0-cs1 {
- rockchip,pins =
- /* spi4_cs1_m0 */
- <1 RK_PC4 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m1_pins: spi4m1-pins {
- rockchip,pins =
- /* spi4_clk_m1 */
- <3 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
- /* spi4_miso_m1 */
- <3 RK_PA0 8 &pcfg_pull_up_drv_level_6>,
- /* spi4_mosi_m1 */
- <3 RK_PA1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m1_cs0: spi4m1-cs0 {
- rockchip,pins =
- /* spi4_cs0_m1 */
- <3 RK_PA3 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m1_cs1: spi4m1-cs1 {
- rockchip,pins =
- /* spi4_cs1_m1 */
- <3 RK_PA4 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m2_pins: spi4m2-pins {
- rockchip,pins =
- /* spi4_clk_m2 */
- <1 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
- /* spi4_miso_m2 */
- <1 RK_PA0 8 &pcfg_pull_up_drv_level_6>,
- /* spi4_mosi_m2 */
- <1 RK_PA1 8 &pcfg_pull_up_drv_level_6>;
- };
-
- /omit-if-no-ref/
- spi4m2_cs0: spi4m2-cs0 {
- rockchip,pins =
- /* spi4_cs0_m2 */
- <1 RK_PA3 8 &pcfg_pull_up_drv_level_6>;
- };
- };
-
- tsadc {
- /omit-if-no-ref/
- tsadcm1_shut: tsadcm1-shut {
- rockchip,pins =
- /* tsadcm1_shut */
- <0 RK_PA2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- tsadc_shut: tsadc-shut {
- rockchip,pins =
- /* tsadc_shut */
- <0 RK_PA1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- tsadc_shut_org: tsadc-shut-org {
- rockchip,pins =
- /* tsadc_shut_org */
- <0 RK_PA1 1 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- /omit-if-no-ref/
- uart0m0_xfer: uart0m0-xfer {
- rockchip,pins =
- /* uart0_rx_m0 */
- <0 RK_PC4 4 &pcfg_pull_up>,
- /* uart0_tx_m0 */
- <0 RK_PC5 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0m1_xfer: uart0m1-xfer {
- rockchip,pins =
- /* uart0_rx_m1 */
- <0 RK_PB0 4 &pcfg_pull_up>,
- /* uart0_tx_m1 */
- <0 RK_PB1 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0m2_xfer: uart0m2-xfer {
- rockchip,pins =
- /* uart0_rx_m2 */
- <4 RK_PA4 10 &pcfg_pull_up>,
- /* uart0_tx_m2 */
- <4 RK_PA3 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0_ctsn: uart0-ctsn {
- rockchip,pins =
- /* uart0_ctsn */
- <0 RK_PD1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart0_rtsn: uart0-rtsn {
- rockchip,pins =
- /* uart0_rtsn */
- <0 RK_PC6 4 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- /omit-if-no-ref/
- uart1m1_xfer: uart1m1-xfer {
- rockchip,pins =
- /* uart1_rx_m1 */
- <1 RK_PB7 10 &pcfg_pull_up>,
- /* uart1_tx_m1 */
- <1 RK_PB6 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m1_ctsn: uart1m1-ctsn {
- rockchip,pins =
- /* uart1m1_ctsn */
- <1 RK_PD7 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m1_rtsn: uart1m1-rtsn {
- rockchip,pins =
- /* uart1m1_rtsn */
- <1 RK_PD6 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m2_xfer: uart1m2-xfer {
- rockchip,pins =
- /* uart1_rx_m2 */
- <0 RK_PD2 10 &pcfg_pull_up>,
- /* uart1_tx_m2 */
- <0 RK_PD1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m2_ctsn: uart1m2-ctsn {
- rockchip,pins =
- /* uart1m2_ctsn */
- <0 RK_PD0 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m2_rtsn: uart1m2-rtsn {
- rockchip,pins =
- /* uart1m2_rtsn */
- <0 RK_PC7 10 &pcfg_pull_none>;
- };
- };
-
- uart2 {
- /omit-if-no-ref/
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins =
- /* uart2_rx_m0 */
- <0 RK_PB6 10 &pcfg_pull_up>,
- /* uart2_tx_m0 */
- <0 RK_PB5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- /* uart2_rx_m1 */
- <4 RK_PD1 10 &pcfg_pull_up>,
- /* uart2_tx_m1 */
- <4 RK_PD0 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2m2_xfer: uart2m2-xfer {
- rockchip,pins =
- /* uart2_rx_m2 */
- <3 RK_PB2 10 &pcfg_pull_up>,
- /* uart2_tx_m2 */
- <3 RK_PB1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2_ctsn: uart2-ctsn {
- rockchip,pins =
- /* uart2_ctsn */
- <3 RK_PB4 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart2_rtsn: uart2-rtsn {
- rockchip,pins =
- /* uart2_rtsn */
- <3 RK_PB3 10 &pcfg_pull_none>;
- };
- };
-
- uart3 {
- /omit-if-no-ref/
- uart3m0_xfer: uart3m0-xfer {
- rockchip,pins =
- /* uart3_rx_m0 */
- <1 RK_PC0 10 &pcfg_pull_up>,
- /* uart3_tx_m0 */
- <1 RK_PC1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3m1_xfer: uart3m1-xfer {
- rockchip,pins =
- /* uart3_rx_m1 */
- <3 RK_PB6 10 &pcfg_pull_up>,
- /* uart3_tx_m1 */
- <3 RK_PB5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3m2_xfer: uart3m2-xfer {
- rockchip,pins =
- /* uart3_rx_m2 */
- <4 RK_PA6 10 &pcfg_pull_up>,
- /* uart3_tx_m2 */
- <4 RK_PA5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3_ctsn: uart3-ctsn {
- rockchip,pins =
- /* uart3_ctsn */
- <1 RK_PC3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart3_rtsn: uart3-rtsn {
- rockchip,pins =
- /* uart3_rtsn */
- <1 RK_PC2 10 &pcfg_pull_none>;
- };
- };
-
- uart4 {
- /omit-if-no-ref/
- uart4m0_xfer: uart4m0-xfer {
- rockchip,pins =
- /* uart4_rx_m0 */
- <1 RK_PD3 10 &pcfg_pull_up>,
- /* uart4_tx_m0 */
- <1 RK_PD2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4m1_xfer: uart4m1-xfer {
- rockchip,pins =
- /* uart4_rx_m1 */
- <3 RK_PD0 10 &pcfg_pull_up>,
- /* uart4_tx_m1 */
- <3 RK_PD1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4m2_xfer: uart4m2-xfer {
- rockchip,pins =
- /* uart4_rx_m2 */
- <1 RK_PB2 10 &pcfg_pull_up>,
- /* uart4_tx_m2 */
- <1 RK_PB3 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4_ctsn: uart4-ctsn {
- rockchip,pins =
- /* uart4_ctsn */
- <1 RK_PC7 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart4_rtsn: uart4-rtsn {
- rockchip,pins =
- /* uart4_rtsn */
- <1 RK_PC5 10 &pcfg_pull_none>;
- };
- };
-
- uart5 {
- /omit-if-no-ref/
- uart5m0_xfer: uart5m0-xfer {
- rockchip,pins =
- /* uart5_rx_m0 */
- <4 RK_PD4 10 &pcfg_pull_up>,
- /* uart5_tx_m0 */
- <4 RK_PD5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart5m0_ctsn: uart5m0-ctsn {
- rockchip,pins =
- /* uart5m0_ctsn */
- <4 RK_PD2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m0_rtsn: uart5m0-rtsn {
- rockchip,pins =
- /* uart5m0_rtsn */
- <4 RK_PD3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m1_xfer: uart5m1-xfer {
- rockchip,pins =
- /* uart5_rx_m1 */
- <3 RK_PC5 10 &pcfg_pull_up>,
- /* uart5_tx_m1 */
- <3 RK_PC4 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart5m1_ctsn: uart5m1-ctsn {
- rockchip,pins =
- /* uart5m1_ctsn */
- <2 RK_PA2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m1_rtsn: uart5m1-rtsn {
- rockchip,pins =
- /* uart5m1_rtsn */
- <2 RK_PA3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m2_xfer: uart5m2-xfer {
- rockchip,pins =
- /* uart5_rx_m2 */
- <2 RK_PD4 10 &pcfg_pull_up>,
- /* uart5_tx_m2 */
- <2 RK_PD5 10 &pcfg_pull_up>;
- };
- };
-
- uart6 {
- /omit-if-no-ref/
- uart6m1_xfer: uart6m1-xfer {
- rockchip,pins =
- /* uart6_rx_m1 */
- <1 RK_PA0 10 &pcfg_pull_up>,
- /* uart6_tx_m1 */
- <1 RK_PA1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart6m1_ctsn: uart6m1-ctsn {
- rockchip,pins =
- /* uart6m1_ctsn */
- <1 RK_PA3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m1_rtsn: uart6m1-rtsn {
- rockchip,pins =
- /* uart6m1_rtsn */
- <1 RK_PA2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m2_xfer: uart6m2-xfer {
- rockchip,pins =
- /* uart6_rx_m2 */
- <1 RK_PD1 10 &pcfg_pull_up>,
- /* uart6_tx_m2 */
- <1 RK_PD0 10 &pcfg_pull_up>;
- };
- };
-
- uart7 {
- /omit-if-no-ref/
- uart7m1_xfer: uart7m1-xfer {
- rockchip,pins =
- /* uart7_rx_m1 */
- <3 RK_PC1 10 &pcfg_pull_up>,
- /* uart7_tx_m1 */
- <3 RK_PC0 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart7m1_ctsn: uart7m1-ctsn {
- rockchip,pins =
- /* uart7m1_ctsn */
- <3 RK_PC3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m1_rtsn: uart7m1-rtsn {
- rockchip,pins =
- /* uart7m1_rtsn */
- <3 RK_PC2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m2_xfer: uart7m2-xfer {
- rockchip,pins =
- /* uart7_rx_m2 */
- <1 RK_PB4 10 &pcfg_pull_up>,
- /* uart7_tx_m2 */
- <1 RK_PB5 10 &pcfg_pull_up>;
- };
- };
-
- uart8 {
- /omit-if-no-ref/
- uart8m0_xfer: uart8m0-xfer {
- rockchip,pins =
- /* uart8_rx_m0 */
- <4 RK_PB1 10 &pcfg_pull_up>,
- /* uart8_tx_m0 */
- <4 RK_PB0 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart8m0_ctsn: uart8m0-ctsn {
- rockchip,pins =
- /* uart8m0_ctsn */
- <4 RK_PB3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m0_rtsn: uart8m0-rtsn {
- rockchip,pins =
- /* uart8m0_rtsn */
- <4 RK_PB2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m1_xfer: uart8m1-xfer {
- rockchip,pins =
- /* uart8_rx_m1 */
- <3 RK_PA3 10 &pcfg_pull_up>,
- /* uart8_tx_m1 */
- <3 RK_PA2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart8m1_ctsn: uart8m1-ctsn {
- rockchip,pins =
- /* uart8m1_ctsn */
- <3 RK_PA5 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m1_rtsn: uart8m1-rtsn {
- rockchip,pins =
- /* uart8m1_rtsn */
- <3 RK_PA4 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8_xfer: uart8-xfer {
- rockchip,pins =
- /* uart8_rx_ */
- <4 RK_PB1 10 &pcfg_pull_up>;
- };
- };
-
- uart9 {
- /omit-if-no-ref/
- uart9m1_xfer: uart9m1-xfer {
- rockchip,pins =
- /* uart9_rx_m1 */
- <4 RK_PB5 10 &pcfg_pull_up>,
- /* uart9_tx_m1 */
- <4 RK_PB4 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m1_ctsn: uart9m1-ctsn {
- rockchip,pins =
- /* uart9m1_ctsn */
- <4 RK_PA1 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m1_rtsn: uart9m1-rtsn {
- rockchip,pins =
- /* uart9m1_rtsn */
- <4 RK_PA0 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m2_xfer: uart9m2-xfer {
- rockchip,pins =
- /* uart9_rx_m2 */
- <3 RK_PD4 10 &pcfg_pull_up>,
- /* uart9_tx_m2 */
- <3 RK_PD5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m2_ctsn: uart9m2-ctsn {
- rockchip,pins =
- /* uart9m2_ctsn */
- <3 RK_PD3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m2_rtsn: uart9m2-rtsn {
- rockchip,pins =
- /* uart9m2_rtsn */
- <3 RK_PD2 10 &pcfg_pull_none>;
- };
- };
-
- vop {
- /omit-if-no-ref/
- vop_pins: vop-pins {
- rockchip,pins =
- /* vop_post_empty */
- <1 RK_PA2 1 &pcfg_pull_none>;
- };
- };
-};
-
-/*
- * This part is edited handly.
- */
-&pinctrl {
- bt656 {
- /omit-if-no-ref/
- bt656_pins: bt656-pins {
- rockchip,pins =
- /* bt1120_clkout */
- <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d0 */
- <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d1 */
- <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d2 */
- <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d3 */
- <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d4 */
- <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d5 */
- <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d6 */
- <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d7 */
- <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
- };
- };
-
- gpio-func {
- /omit-if-no-ref/
- tsadc_gpio_func: tsadc-gpio-func {
- rockchip,pins =
- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi (nonexistent)
@@ -1,615 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/input/rk-input.h>
-#include <dt-bindings/display/drm_mipi_dsi.h>
-#include <dt-bindings/display/rockchip_vop.h>
-#include <dt-bindings/sensor-dev.h>
-
-/ {
- adc_keys: adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- vol-up-key {
- label = "volume up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <17000>;
- };
-
- vol-down-key {
- label = "volume down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <417000>;
- };
-
- menu-key {
- label = "menu";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <890000>;
- };
-
- back-key {
- label = "back";
- linux,code = <KEY_BACK>;
- press-threshold-microvolt = <1235000>;
- };
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <
- 0 20 20 21 21 22 22 23
- 23 24 24 25 25 26 26 27
- 27 28 28 29 29 30 30 31
- 31 32 32 33 33 34 34 35
- 35 36 36 37 37 38 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255
- >;
- default-brightness-level = <200>;
- };
-
- backlight_1: backlight_1 {
- compatible = "pwm-backlight";
- brightness-levels = <
- 0 20 20 21 21 22 22 23
- 23 24 24 25 25 26 26 27
- 27 28 28 29 29 30 30 31
- 31 32 32 33 33 34 34 35
- 35 36 36 37 37 38 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255
- >;
- default-brightness-level = <200>;
- };
-
- dp0_sound: dp0-sound {
- status = "disabled";
- compatible = "rockchip,hdmi";
- rockchip,card-name= "rockchip-dp0";
- rockchip,mclk-fs = <512>;
- rockchip,cpu = <&spdif_tx2>;
- rockchip,codec = <&dp0 1>;
- rockchip,jack-det;
- };
-
- hdmi0_sound: hdmi0-sound {
- status = "disabled";
- compatible = "rockchip,hdmi";
- rockchip,mclk-fs = <128>;
- rockchip,card-name = "rockchip-hdmi0";
- rockchip,cpu = <&i2s5_8ch>;
- rockchip,codec = <&hdmi0>;
- rockchip,jack-det;
- };
-
- spdif_tx1_dc: spdif-tx1-dc {
- status = "disabled";
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
- };
-
- spdif_tx1_sound: spdif-tx1-sound {
- status = "disabled";
- compatible = "simple-audio-card";
- simple-audio-card,name = "rockchip,spdif-tx1";
- simple-audio-card,cpu {
- sound-dai = <&spdif_tx1>;
- };
- simple-audio-card,codec {
- sound-dai = <&spdif_tx1_dc>;
- };
- };
-
- test-power {
- status = "okay";
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usbdcin: vcc5v0-usbdcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usbdcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usbdcin>;
- };
-};
-
-&av1d {
- status = "okay";
-};
-
-&av1d_mmu {
- status = "okay";
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
- mem-supply = <&vdd_cpu_lit_mem_s0>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- mem-supply = <&vdd_cpu_big0_mem_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
- mem-supply = <&vdd_cpu_big1_mem_s0>;
-};
-
-&dsi0 {
- status = "okay";
- //rockchip,lane-rate = <1000>;
- dsi0_panel: panel@0 {
- status = "okay";
- compatible = "innolux,afj101-ba2131";
- reg = <0>;
- backlight = <&backlight>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- panel_in_dsi: endpoint {
- remote-endpoint = <&dsi_out_panel>;
- };
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi_out_panel: endpoint {
- remote-endpoint = <&panel_in_dsi>;
- };
- };
- };
-
-};
-
-&dsi1 {
- status = "okay";
- //rockchip,lane-rate = <1000>;
- dsi1_panel: panel@0 {
- status = "okay";
- compatible = "innolux,afj101-ba2131";
- reg = <0>;
- backlight = <&backlight_1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- panel_in_dsi1: endpoint {
- remote-endpoint = <&dsi1_out_panel>;
- };
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi1_out_panel: endpoint {
- remote-endpoint = <&panel_in_dsi1>;
- };
- };
- };
-
-};
-
-&gpu {
- mali-supply = <&vdd_gpu_s0>;
- mem-supply = <&vdd_gpu_mem_s0>;
- status = "okay";
-};
-
-&i2s0_8ch {
- status = "okay";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
-};
-
-&iep {
- status = "okay";
-};
-
-&iep_mmu {
- status = "okay";
-};
-
-&jpegd {
- status = "okay";
-};
-
-&jpegd_mmu {
- status = "okay";
-};
-
-&jpege_ccu {
- status = "okay";
-};
-
-&jpege0 {
- status = "okay";
-};
-
-&jpege0_mmu {
- status = "okay";
-};
-
-&jpege1 {
- status = "okay";
-};
-
-&jpege1_mmu {
- status = "okay";
-};
-
-&jpege2 {
- status = "okay";
-};
-
-&jpege2_mmu {
- status = "okay";
-};
-
-&jpege3 {
- status = "okay";
-};
-
-&jpege3_mmu {
- status = "okay";
-};
-
-&mpp_srv {
- status = "okay";
-};
-
-&rga3_core0 {
- status = "okay";
-};
-
-&rga3_0_mmu {
- status = "okay";
-};
-
-&rga3_core1 {
- status = "okay";
-};
-
-&rga3_1_mmu {
- status = "okay";
-};
-
-&rga2 {
- status = "okay";
-};
-
-&rknpu {
- rknpu-supply = <&vdd_npu_s0>;
- mem-supply = <&vdd_npu_mem_s0>;
- status = "okay";
-};
-
-&rknpu_mmu {
- status = "okay";
-};
-
-&rkvdec_ccu {
- status = "okay";
-};
-
-&rkvdec0 {
- status = "okay";
-};
-
-&rkvdec0_mmu {
- status = "okay";
-};
-
-&rkvdec1 {
- status = "okay";
-};
-
-&rkvdec1_mmu {
- status = "okay";
-};
-
-&rkvenc_ccu {
- status = "okay";
-};
-
-&rkvenc0 {
- status = "okay";
-};
-
-&rkvenc0_mmu {
- status = "okay";
-};
-
-&rkvenc1 {
- status = "okay";
-};
-
-&rkvenc1_mmu {
- status = "okay";
-};
-
-&rockchip_suspend {
- status = "okay";
- rockchip,sleep-debug-en = <1>;
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vcc_1v8_s0>;
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "disabled";
-};
-
-&sdmmc {
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_sd_s0>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy0_otg {
- status = "okay";
-};
-
-&u2phy2_host {
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdp_phy0 {
- status = "okay";
-};
-
-&usbdp_phy0_dp {
- status = "okay";
-};
-
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&usbhost3_0 {
- status = "okay";
-};
-
-&usbhost_dwc3_0 {
- status = "okay";
-};
-
-&vdpu {
- status = "okay";
-};
-
-&vdpu_mmu {
- status = "okay";
-};
-
-&vop {
- status = "okay";
- disable-win-move;
- assigned-clocks = <&cru ACLK_VOP>;
- assigned-clock-rates = <800000000>;
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vepu {
- status = "okay";
-};
-
-/* vp0 & vp1 splice for 8K output */
-&vp0 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART0>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER0>;
-};
-
-&vp1 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART1>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER1>;
-};
-
-&vp2 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART2>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER2>;
-};
-
-&vp3 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART3>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER3>;
-};
-
-/* Fix tty terminal out of screen, and most dclk of resolutions was not supported in hdmiphy clock from parent clock by default */
-&display_subsystem {
- clocks = <&hdptxphy_hdmi_clk0>;
- clock-names = "hdmi0_phy_pll";
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi (nonexistent)
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-/ {
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdhci;
- mmc2 = &sdio;
- };
-
- //chosen: chosen {
- // bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait";
- //};
-
- cspmu: cspmu@fd10c000 {
- compatible = "rockchip,cspmu";
- reg = <0x0 0xfd10c000 0x0 0x1000>,
- <0x0 0xfd10d000 0x0 0x1000>,
- <0x0 0xfd10e000 0x0 0x1000>,
- <0x0 0xfd10f000 0x0 0x1000>,
- <0x0 0xfd12c000 0x0 0x1000>,
- <0x0 0xfd12d000 0x0 0x1000>,
- <0x0 0xfd12e000 0x0 0x1000>,
- <0x0 0xfd12f000 0x0 0x1000>;
- };
-
- debug: debug@fd104000 {
- compatible = "rockchip,debug";
- reg = <0x0 0xfd104000 0x0 0x1000>,
- <0x0 0xfd105000 0x0 0x1000>,
- <0x0 0xfd106000 0x0 0x1000>,
- <0x0 0xfd107000 0x0 0x1000>,
- <0x0 0xfd124000 0x0 0x1000>,
- <0x0 0xfd125000 0x0 0x1000>,
- <0x0 0xfd126000 0x0 0x1000>,
- <0x0 0xfd127000 0x0 0x1000>;
- };
-
- fiq_debugger: fiq-debugger {
- compatible = "rockchip,fiq-debugger";
- rockchip,serial-id = <2>;
- rockchip,wake-irq = <0>;
- /* If enable uart uses irq instead of fiq */
- rockchip,irq-mode-enable = <1>;
- rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
- interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
- };
-
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- //status = "disabled";
- };
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 (8 * 0x100000)>;
- linux,cma-default;
- };
-
- drm_logo: drm-logo@0 {
- compatible = "rockchip,drm-logo";
- reg = <0x0 0x0 0x0 0x0>;
- };
-
- drm_cubic_lut: drm-cubic-lut@0 {
- compatible = "rockchip,drm-cubic-lut";
- reg = <0x0 0x0 0x0 0x0>;
- };
-
- ramoops: ramoops@110000 {
- compatible = "ramoops";
- reg = <0x0 0x110000 0x0 0xf0000>;
- record-size = <0x20000>;
- console-size = <0x80000>;
- ftrace-size = <0x00000>;
- pmsg-size = <0x50000>;
- };
- };
-};
-
-&display_subsystem {
- memory-region = <&drm_logo>;
- memory-region-names = "drm-logo";
-};
-
-&dfi {
- status = "okay";
-};
-
-&dmc {
- status = "disabled";
- center-supply = <&vdd_ddr_s0>;
- mem-supply = <&vdd_log_s0>;
-};
-
-&rng {
- status = "okay";
-};
-
-&rockchip_suspend {
-
- rockchip,sleep-mode-config = <
- (0
- | RKPM_SLP_ARMOFF_DDRPD
- | RKPM_SLP_PMU_PMUALIVE_32K
- | RKPM_SLP_PMU_DIS_OSC
- | RKPM_SLP_32K_EXT
- | RKPM_SLP_PMU_DBG
- )
- >;
-};
-
-&vdd_log_s0 {
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi (nonexistent)
@@ -1,201 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-&csi2_dphy0_hw {
- status = "disabled";
-};
-
-&csi2_dphy0 {
- status = "disabled";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_ucam0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ov13850_out2>;
- data-lanes = <1 2>;
- };
-
- mipi_in_ucam1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ov13855_out2>;
- data-lanes = <1 2>;
- };
-
- mipi_in_ucam2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&gc5035_out>;
- data-lanes = <1 2>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- csidphy0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi2_csi2_input>;
- };
- };
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m0_xfer>;
-
- vm149c_p1: vm149c-p1@c {
- compatible = "silicon touch,vm149c";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "back";
- };
-
- ov13850_1: ov13850-1@10 {
- compatible = "ovti,ov13850";
- status = "disabled";
- reg = <0x10>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim1_camera3_clk>;
- reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "back";
- rockchip,camera-module-name = "CMK-CT0116";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&vm149c_p1>;
- port {
- ov13850_out2: endpoint {
- remote-endpoint = <&mipi_in_ucam0>;
- data-lanes = <1 2>;
- };
- };
- };
-
- dw9714_p1: dw9714-p1@c {
- compatible = "dongwoon,dw9714";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <0>;
- rockchip,vcm-start-current = <10>;
- rockchip,vcm-rated-current = <85>;
- rockchip,vcm-step-mode = <5>;
- rockchip,camera-module-facing = "back";
- };
-
- ov13855_1: ov13855-1@36 {
- compatible = "ovti,ov13855";
- status = "disabled";
- reg = <0x36>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim1_camera3_clk>;
- reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "back";
- rockchip,camera-module-name = "CMK-OT2016-FV1";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&dw9714_p1>;
- port {
- ov13855_out2: endpoint {
- remote-endpoint = <&mipi_in_ucam1>;
- data-lanes = <1 2>;
- };
- };
- };
-
- gc5035: gc5035@37 {
- compatible = "galaxycore,gc5035";
- status = "okay";
- reg = <0x37>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim1_camera3_clk>;
-
- //reset pin control by hardware,used this pin switch to mipi input
- //0->FRONT camera, 1->REAR camera
- reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "front";
- rockchip,camera-module-name = "XHG-RKX11F-V5";
- rockchip,camera-module-lens-name = "HR232H65";
- port {
- gc5035_out: endpoint {
- remote-endpoint = <&mipi_in_ucam2>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
-&mipi2_csi2 {
- status = "disabled";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi2_csi2_input: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csidphy0_out>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi2_csi2_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&cif_mipi_in2>;
- };
- };
- };
-};
-
-&rkcif_mipi_lvds2 {
- status = "disabled";
- port {
- cif_mipi_in2: endpoint {
- remote-endpoint = <&mipi2_csi2_output>;
- };
- };
-};
-
-&rkcif_mipi_lvds2_sditf {
- status = "disabled";
- port {
- mipi2_lvds_sditf: endpoint {
- remote-endpoint = <&isp0_vir1>;
- };
- };
-};
-
-&rkisp0_vir1 {
- status = "disabled";
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- isp0_vir1: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi2_lvds_sditf>;
- };
- };
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi (nonexistent)
@@ -1,381 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include "dt-bindings/usb/pd.h"
-#include "rk3588s.dtsi"
-#include "rk3588s-orangepi.dtsi"
-#include "rk3588-rk806-single.dtsi"
-
-/ {
- combophy_avdd0v85: combophy-avdd0v85 {
- compatible = "regulator-fixed";
- regulator-name = "combophy_avdd0v85";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- vin-supply = <&vdd_0v85_s0>;
- };
-
- combophy_avdd1v8: combophy-avdd1v8 {
- compatible = "regulator-fixed";
- regulator-name = "combophy_avdd1v8";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&avcc_1v8_s0>;
- };
-
- es8388_sound: es8388-sound {
- status = "okay";
- compatible = "rockchip,multicodecs-card";
- rockchip,card-name = "rockchip-es8388";
- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- io-channels = <&saradc 3>;
- io-channel-names = "adc-detect";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
- rockchip,format = "i2s";
- rockchip,mclk-fs = <256>;
- rockchip,cpu = <&i2s1_8ch>;
- rockchip,codec = <&es8388>;
- rockchip,audio-routing =
- "Headphone", "LOUT1",
- "Headphone", "ROUT1",
- "Headphone", "Headphone Power",
- "Headphone", "Headphone Power",
- "LINPUT1", "Main Mic",
- "LINPUT2", "Main Mic",
- "RINPUT1", "Headset Mic",
- "RINPUT2", "Headset Mic";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det>;
- play-pause-key {
- label = "playpause";
- linux,code = <KEY_PLAYPAUSE>;
- press-threshold-microvolt = <2000>;
- };
- };
-
- wireless_bluetooth: wireless-bluetooth {
- compatible = "bluetooth-platdata";
- clocks = <&hym8563>;
- clock-names = "ext_clock";
- uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "rts_gpio";
- pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>;
- pinctrl-1 = <&uart9_gpios>;
- BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
- BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
- status = "disabled";
- };
-
- wireless_wlan: wireless-wlan {
- compatible = "wlan-platdata";
- wifi_chip_type = "ap6275p";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
- WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
- status = "disabled";
- };
-
- vbus5v0_typec: vbus5v0-typec {
- compatible = "regulator-fixed";
- regulator-name = "vbus5v0_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_usb>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- };
-};
-
-&pwm6 {
- status = "okay";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm6m0_pins>;
-};
-
-&pwm2 {
- status = "okay";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2m0_pins>;
-};
-
-&backlight_1 {
- pwms = <&pwm6 0 25000 0>;
- status = "okay";
-};
-
-&backlight {
- pwms = <&pwm2 0 25000 0>;
- status = "okay";
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&dp0 {
- status = "okay";
-};
-
-&dp0_in_vp1 {
- status = "okay";
-};
-
-&dp0_in_vp2 {
- status = "disabled";
-};
-
-&dp0_sound{
- status = "okay";
-};
-
-&spdif_tx2{
- status = "okay";
-};
-
-&mipi_dcphy0 {
- status = "okay";
-};
-
-&mipi_dcphy1 {
- status = "okay";
-};
-
-&i2c6 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6m3_xfer>;
-
- es8388: es8388@10 {
- status = "okay";
- #sound-dai-cells = <0>;
- compatible = "everest,es8388", "everest,es8323";
- reg = <0x10>;
- clocks = <&cru I2S1_8CH_MCLKOUT>;
- clock-names = "mclk";
- assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_mclk>;
- };
-
- usbc0: fusb302@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&usbc0_int>;
- vbus-supply = <&vbus5v0_typec>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_role_sw: endpoint@0 {
- remote-endpoint = <&dwc3_0_role_switch>;
- };
- };
- };
-
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
- power-role = "dual";
- try-power-role = "sink";
- op-sink-microwatt = <1000000>;
- sink-pdos =
- <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-
- altmodes {
- #address-cells = <1>;
- #size-cells = <0>;
-
- altmode@0 {
- reg = <0>;
- svid = <0xff01>;
- vdo = <0xffffffff>;
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_orien_sw: endpoint {
- remote-endpoint = <&usbdp_phy0_orientation_switch>;
- };
- };
-
- port@1 {
- reg = <1>;
- dp_altmode_mux: endpoint {
- remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
- };
- };
- };
- };
- };
-
- hym8563: hym8563@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&pcie2x1l1 {
- status = "disabled";
-};
-
-&pcie2x1l2 {
- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- rockchip,skip-scan-in-resume;
- status = "disabled";
-};
-
-&pinctrl {
- sata {
- sata_reset:sata-reset{
- rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- lcd {
- lcd0_rst_gpio: lcd0-rst-gpio {
- rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- lcd1_rst_gpio: lcd1-rst-gpio {
- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- usbc0_int: usbc0-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wireless-bluetooth {
- uart9_gpios: uart9-gpios {
- rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_gpio: bt-gpio {
- rockchip,pins =
- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wireless-wlan {
- wifi_host_wake_irq: wifi-host-wake-irq {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- wifi_poweren_gpio: wifi-poweren-gpio {
- rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&u2phy0_otg {
- rockchip,typec-vbus-det;
- status = "okay";
-};
-
-&uart9 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
-};
-
-&usbdp_phy0 {
- orientation-switch;
- svid = <0xff01>;
- sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
- sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- usbdp_phy0_orientation_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_orien_sw>;
- };
-
- usbdp_phy0_dp_altmode_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dp_altmode_mux>;
- };
- };
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
- usb-role-switch;
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- dwc3_0_role_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_role_sw>;
- };
- };
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&usbhost3_0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbhost_dwc3_0 {
- status = "okay";
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi (nonexistent)
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include "rk3588-linux.dtsi"
-
-&CPU_SLEEP {
- status = "disabled";
-};
-
-&cluster0_opp_table {
- /delete-node/ opp-408000000;
- /delete-node/ opp-600000000;
- /delete-node/ opp-816000000;
- /delete-node/ opp-1008000000;
-};
-
-&cluster1_opp_table {
- /delete-node/ opp-408000000;
- /delete-node/ opp-600000000;
- /delete-node/ opp-816000000;
- /delete-node/ opp-1008000000;
- /delete-node/ opp-2256000000;
- /delete-node/ opp-2304000000;
- /delete-node/ opp-2352000000;
- /delete-node/ opp-2400000000;
-};
-
-&cluster2_opp_table {
- /delete-node/ opp-408000000;
- /delete-node/ opp-600000000;
- /delete-node/ opp-816000000;
- /delete-node/ opp-1008000000;
- /delete-node/ opp-2256000000;
- /delete-node/ opp-2304000000;
- /delete-node/ opp-2352000000;
- /delete-node/ opp-2400000000;
-};
-
-&dfi {
- status = "disabled";
-};
-
-&dmc {
- status = "disabled";
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi (nonexistent)
@@ -1,396 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
-
- rk806single: rk806single@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default", "pmic-power-off";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- pinctrl-1 = <&rk806_dvs1_pwrdn>;
-
- /* 2800mv-3500mv */
- low_voltage_threshold = <3000>;
- /* 2700mv-3400mv */
- shutdown_voltage_threshold = <2700>;
- /* 140 160 */
- shutdown_temperture_threshold = <160>;
- hotdie_temperture_threshold = <115>;
-
- /* 0: restart PMU;
- * 1: reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode;
- * 2: Reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode,
- * and simultaneously pull down the RESETB PIN for 5mS before releasing
- */
- pmic-reset-func = <1>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- pwrkey {
- status = "okay";
- };
-
- pinctrl_rk806: pinctrl_rk806 {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: rk806_dvs1_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs1_slp: rk806_dvs1_slp {
- pins = "gpio_pwrctrl1";
- function = "pin_fun1";
- };
-
- rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
- pins = "gpio_pwrctrl1";
- function = "pin_fun2";
- };
-
- rk806_dvs1_rst: rk806_dvs1_rst {
- pins = "gpio_pwrctrl1";
- function = "pin_fun3";
- };
-
- rk806_dvs2_null: rk806_dvs2_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_slp: rk806_dvs2_slp {
- pins = "gpio_pwrctrl2";
- function = "pin_fun1";
- };
-
- rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
- pins = "gpio_pwrctrl2";
- function = "pin_fun2";
- };
-
- rk806_dvs2_rst: rk806_dvs2_rst {
- pins = "gpio_pwrctrl2";
- function = "pin_fun3";
- };
-
- rk806_dvs2_dvs: rk806_dvs2_dvs {
- pins = "gpio_pwrctrl2";
- function = "pin_fun4";
- };
-
- rk806_dvs2_gpio: rk806_dvs2_gpio {
- pins = "gpio_pwrctrl2";
- function = "pin_fun5";
- };
-
- rk806_dvs3_null: rk806_dvs3_null {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- rk806_dvs3_slp: rk806_dvs3_slp {
- pins = "gpio_pwrctrl3";
- function = "pin_fun1";
- };
-
- rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
- pins = "gpio_pwrctrl3";
- function = "pin_fun2";
- };
-
- rk806_dvs3_rst: rk806_dvs3_rst {
- pins = "gpio_pwrctrl3";
- function = "pin_fun3";
- };
-
- rk806_dvs3_dvs: rk806_dvs3_dvs {
- pins = "gpio_pwrctrl3";
- function = "pin_fun4";
- };
-
- rk806_dvs3_gpio: rk806_dvs3_gpio {
- pins = "gpio_pwrctrl3";
- function = "pin_fun5";
- };
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-init-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: DCDC_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: DCDC_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: DCDC_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: DCDC_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: DCDC_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: DCDC_REG10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: PLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "avcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: PLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: PLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-name = "avdd_1v2_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: PLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: PLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: PLDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: NLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: NLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: NLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <837500>;
- regulator-max-microvolt = <837500>;
- regulator-name = "avdd_0v75_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: NLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: NLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588m.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588m.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588m.dtsi (nonexistent)
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include "rk3588.dtsi"
-
-&cluster0_opp_table {
- /delete-node/ opp-1800000000;
-
- opp-1704000000 {
- opp-supported-hw = <0x02 0xffff>;
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <900000 900000 950000>,
- <900000 900000 950000>;
- opp-microvolt-L1 = <887500 887500 950000>,
- <887500 887500 950000>;
- opp-microvolt-L2 = <875000 875000 950000>,
- <875000 875000 950000>;
- opp-microvolt-L3 = <862500 862500 950000>,
- <862500 862500 950000>;
- opp-microvolt-L4 = <850000 850000 950000>,
- <850000 850000 950000>;
- opp-microvolt-L5 = <837500 837500 950000>,
- <837500 837500 950000>;
- opp-microvolt-L6 = <825000 825000 950000>,
- <825000 825000 950000>;
- clock-latency-ns = <40000>;
- };
-};
-
-&cluster1_opp_table {
- /delete-node/ opp-2208000000;
- /delete-node/ opp-2256000000;
- /delete-node/ opp-2304000000;
- /delete-node/ opp-2352000000;
- /delete-node/ opp-2400000000;
-};
-
-&cluster2_opp_table {
- /delete-node/ opp-2208000000;
- /delete-node/ opp-2256000000;
- /delete-node/ opp-2304000000;
- /delete-node/ opp-2352000000;
- /delete-node/ opp-2400000000;
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi (nonexistent)
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-&csi2_dcphy0 {
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_cam0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ov13850_out>;
- data-lanes = <1 2>;
- };
-
- mipi_in_cam1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ov13855_out>;
- data-lanes = <1 2>;
- };
- };
-
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- csidcphy0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi0_csi2_input>;
- };
- };
- };
-};
-
-&i2c7 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7m0_xfer>;
-
- vm149c_p2: vm149c-p2@c {
- compatible = "silicon touch,vm149c";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "back";
- };
-
- ov13850_2: ov13850-2@10 {
- compatible = "ovti,ov13850";
- status = "disabled";
- reg = <0x10>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
- clock-names = "xvclk";
- power-domains = <&power RK3588_PD_VI>;
- pinctrl-names = "default";
- pinctrl-0 = <&mipim0_camera4_clk>;
- rockchip,grf = <&sys_grf>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "back";
- rockchip,camera-module-name = "CMK-CT0116";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&vm149c_p2>;
- port {
- ov13850_out: endpoint {
- remote-endpoint = <&mipi_in_cam0>;
- data-lanes = <1 2>;
- };
- };
- };
-
- dw9714_p2: dw9714-p2@c {
- compatible = "dongwoon,dw9714";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <0>;
- rockchip,vcm-start-current = <10>;
- rockchip,vcm-rated-current = <85>;
- rockchip,vcm-step-mode = <5>;
- rockchip,camera-module-facing = "back";
- };
-
- ov13855_2: ov13855-2@36 {
- compatible = "ovti,ov13855";
- status = "disabled";
- reg = <0x36>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
- clock-names = "xvclk";
- power-domains = <&power RK3588_PD_VI>;
- pinctrl-names = "default";
- pinctrl-0 = <&mipim0_camera4_clk>;
- rockchip,grf = <&sys_grf>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "back";
- rockchip,camera-module-name = "CMK-OT2016-FV1";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&dw9714_p2>;
- port {
- ov13855_out: endpoint {
- remote-endpoint = <&mipi_in_cam1>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
-&mipi0_csi2 {
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi0_csi2_input: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csidcphy0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi0_csi2_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&cif_mipi_in0>;
- };
- };
- };
-};
-
-&rkcif_mipi_lvds {
- status = "disabled";
-
- port {
- cif_mipi_in0: endpoint {
- remote-endpoint = <&mipi0_csi2_output>;
- };
- };
-};
-
-&rkcif_mipi_lvds_sditf {
- status = "disabled";
-
- port {
- mipi_lvds_sditf: endpoint {
- remote-endpoint = <&isp1_in1>;
- };
- };
-};
-
-&rkisp0_vir0 {
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- isp1_in1: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi_lvds_sditf>;
- };
- };
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi (nonexistent)
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-&csi2_dphy0_hw {
- status = "disabled";
-};
-
-&csi2_dphy0 {
- status = "disabled";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_ucam0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ov13850_out2>;
- data-lanes = <1 2>;
- };
-
- mipi_in_ucam1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ov13855_out2>;
- data-lanes = <1 2>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- csidphy0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi2_csi2_input>;
- };
- };
- };
-};
-
-&i2c7 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7m0_xfer>;
-
- vm149c_p1: vm149c-p1@c {
- compatible = "silicon touch,vm149c";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "back";
- };
-
- ov13850_1: ov13850-1@10 {
- compatible = "ovti,ov13850";
- status = "disabled";
- reg = <0x10>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim0_camera3_clk>;
- reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "back";
- rockchip,camera-module-name = "CMK-CT0116";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&vm149c_p1>;
- port {
- ov13850_out2: endpoint {
- remote-endpoint = <&mipi_in_ucam0>;
- data-lanes = <1 2>;
- };
- };
- };
-
- dw9714_p1: dw9714-p1@c {
- compatible = "dongwoon,dw9714";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <0>;
- rockchip,vcm-start-current = <10>;
- rockchip,vcm-rated-current = <85>;
- rockchip,vcm-step-mode = <5>;
- rockchip,camera-module-facing = "back";
- };
-
- ov13855_1: ov13855-1@36 {
- compatible = "ovti,ov13855";
- status = "disabled";
- reg = <0x36>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim0_camera3_clk>;
- reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "back";
- rockchip,camera-module-name = "CMK-OT2016-FV1";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&dw9714_p1>;
- port {
- ov13855_out2: endpoint {
- remote-endpoint = <&mipi_in_ucam1>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
-&mipi2_csi2 {
- status = "disabled";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi2_csi2_input: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csidphy0_out>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi2_csi2_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&cif_mipi_in2>;
- };
- };
- };
-};
-
-&rkcif_mipi_lvds2 {
- status = "disabled";
- port {
- cif_mipi_in2: endpoint {
- remote-endpoint = <&mipi2_csi2_output>;
- };
- };
-};
-
-&rkcif_mipi_lvds2_sditf {
- status = "disabled";
- port {
- mipi2_lvds_sditf: endpoint {
- remote-endpoint = <&isp0_vir1>;
- };
- };
-};
-
-&rkisp0_vir1 {
- status = "disabled";
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- isp0_vir1: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi2_lvds_sditf>;
- };
- };
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi.dtsi (nonexistent)
@@ -1,651 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/input/rk-input.h>
-#include <dt-bindings/display/drm_mipi_dsi.h>
-#include <dt-bindings/display/rockchip_vop.h>
-#include <dt-bindings/sensor-dev.h>
-
-/ {
- adc_keys: adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- vol-up-key {
- label = "volume up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <17000>;
- };
-
- vol-down-key {
- label = "volume down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <417000>;
- };
-
- menu-key {
- label = "menu";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <890000>;
- };
-
- back-key {
- label = "back";
- linux,code = <KEY_BACK>;
- press-threshold-microvolt = <1235000>;
- };
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <
- 0 20 20 21 21 22 22 23
- 23 24 24 25 25 26 26 27
- 27 28 28 29 29 30 30 31
- 31 32 32 33 33 34 34 35
- 35 36 36 37 37 38 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255
- >;
- default-brightness-level = <200>;
- };
-
- dp0_sound: dp0-sound {
- status = "disabled";
- compatible = "rockchip,hdmi";
- rockchip,card-name= "rockchip,dp0";
- rockchip,mclk-fs = <512>;
- rockchip,cpu = <&spdif_tx2>;
- rockchip,codec = <&dp0 1>;
- rockchip,jack-det;
- };
-
- dp1_sound: dp1-sound {
- status = "disabled";
- compatible = "rockchip,hdmi";
- rockchip,card-name= "rockchip,dp1";
- rockchip,mclk-fs = <512>;
- rockchip,cpu = <&spdif_tx5>;
- rockchip,codec = <&dp1 1>;
- rockchip,jack-det;
- };
-
- hdmi0_sound: hdmi0-sound {
- status = "disabled";
- compatible = "rockchip,hdmi";
- rockchip,mclk-fs = <128>;
- rockchip,card-name = "rockchip-hdmi0";
- rockchip,cpu = <&i2s5_8ch>;
- rockchip,codec = <&hdmi0>;
- rockchip,jack-det;
- };
-
- hdmi1_sound: hdmi1-sound {
- status = "disabled";
- compatible = "rockchip,hdmi";
- rockchip,mclk-fs = <128>;
- rockchip,card-name = "rockchip-hdmi1";
- rockchip,cpu = <&i2s6_8ch>;
- rockchip,codec = <&hdmi1>;
- rockchip,jack-det;
- };
-
- spdif_tx1_dc: spdif-tx1-dc {
- status = "disabled";
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
- };
-
- spdif_tx1_sound: spdif-tx1-sound {
- status = "disabled";
- compatible = "simple-audio-card";
- simple-audio-card,name = "rockchip,spdif-tx1";
- simple-audio-card,cpu {
- sound-dai = <&spdif_tx1>;
- };
- simple-audio-card,codec {
- sound-dai = <&spdif_tx1_dc>;
- };
- };
-
- test-power {
- status = "disabled";
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usbdcin: vcc5v0-usbdcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usbdcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usbdcin>;
- };
-
- spi2: spi@feb20000 {
- compatible = "rockchip,rk3066-spi";
- reg = <0x0 0xfeb20000 0x0 0x1000>;
- interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac1 15>, <&dmac1 16>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <2>;
- status = "okay";
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sd_s0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pwr>;
- enable-active-low;
- };
-};
-
-&av1d_mmu {
- status = "okay";
-};
-
-&dsi0 {
- status = "disabled";
- //rockchip,lane-rate = <1000>;
- dsi0_panel: panel@0 {
- status = "disabled";
- compatible = "innolux,afj101-ba2131";
- reg = <0>;
- backlight = <&backlight>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- panel_in_dsi: endpoint {
- remote-endpoint = <&dsi_out_panel>;
- };
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi_out_panel: endpoint {
- remote-endpoint = <&panel_in_dsi>;
- };
- };
- };
-};
-
-&dsi1 {
- status = "disabled";
- //rockchip,lane-rate = <1000>;
- dsi1_panel: panel@0 {
- status = "disabled";
- compatible = "innolux,afj101-ba2131";
- reg = <0>;
- backlight = <&backlight>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- panel_in_dsi1: endpoint {
- remote-endpoint = <&dsi1_out_panel>;
- };
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi1_out_panel: endpoint {
- remote-endpoint = <&panel_in_dsi1>;
- };
- };
- };
-};
-
-&gpu {
- mali-supply = <&vdd_gpu_s0>;
- mem-supply = <&vdd_gpu_mem_s0>;
- status = "okay";
-};
-
-&i2s0_8ch {
- status = "okay";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
-};
-
-&iep {
- status = "okay";
-};
-
-&iep_mmu {
- status = "okay";
-};
-
-&jpegd {
- status = "okay";
-};
-
-&jpegd_mmu {
- status = "okay";
-};
-
-&jpege_ccu {
- status = "okay";
-};
-&jpege0 {
- status = "okay";
-};
-
-&jpege0_mmu {
- status = "okay";
-};
-
-&jpege1 {
- status = "okay";
-};
-
-&jpege1_mmu {
- status = "okay";
-};
-
-&jpege2 {
- status = "okay";
-};
-
-&jpege2_mmu {
- status = "okay";
-};
-
-&jpege3 {
- status = "okay";
-};
-
-&jpege3_mmu {
- status = "okay";
-};
-
-&mpp_srv {
- status = "okay";
-};
-
-&rga3_core0 {
- status = "okay";
-};
-
-&rga3_0_mmu {
- status = "okay";
-};
-
-&rga3_core1 {
- status = "okay";
-};
-
-&rga3_1_mmu {
- status = "okay";
-};
-
-&rga2 {
- status = "okay";
-};
-
-&rknpu {
- rknpu-supply = <&vdd_npu_s0>;
- mem-supply = <&vdd_npu_mem_s0>;
- status = "okay";
-};
-
-&rknpu_mmu {
- status = "okay";
-};
-
-&rkvdec_ccu {
- status = "okay";
-};
-
-&rkvdec0 {
- status = "okay";
-};
-
-&rkvdec0_mmu {
- status = "okay";
-};
-
-&rkvdec1 {
- status = "okay";
-};
-
-&rkvdec1_mmu {
- status = "okay";
-};
-
-&rkvenc_ccu {
- status = "okay";
-};
-
-&rkvenc0 {
- status = "okay";
-};
-
-&rkvenc0_mmu {
- status = "okay";
-};
-
-&rkvenc1 {
- status = "okay";
-};
-
-&rkvenc1_mmu {
- status = "okay";
-};
-
-&rockchip_suspend {
- status = "okay";
- rockchip,sleep-debug-en = <1>;
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vcc_1v8_s0>;
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "disabled";
-};
-
-&sdmmc {
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_sd_s0>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy1 {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy0_otg {
- rockchip,typec-vbus-det;
- status = "okay";
-};
-
-&u2phy1_otg {
- status = "okay";
-};
-
-&u2phy2_host {
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdp_phy0 {
- status = "okay";
-};
-
-&usbdp_phy0_dp {
- status = "okay";
-};
-
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
-&usbdp_phy1 {
- status = "okay";
-};
-
-&usbdp_phy1_dp {
- status = "okay";
-};
-
-&usbdp_phy1_u3 {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&usbhost3_0 {
- status = "okay";
-};
-
-&usbhost_dwc3_0 {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
-};
-
-&vdpu {
- status = "okay";
-};
-
-&vdpu_mmu {
- status = "okay";
-};
-
-&vepu {
- status = "okay";
-};
-
-&vop {
- status = "okay";
- disable-win-move;
- assigned-clocks = <&cru ACLK_VOP>;
- assigned-clock-rates = <800000000>;
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-/* vp0 & vp1 splice for 8K output */
-&vp0 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART0>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER0>;
-};
-
-&vp1 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART1>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER1>;
-};
-
-&vp2 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART2>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER2>;
-};
-
-&vp3 {
- cursor-win-id=<ROCKCHIP_VOP2_ESMART3>;
- rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
- rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER3>;
-};
-
-&display_subsystem {
- clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
- clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
- mem-supply = <&vdd_cpu_lit_mem_s0>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- mem-supply = <&vdd_cpu_big0_mem_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
- mem-supply = <&vdd_cpu_big1_mem_s0>;
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi (nonexistent)
@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-&csi2_dcphy1 {
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_dcphy0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ov13850_out1>;
- data-lanes = <1 2>;
- };
-
- mipi_in_dcphy1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ov13855_out1>;
- data-lanes = <1 2>;
- };
- };
-
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- csidcphy1_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi1_csi2_input>;
- };
- };
- };
-};
-
-&i2c2 {
- status = "okay";
-
- vm149cp1: vm149c@c {
- compatible = "silicon touch,vm149c";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "front";
- };
-
- ov13850_3: ov13850@10 {
- compatible = "ovti,ov13850";
- status = "disabled";
- reg = <0x10>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim0_camera4_clk>;
- rockchip,grf = <&sys_grf>;
- reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "front";
- rockchip,camera-module-name = "CMK-CT0116";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&vm149cp1>;
- port {
- ov13850_out1: endpoint {
- remote-endpoint = <&mipi_in_dcphy0>;
- data-lanes = <1 2>;
- };
- };
- };
-
- dw9714: dw9714@c {
- compatible = "dongwoon,dw9714";
- status = "disabled";
- reg = <0x0c>;
- rockchip,camera-module-index = <0>;
- rockchip,vcm-start-current = <10>;
- rockchip,vcm-rated-current = <85>;
- rockchip,vcm-step-mode = <5>;
- rockchip,camera-module-facing = "front";
- };
-
- ov13855_3: ov13855@36 {
- compatible = "ovti,ov13855";
- status = "disabled";
- reg = <0x36>;
- clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
- clock-names = "xvclk";
- pinctrl-names = "default";
- pinctrl-0 = <&mipim0_camera4_clk>;
- rockchip,grf = <&sys_grf>;
- reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "front";
- rockchip,camera-module-name = "CMK-OT2016-FV1";
- rockchip,camera-module-lens-name = "default";
- lens-focus = <&dw9714>;
- port {
- ov13855_out1: endpoint {
- remote-endpoint = <&mipi_in_dcphy1>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
-&mipi1_csi2 {
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi1_csi2_input: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csidcphy1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi1_csi2_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&cif_mipi_in1>;
- };
- };
- };
-};
-
-&rkcif_mipi_lvds1 {
- status = "disabled";
-
- port {
- cif_mipi_in1: endpoint {
- remote-endpoint = <&mipi1_csi2_output>;
- };
- };
-};
-
-&rkcif_mipi_lvds1_sditf {
- status = "disabled";
-
- port {
- mipi1_lvds_sditf: endpoint {
- remote-endpoint = <&isp1_in0>;
- };
- };
-};
-
-&rkisp1_vir0 {
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- isp1_in0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi1_lvds_sditf>;
- };
- };
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s.dtsi (nonexistent)
@@ -1,5896 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rk3588-cru.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/power/rk3588-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/soc/rockchip-system-status.h>
-#include <dt-bindings/suspend/rockchip-rk3588.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- compatible = "rockchip,rk3588";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- csi2dcphy0 = &csi2_dcphy0;
- csi2dcphy1 = &csi2_dcphy1;
- csi2dphy0 = &csi2_dphy0;
- csi2dphy1 = &csi2_dphy1;
- csi2dphy2 = &csi2_dphy2;
- dsi0 = &dsi0;
- dsi1 = &dsi1;
- ethernet1 = &gmac1;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c7;
- i2c8 = &i2c8;
- rkcif_mipi_lvds0= &rkcif_mipi_lvds;
- rkcif_mipi_lvds1= &rkcif_mipi_lvds1;
- rkcif_mipi_lvds2= &rkcif_mipi_lvds2;
- rkcif_mipi_lvds3= &rkcif_mipi_lvds3;
- rkvenc0 = &rkvenc0;
- rkvenc1 = &rkvenc1;
- jpege0 = &jpege0;
- jpege1 = &jpege1;
- jpege2 = &jpege2;
- jpege3 = &jpege3;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- serial6 = &uart6;
- serial7 = &uart7;
- serial8 = &uart8;
- serial9 = &uart9;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- spi3 = &spi3;
- spi4 = &spi4;
- spi5 = &sfc;
- hdcp0 = &hdcp0;
- hdcp1 = &hdcp1;
- };
-
- clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- spll: spll {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <702000000>;
- clock-output-names = "spll";
- };
-
- xin32k: xin32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-
- xin24m: xin24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- };
-
- hclk_vo1: hclk_vo1@fd7c08ec {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08ec 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VO1USB_TOP_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08b0 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_vo0: hclk_vo0@fd7c08dc {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08dc 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VOP_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_usb: hclk_usb@fd7c08a8 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08a8 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VO1USB_TOP_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_nvm: hclk_nvm@fd7c087c {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c087c 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_NVM_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_usb: aclk_usb@fd7c08a8 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08a8 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VO1USB_TOP_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_isp1_pre: hclk_isp1_pre@fd7c0868 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c0868 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VI_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_isp1_pre: aclk_isp1_pre@fd7c0868 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c0868 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VI_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08a0 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08a0 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08a4 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08a4 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08b0 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08c0 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_RKVENC0>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08c0 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_RKVENC0>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08dc 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VOP_LOW_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c08ec 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VO1USB_TOP_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- pclk_av1_pre: pclk_av1_pre@fd7c0910 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c0910 0 0x10>;
- clock-names = "link";
- clocks = <&cru HCLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- aclk_av1_pre: aclk_av1_pre@fd7c0910 {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c0910 0 0x10>;
- clock-names = "link";
- clocks = <&cru ACLK_VDPU_ROOT>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- hclk_sdio_pre: hclk_sdio_pre@fd7c092c {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0 0xfd7c092c 0 0x10>;
- clock-names = "link";
- clocks = <&hclk_nvm>;
- #power-domain-cells = <1>;
- #clock-cells = <0>;
- };
-
- pclk_vo0_grf: pclk_vo0_grf@fd7c08dc {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0x0 0xfd7c08dc 0x0 0x4>;
- clocks = <&hclk_vo0>;
- clock-names = "link";
- #clock-cells = <0>;
- };
-
- pclk_vo1_grf: pclk_vo1_grf@fd7c08ec {
- compatible = "rockchip,rk3588-clock-gate-link";
- reg = <0x0 0xfd7c08ec 0x0 0x4>;
- clocks = <&hclk_vo1>;
- clock-names = "link";
- #clock-cells = <0>;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu_l0>;
- };
- core1 {
- cpu = <&cpu_l1>;
- };
- core2 {
- cpu = <&cpu_l2>;
- };
- core3 {
- cpu = <&cpu_l3>;
- };
- };
- cluster1 {
- core0 {
- cpu = <&cpu_b0>;
- };
- core1 {
- cpu = <&cpu_b1>;
- };
- };
- cluster2 {
- core0 {
- cpu = <&cpu_b2>;
- };
- core1 {
- cpu = <&cpu_b3>;
- };
- };
- };
-
- cpu_l0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- operating-points-v2 = <&cluster0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l0>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <100>;
- };
-
- cpu_l1: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- operating-points-v2 = <&cluster0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l1>;
- };
-
- cpu_l2: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x200>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- operating-points-v2 = <&cluster0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l2>;
- };
-
- cpu_l3: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x300>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- operating-points-v2 = <&cluster0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l3>;
- };
-
- cpu_b0: cpu@400 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x400>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- operating-points-v2 = <&cluster1_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b0>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <300>;
- };
-
- cpu_b1: cpu@500 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x500>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- operating-points-v2 = <&cluster1_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b1>;
- };
-
- cpu_b2: cpu@600 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x600>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- operating-points-v2 = <&cluster2_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b2>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <300>;
- };
-
- cpu_b3: cpu@700 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x700>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- operating-points-v2 = <&cluster2_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b3>;
- };
-
- idle-states {
- entry-method = "psci";
- CPU_SLEEP: cpu-sleep {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <100>;
- exit-latency-us = <120>;
- min-residency-us = <1000>;
- };
- };
-
- l2_cache_l0: l2-cache-l0 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_l1: l2-cache-l1 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_l2: l2-cache-l2 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_l3: l2-cache-l3 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b0: l2-cache-b0 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b1: l2-cache-b1 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b2: l2-cache-b2 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b3: l2-cache-b3 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&l3_cache>;
- };
-
- l3_cache: l3-cache {
- compatible = "cache";
- cache-size = <3145728>;
- cache-line-size = <64>;
- cache-sets = <4096>;
- };
- };
-
- cluster0_opp_table: cluster0-opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- nvmem-cells = <&cpul_leakage>, <&specification_serial_number>;
- nvmem-cell-names = "leakage", "specification_serial_number";
- rockchip,supported-hw;
- rockchip,opp-shared-dsu;
-
- rockchip,pvtm-voltage-sel = <
- 0 1410 0
- 1411 1434 1
- 1435 1458 2
- 1459 1482 3
- 1483 1506 4
- 1507 1530 5
- 1531 9999 6
- >;
- rockchip,pvtm-pvtpll;
- rockchip,pvtm-offset = <0x64>;
- rockchip,pvtm-sample-time = <1100>;
- rockchip,pvtm-freq = <1416000>;
- rockchip,pvtm-volt = <750000>;
- rockchip,pvtm-ref-temp = <25>;
- rockchip,pvtm-temp-prop = <244 244>;
- rockchip,pvtm-thermal-zone = "soc-thermal";
-
- rockchip,grf = <&litcore_grf>;
-
- rockchip,reboot-freq = <1416000>;
-
- rockchip,temp-hysteresis = <5000>;
- rockchip,low-temp = <10000>;
- rockchip,low-temp-min-volt = <750000>;
- rockchip,high-temp = <85000>;
- rockchip,high-temp-max-freq = <1608000>;
-
- opp-408000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <675000 675000 950000>,
- <675000 675000 950000>;
- clock-latency-ns = <40000>;
- };
- opp-600000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <675000 675000 950000>,
- <675000 675000 950000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <675000 675000 950000>,
- <675000 675000 950000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <675000 675000 950000>,
- <675000 675000 950000>;
- clock-latency-ns = <40000>;
- };
- opp-1200000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <712500 712500 950000>,
- <712500 712500 950000>;
- opp-microvolt-L1 = <700000 700000 950000>,
- <700000 700000 950000>;
- opp-microvolt-L2 = <700000 700000 950000>,
- <700000 700000 950000>;
- opp-microvolt-L3 = <687500 687500 950000>,
- <687500 687500 950000>;
- opp-microvolt-L4 = <675000 675000 950000>,
- <675000 675000 950000>;
- opp-microvolt-L5 = <675000 675000 950000>,
- <675000 675000 950000>;
- opp-microvolt-L6 = <675000 675000 950000>,
- <675000 675000 950000>;
- clock-latency-ns = <40000>;
- };
- opp-1416000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <762500 762500 950000>,
- <762500 762500 950000>;
- opp-microvolt-L1 = <750000 750000 950000>,
- <750000 750000 950000>;
- opp-microvolt-L2 = <737500 737500 950000>,
- <737500 737500 950000>;
- opp-microvolt-L3 = <725000 725000 950000>,
- <725000 725000 950000>;
- opp-microvolt-L4 = <725000 725000 950000>,
- <725000 725000 950000>;
- opp-microvolt-L5 = <712500 712500 950000>,
- <712500 712500 950000>;
- opp-microvolt-L6 = <712500 712500 950000>,
- <712500 712500 950000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-1608000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <850000 850000 950000>,
- <850000 850000 950000>;
- opp-microvolt-L1 = <837500 837500 950000>,
- <837500 837500 950000>;
- opp-microvolt-L2 = <825000 825000 950000>,
- <825000 825000 950000>;
- opp-microvolt-L3 = <812500 812500 950000>,
- <812500 812500 950000>;
- opp-microvolt-L4 = <800000 800000 950000>,
- <800000 800000 950000>;
- opp-microvolt-L5 = <800000 800000 950000>,
- <800000 800000 950000>;
- opp-microvolt-L6 = <787500 787500 950000>,
- <787500 787500 950000>;
- clock-latency-ns = <40000>;
- };
- opp-1800000000 {
- opp-supported-hw = <0xfd 0xffff>;
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <950000 950000 950000>,
- <950000 950000 950000>;
- opp-microvolt-L1 = <937500 937500 950000>,
- <937500 937500 950000>;
- opp-microvolt-L2 = <925000 925000 950000>,
- <925000 925000 950000>;
- opp-microvolt-L3 = <912500 912500 950000>,
- <912500 912500 950000>;
- opp-microvolt-L4 = <900000 900000 950000>,
- <900000 900000 950000>;
- opp-microvolt-L5 = <887500 887500 950000>,
- <887500 887500 950000>;
- opp-microvolt-L6 = <875000 875000 950000>,
- <875000 875000 950000>;
- clock-latency-ns = <40000>;
- };
- };
-
- cluster1_opp_table: cluster1-opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- nvmem-cells = <&cpub0_leakage>, <&specification_serial_number>;
- nvmem-cell-names = "leakage", "specification_serial_number";
- rockchip,supported-hw;
-
- rockchip,pvtm-voltage-sel = <
- 0 1595 0
- 1596 1615 1
- 1616 1640 2
- 1641 1675 3
- 1676 1710 4
- 1711 1743 5
- 1744 1776 6
- 1777 9999 7
- >;
- rockchip,pvtm-pvtpll;
- rockchip,pvtm-offset = <0x18>;
- rockchip,pvtm-sample-time = <1100>;
- rockchip,pvtm-freq = <1608000>;
- rockchip,pvtm-volt = <750000>;
- rockchip,pvtm-ref-temp = <25>;
- rockchip,pvtm-temp-prop = <270 270>;
- rockchip,pvtm-thermal-zone = "soc-thermal";
- rockchip,pvtm-low-len-sel = <3>;
-
- rockchip,grf = <&bigcore0_grf>;
- volt-mem-read-margin = <
- 855000 1
- 765000 2
- 675000 3
- 495000 4
- >;
- low-volt-mem-read-margin = <4>;
- intermediate-threshold-freq = <1008000>; /* KHz */
- rockchip,idle-threshold-freq = <2208000>; /* KHz */
- rockchip,reboot-freq = <1800000>; /* KHz */
-
- rockchip,temp-hysteresis = <5000>;
- rockchip,low-temp = <10000>;
- rockchip,low-temp-min-volt = <750000>;
- rockchip,high-temp = <85000>;
- rockchip,high-temp-max-freq = <2208000>;
-
- opp-408000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-600000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1200000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1416000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <725000 725000 1000000>,
- <725000 725000 1000000>;
- opp-microvolt-L2 = <712500 712500 1000000>,
- <712500 712500 1000000>;
- opp-microvolt-L3 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- opp-microvolt-L4 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- opp-microvolt-L5 = <687500 687500 1000000>,
- <687500 687500 1000000>;
- opp-microvolt-L6 = <675000 675000 1000000>,
- <675000 675000 1000000>;
- opp-microvolt-L7 = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1608000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <762500 762500 1000000>,
- <762500 762500 1000000>;
- opp-microvolt-L2 = <750000 750000 1000000>,
- <750000 750000 1000000>;
- opp-microvolt-L3 = <737500 737500 1000000>,
- <737500 737500 1000000>;
- opp-microvolt-L4 = <725000 725000 1000000>,
- <725000 725000 1000000>;
- opp-microvolt-L5 = <712500 712500 1000000>,
- <712500 712500 1000000>;
- opp-microvolt-L6 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- opp-microvolt-L7 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1800000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <850000 850000 1000000>,
- <850000 850000 1000000>;
- opp-microvolt-L1 = <837500 837500 1000000>,
- <837500 837500 1000000>;
- opp-microvolt-L2 = <825000 825000 1000000>,
- <825000 825000 1000000>;
- opp-microvolt-L3 = <812500 812500 1000000>,
- <812500 812500 1000000>;
- opp-microvolt-L4 = <800000 800000 1000000>,
- <800000 800000 1000000>;
- opp-microvolt-L5 = <787500 787500 1000000>,
- <787500 787500 1000000>;
- opp-microvolt-L6 = <775000 775000 1000000>,
- <775000 775000 1000000>;
- opp-microvolt-L7 = <762500 762500 1000000>,
- <762500 762500 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2016000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2016000000>;
- opp-microvolt = <925000 925000 1000000>,
- <925000 925000 1000000>;
- opp-microvolt-L1 = <912500 912500 1000000>,
- <912500 912500 1000000>;
- opp-microvolt-L2 = <900000 900000 1000000>,
- <900000 900000 1000000>;
- opp-microvolt-L3 = <887500 887500 1000000>,
- <887500 887500 1000000>;
- opp-microvolt-L4 = <875000 875000 1000000>,
- <875000 875000 1000000>;
- opp-microvolt-L5 = <862500 862500 1000000>,
- <862500 862500 1000000>;
- opp-microvolt-L6 = <850000 850000 1000000>,
- <850000 850000 1000000>;
- opp-microvolt-L7 = <837500 837500 1000000>,
- <837500 837500 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2208000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2208000000>;
- opp-microvolt = <987500 987500 1000000>,
- <987500 987500 1000000>;
- opp-microvolt-L1 = <975000 975000 1000000>,
- <975000 975000 1000000>;
- opp-microvolt-L2 = <962500 962500 1000000>,
- <962500 962500 1000000>;
- opp-microvolt-L3 = <950000 950000 1000000>,
- <950000 950000 1000000>;
- opp-microvolt-L4 = <962500 962500 1000000>,
- <962500 962500 1000000>;
- opp-microvolt-L5 = <950000 950000 1000000>,
- <950000 950000 1000000>;
- opp-microvolt-L6 = <925000 925000 1000000>,
- <925000 925000 1000000>;
- opp-microvolt-L7 = <912500 912500 1000000>,
- <912500 912500 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2256000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2256000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2304000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2304000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2352000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2352000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2400000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2400000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- };
-
- cluster2_opp_table: cluster2-opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- nvmem-cells = <&cpub1_leakage>, <&specification_serial_number>;
- nvmem-cell-names = "leakage", "specification_serial_number";
- rockchip,supported-hw;
-
- rockchip,pvtm-voltage-sel = <
- 0 1595 0
- 1596 1615 1
- 1616 1640 2
- 1641 1675 3
- 1676 1710 4
- 1711 1743 5
- 1744 1776 6
- 1777 9999 7
- >;
- rockchip,pvtm-pvtpll;
- rockchip,pvtm-offset = <0x18>;
- rockchip,pvtm-sample-time = <1100>;
- rockchip,pvtm-freq = <1608000>;
- rockchip,pvtm-volt = <750000>;
- rockchip,pvtm-ref-temp = <25>;
- rockchip,pvtm-temp-prop = <270 270>;
- rockchip,pvtm-thermal-zone = "soc-thermal";
- rockchip,pvtm-low-len-sel = <3>;
-
- rockchip,grf = <&bigcore1_grf>;
- volt-mem-read-margin = <
- 855000 1
- 765000 2
- 675000 3
- 495000 4
- >;
- low-volt-mem-read-margin = <4>;
- intermediate-threshold-freq = <1008000>; /* KHz */
- rockchip,idle-threshold-freq = <2208000>; /* KHz */
- rockchip,reboot-freq = <1800000>; /* KHz */
-
- rockchip,temp-hysteresis = <5000>;
- rockchip,low-temp = <10000>;
- rockchip,low-temp-min-volt = <750000>;
- rockchip,high-temp = <85000>;
- rockchip,high-temp-max-freq = <2208000>;
-
- opp-408000000 {
- opp-supported-hw = <0xff 0x0ffff>;
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-600000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1200000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1416000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <725000 725000 1000000>,
- <725000 725000 1000000>;
- opp-microvolt-L2 = <712500 712500 1000000>,
- <712500 712500 1000000>;
- opp-microvolt-L3 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- opp-microvolt-L4 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- opp-microvolt-L5 = <687500 687500 1000000>,
- <687500 687500 1000000>;
- opp-microvolt-L6 = <675000 675000 1000000>,
- <675000 675000 1000000>;
- opp-microvolt-L7 = <675000 675000 1000000>,
- <675000 675000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1608000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <762500 762500 1000000>,
- <762500 762500 1000000>;
- opp-microvolt-L2 = <750000 750000 1000000>,
- <750000 750000 1000000>;
- opp-microvolt-L3 = <737500 737500 1000000>,
- <737500 737500 1000000>;
- opp-microvolt-L4 = <725000 725000 1000000>,
- <725000 725000 1000000>;
- opp-microvolt-L5 = <712500 712500 1000000>,
- <712500 712500 1000000>;
- opp-microvolt-L6 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- opp-microvolt-L7 = <700000 700000 1000000>,
- <700000 700000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1800000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <850000 850000 1000000>,
- <850000 850000 1000000>;
- opp-microvolt-L1 = <837500 837500 1000000>,
- <837500 837500 1000000>;
- opp-microvolt-L2 = <825000 825000 1000000>,
- <825000 825000 1000000>;
- opp-microvolt-L3 = <812500 812500 1000000>,
- <812500 812500 1000000>;
- opp-microvolt-L4 = <800000 800000 1000000>,
- <800000 800000 1000000>;
- opp-microvolt-L5 = <787500 787500 1000000>,
- <787500 787500 1000000>;
- opp-microvolt-L6 = <775000 775000 1000000>,
- <775000 775000 1000000>;
- opp-microvolt-L7 = <762500 762500 1000000>,
- <762500 762500 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2016000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2016000000>;
- opp-microvolt = <925000 925000 1000000>,
- <925000 925000 1000000>;
- opp-microvolt-L1 = <912500 912500 1000000>,
- <912500 912500 1000000>;
- opp-microvolt-L2 = <900000 900000 1000000>,
- <900000 900000 1000000>;
- opp-microvolt-L3 = <887500 887500 1000000>,
- <887500 887500 1000000>;
- opp-microvolt-L4 = <875000 875000 1000000>,
- <875000 875000 1000000>;
- opp-microvolt-L5 = <862500 862500 1000000>,
- <862500 862500 1000000>;
- opp-microvolt-L6 = <850000 850000 1000000>,
- <850000 850000 1000000>;
- opp-microvolt-L7 = <837500 837500 1000000>,
- <837500 837500 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2208000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2208000000>;
- opp-microvolt = <987500 987500 1000000>,
- <987500 987500 1000000>;
- opp-microvolt-L3 = <975000 975000 1000000>,
- <975000 975000 1000000>;
- opp-microvolt-L4 = <962500 962500 1000000>,
- <962500 962500 1000000>;
- opp-microvolt-L5 = <950000 950000 1000000>,
- <950000 950000 1000000>;
- opp-microvolt-L6 = <925000 925000 1000000>,
- <925000 925000 1000000>;
- opp-microvolt-L7 = <912500 912500 1000000>,
- <912500 912500 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2256000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2256000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2304000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2304000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2352000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2352000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- opp-2400000000 {
- opp-supported-hw = <0xff 0xffff>;
- opp-hz = /bits/ 64 <2400000000>;
- opp-microvolt = <1000000 1000000 1000000>,
- <1000000 1000000 1000000>;
- clock-latency-ns = <40000>;
- };
- };
-
- arm_pmu: arm-pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>,
- <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
- };
-
- cpuinfo {
- compatible = "rockchip,cpuinfo";
- nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
- nvmem-cell-names = "id", "cpu-version", "cpu-code";
- };
-
- csi2_dcphy0: csi2-dcphy0 {
- compatible = "rockchip,rk3588-csi2-dcphy";
- phys = <&mipi_dcphy0>;
- phy-names = "dcphy";
- status = "disabled";
- };
-
- csi2_dcphy1: csi2-dcphy1 {
- compatible = "rockchip,rk3588-csi2-dcphy";
- phys = <&mipi_dcphy1>;
- phy-names = "dcphy";
- status = "disabled";
- };
-
- /* dphy0 full mode */
- csi2_dphy0: csi2-dphy0 {
- compatible = "rockchip,rk3568-csi2-dphy";
- rockchip,hw = <&csi2_dphy0_hw>;
- status = "disabled";
- };
-
- /* dphy0 split mode 01 */
- csi2_dphy1: csi2-dphy1 {
- compatible = "rockchip,rk3568-csi2-dphy";
- rockchip,hw = <&csi2_dphy0_hw>;
- status = "disabled";
- };
-
- /* dphy0 split mode 23 */
- csi2_dphy2: csi2-dphy2 {
- compatible = "rockchip,rk3568-csi2-dphy";
- rockchip,hw = <&csi2_dphy0_hw>;
- status = "disabled";
- };
-
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
-
- route {
- route_dp0: route-dp0 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp1_out_dp0>;
- };
-
- route_dsi0: route-dsi0 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp3_out_dsi0>;
- };
-
- route_dsi1: route-dsi1 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp3_out_dsi1>;
- };
-
- route_edp0: route-edp0 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp2_out_edp0>;
- };
-
- route_edp1: route-edp1 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- };
-
- route_hdmi0: route-hdmi0 {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp0_out_hdmi0>;
- };
-
- route_rgb: route-rgb {
- status = "disabled";
- logo,uboot = "logo.bmp";
- logo,kernel = "logo_kernel.bmp";
- logo,mode = "center";
- charge_logo,mode = "center";
- connect = <&vp3_out_rgb>;
- };
- };
- };
-
- dmc: dmc {
- compatible = "rockchip,rk3588-dmc";
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "complete";
- devfreq-events = <&dfi>;
- clocks = <&scmi_clk 4>;
- clock-names = "dmc_clk";
- operating-points-v2 = <&dmc_opp_table>;
- upthreshold = <40>;
- downdifferential = <20>;
- system-status-level = <
- /*system status freq level*/
- SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH
- SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
- SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
- SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
- SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
- SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
- SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
- SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
- SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
- SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
- SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
- >;
- auto-freq-en = <1>;
- status = "disabled";
- };
-
- dmc_opp_table: dmc-opp-table {
- compatible = "operating-points-v2";
-
- nvmem-cells = <&log_leakage>;
- nvmem-cell-names = "leakage";
- rockchip,leakage-voltage-sel = <
- 1 31 0
- 32 44 1
- 45 57 2
- 58 254 3
- >;
- rockchip,temp-hysteresis = <5000>;
- rockchip,low-temp = <10000>;
- rockchip,low-temp-min-volt = <750000>;
-
- opp-528000000 {
- opp-hz = /bits/ 64 <528000000>;
- opp-microvolt = <675000 675000 875000>,
- <725000 725000 750000>;
- opp-microvolt-L1 = <675000 675000 875000>,
- <700000 700000 750000>;
- opp-microvolt-L2 = <675000 675000 875000>,
- <687500 687500 750000>;
- opp-microvolt-L3 = <675000 675000 875000>,
- <675000 675000 750000>;
- };
- opp-1068000000 {
- opp-hz = /bits/ 64 <1068000000>;
- opp-microvolt = <725000 725000 875000>,
- <737500 737500 750000>;
- opp-microvolt-L1 = <700000 700000 875000>,
- <712500 712500 750000>;
- opp-microvolt-L2 = <675000 675000 875000>,
- <700000 700000 750000>;
- opp-microvolt-L3 = <675000 675000 875000>,
- <687500 687500 750000>;
- };
- opp-1560000000 {
- opp-hz = /bits/ 64 <1560000000>;
- opp-microvolt = <800000 800000 875000>,
- <750000 750000 750000>;
- opp-microvolt-L1 = <775000 775000 875000>,
- <725000 725000 750000>;
- opp-microvolt-L2 = <750000 750000 875000>,
- <712500 712500 750000>;
- opp-microvolt-L3 = <725000 725000 875000>,
- <700000 700000 750000>;
- };
- opp-2750000000 {
- opp-hz = /bits/ 64 <2750000000>;
- opp-microvolt = <875000 875000 875000>,
- <750000 750000 750000>;
- opp-microvolt-L1 = <850000 850000 875000>,
- <750000 750000 750000>;
- opp-microvolt-L2 = <837500 837500 875000>,
- <725000 725000 750000>;
- opp-microvolt-L3 = <825000 820000 875000>,
- <700000 700000 750000>;
- };
- };
-
- firmware {
- scmi: scmi {
- compatible = "arm,scmi-smc";
- shmem = <&scmi_shmem>;
- arm,smc-id = <0x82000010>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
-
- assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>,
- <&scmi_clk SCMI_CLK_CPUB01>,
- <&scmi_clk SCMI_CLK_CPUB23>;
- assigned-clock-rates = <816000000>,
- <816000000>,
- <816000000>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
- };
-
- sdei: sdei {
- compatible = "arm,sdei-1.0";
- method = "smc";
- };
- };
-
- jpege_ccu: jpege-ccu {
- compatible = "rockchip,vpu-jpege-ccu";
- status = "disabled";
- };
-
- mpp_srv: mpp-srv {
- compatible = "rockchip,mpp-service";
- rockchip,taskqueue-count = <12>;
- rockchip,resetgroup-count = <1>;
- status = "disabled";
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- rkcif_dvp: rkcif-dvp {
- compatible = "rockchip,rkcif-dvp";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_dvp_sditf: rkcif-dvp-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_dvp>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds: rkcif-mipi-lvds {
- compatible = "rockchip,rkcif-mipi-lvds";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
- compatible = "rockchip,rkcif-mipi-lvds";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds1>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds1>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds1>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds1>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
- compatible = "rockchip,rkcif-mipi-lvds";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds2>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds2>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds2>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds2>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
- compatible = "rockchip,rkcif-mipi-lvds";
- rockchip,hw = <&rkcif>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds3>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds3>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds3>;
- status = "disabled";
- };
-
- rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
- compatible = "rockchip,rkcif-sditf";
- rockchip,cif = <&rkcif_mipi_lvds3>;
- status = "disabled";
- };
-
- rkisp0_vir0: rkisp0-vir0 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp0>;
- /*
- * dual isp process image case
- * other rkisp hw and virtual nodes should disabled
- * rockchip,hw = <&rkisp_unite>;
- */
- status = "disabled";
- };
-
- rkisp0_vir1: rkisp0-vir1 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp0>;
- status = "disabled";
- };
-
- rkisp0_vir2: rkisp0-vir2 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp0>;
- status = "disabled";
- };
-
- rkisp0_vir3: rkisp0-vir3 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp0>;
- status = "disabled";
- };
-
- rkisp1_vir0: rkisp1-vir0 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp1>;
- status = "disabled";
- };
-
- rkisp1_vir1: rkisp1-vir1 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp1>;
- status = "disabled";
- };
-
- rkisp1_vir2: rkisp1-vir2 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp1>;
- status = "disabled";
- };
-
- rkisp1_vir3: rkisp1-vir3 {
- compatible = "rockchip,rkisp-vir";
- rockchip,hw = <&rkisp1>;
- status = "disabled";
- };
-
- rkispp0_vir0: rkispp0-vir0 {
- compatible = "rockchip,rk3588-rkispp-vir";
- rockchip,hw = <&rkispp0>;
- status = "disabled";
- };
-
- rkispp1_vir0: rkispp1-vir0 {
- compatible = "rockchip,rk3588-rkispp-vir";
- rockchip,hw = <&rkispp1>;
- status = "disabled";
- };
-
- rkvenc_ccu: rkvenc-ccu {
- compatible = "rockchip,rkv-encoder-v2-ccu";
- status = "disabled";
- };
-
- rockchip_suspend: rockchip-suspend {
- compatible = "rockchip,pm-rk3588";
- status = "disabled";
- rockchip,sleep-debug-en = <0>;
- rockchip,sleep-mode-config = <
- (0
- | RKPM_SLP_ARMOFF_LOGOFF
- | RKPM_SLP_PMU_PMUALIVE_32K
- | RKPM_SLP_PMU_DIS_OSC
- | RKPM_SLP_32K_EXT
- )
- >;
- rockchip,wakeup-config = <
- (0
- | RKPM_GPIO_WKUP_EN
- )
- >;
- };
-
- rockchip_system_monitor: rockchip-system-monitor {
- compatible = "rockchip,system-monitor";
-
- rockchip,thermal-zone = "soc-thermal";
- };
-
- thermal_zones: thermal-zones {
- soc_thermal: soc-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- sustainable-power = <2100>; /* milliwatts */
-
- thermal-sensors = <&tsadc 0>;
- trips {
- threshold: trip-point-0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- target: trip-point-1 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- soc_crit: soc-crit {
- /* millicelsius */
- temperature = <115000>;
- /* millicelsius */
- hysteresis = <2000>;
- type = "critical";
- };
- };
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- map1 {
- trip = <&target>;
- cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- map2 {
- trip = <&target>;
- cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- map3 {
- trip = <&target>;
- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- };
- };
-
- bigcore0_thermal: bigcore0-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&tsadc 1>;
- };
-
- bigcore1_thermal: bigcore1-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&tsadc 2>;
- };
-
- little_core_thermal: littlecore-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&tsadc 3>;
- };
-
- center_thermal: center-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&tsadc 4>;
- };
-
- gpu_thermal: gpu-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&tsadc 5>;
- };
-
- npu_thermal: npu-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&tsadc 6>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- sram@10f000 {
- compatible = "mmio-sram";
- reg = <0x0 0x0010f000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x0010f000 0x100>;
-
- scmi_shmem: sram@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x100>;
- };
- };
-
- gpu: gpu@fb000000 {
- compatible = "arm,mali-bifrost";
- reg = <0x0 0xfb000000 0x0 0x200000>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "GPU", "MMU", "JOB";
-
- clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
- <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>;
- clock-names = "clk_mali", "clk_gpu_coregroup",
- "clk_gpu_stacks", "clk_gpu";
- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
- assigned-clock-rates = <200000000>;
- power-domains = <&power RK3588_PD_GPU>;
- operating-points-v2 = <&gpu_opp_table>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <2982>;
-
- upthreshold = <30>;
- downdifferential = <10>;
-
- status = "disabled";
- };
-
- gpu_opp_table: gpu-opp-table {
- compatible = "operating-points-v2";
-
- nvmem-cells = <&gpu_leakage>;
- nvmem-cell-names = "leakage";
-
- rockchip,pvtm-voltage-sel = <
- 0 815 0
- 816 835 1
- 836 860 2
- 861 885 3
- 886 910 4
- 911 9999 5
- >;
- rockchip,pvtm-pvtpll;
- rockchip,pvtm-offset = <0x1c>;
- rockchip,pvtm-sample-time = <1100>;
- rockchip,pvtm-freq = <800000>;
- rockchip,pvtm-volt = <750000>;
- rockchip,pvtm-ref-temp = <25>;
- rockchip,pvtm-temp-prop = <(-135) (-135)>;
- rockchip,pvtm-thermal-zone = "gpu-thermal";
-
- clocks = <&cru CLK_GPU>;
- clock-names = "clk";
- rockchip,grf = <&gpu_grf>;
- volt-mem-read-margin = <
- 855000 1
- 765000 2
- 675000 3
- 495000 4
- >;
- low-volt-mem-read-margin = <4>;
- intermediate-threshold-freq = <400000>; /* KHz */
-
- rockchip,temp-hysteresis = <5000>;
- rockchip,low-temp = <10000>;
- rockchip,low-temp-min-volt = <750000>;
- rockchip,high-temp = <85000>;
- rockchip,high-temp-max-freq = <800000>;
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L2 = <687500 687500 850000>,
- <687500 687500 850000>;
- opp-microvolt-L3 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L4 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L5 = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <750000 750000 850000>,
- <750000 750000 850000>;
- opp-microvolt-L1 = <737500 737500 850000>,
- <737500 737500 850000>;
- opp-microvolt-L2 = <725000 725000 850000>,
- <725000 725000 850000>;
- opp-microvolt-L3 = <712500 712500 850000>,
- <712500 712500 850000>;
- opp-microvolt-L4 = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L5 = <700000 700000 850000>,
- <700000 700000 850000>;
- };
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = <800000 800000 850000>,
- <800000 800000 850000>;
- opp-microvolt-L1 = <787500 787500 850000>,
- <787500 787500 850000>;
- opp-microvolt-L2 = <775000 775000 850000>,
- <775000 775000 850000>;
- opp-microvolt-L3 = <762500 762500 850000>,
- <762500 762500 850000>;
- opp-microvolt-L4 = <750000 750000 850000>,
- <750000 750000 850000>;
- opp-microvolt-L5 = <737500 737500 850000>,
- <737500 737500 850000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <850000 850000 850000>,
- <850000 850000 850000>;
- opp-microvolt-L1 = <837500 837500 850000>,
- <837500 837500 850000>;
- opp-microvolt-L2 = <825000 825000 850000>,
- <825000 825000 850000>;
- opp-microvolt-L3 = <812500 812500 850000>,
- <812500 812500 850000>;
- opp-microvolt-L4 = <800000 800000 850000>,
- <800000 800000 850000>;
- opp-microvolt-L5 = <787500 787500 850000>,
- <787500 787500 850000>;
- };
- };
-
- usbdrd3_0: usbdrd3_0 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
- <&cru ACLK_USB3OTG0>;
- clock-names = "ref", "suspend", "bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- usbdrd_dwc3_0: usb@fc000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfc000000 0x0 0x400000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG0>;
- reset-names = "usb3-otg";
- dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,parkmode-disable-ss-quirk;
- quirk-skip-phy-init;
- status = "disabled";
- };
- };
-
- usb_host0_ehci: usb@fc800000 {
- compatible = "rockchip,rk3588-ehci", "generic-ehci";
- reg = <0x0 0xfc800000 0x0 0x40000>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>;
- clock-names = "usbhost", "arbiter", "utmi";
- companion = <&usb_host0_ohci>;
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host0_ohci: usb@fc840000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfc840000 0x0 0x40000>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>;
- clock-names = "usbhost", "arbiter", "utmi";
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host1_ehci: usb@fc880000 {
- compatible = "rockchip,rk3588-ehci", "generic-ehci";
- reg = <0x0 0xfc880000 0x0 0x40000>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>;
- clock-names = "usbhost", "arbiter", "utmi";
- companion = <&usb_host1_ohci>;
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host1_ohci: usb@fc8c0000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfc8c0000 0x0 0x40000>;
- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>;
- clock-names = "usbhost", "arbiter", "utmi";
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- mmu600_pcie: iommu@fc900000 {
- compatible = "arm,smmu-v3";
- reg = <0x0 0xfc900000 0x0 0x200000>;
- interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- mmu600_php: iommu@fcb00000 {
- compatible = "arm,smmu-v3";
- reg = <0x0 0xfcb00000 0x0 0x200000>;
- interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- usbhost3_0: usbhost3_0 {
- compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
- clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
- <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
- <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>;
- clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- usbhost_dwc3_0: usb@fcd00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfcd00000 0x0 0x400000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&cru SRST_A_USB3OTG2>;
- reset-names = "usb3-host";
- dr_mode = "host";
- phys = <&combphy2_psu PHY_TYPE_USB3>;
- phy-names = "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis_rxdet_inp3_quirk;
- snps,parkmode-disable-ss-quirk;
- status = "disabled";
- };
- };
-
- pmu0_grf: syscon@fd588000 {
- compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd588000 0x0 0x2000>;
-
- reboot_mode: reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x80>;
- mode-bootloader = <BOOT_BL_DOWNLOAD>;
- mode-charge = <BOOT_CHARGING>;
- mode-fastboot = <BOOT_FASTBOOT>;
- mode-loader = <BOOT_BL_DOWNLOAD>;
- mode-normal = <BOOT_NORMAL>;
- mode-recovery = <BOOT_RECOVERY>;
- mode-ums = <BOOT_UMS>;
- mode-panic = <BOOT_PANIC>;
- mode-watchdog = <BOOT_WATCHDOG>;
- };
- };
-
- pmu1_grf: syscon@fd58a000 {
- compatible = "rockchip,rk3588-pmu1-grf", "syscon";
- reg = <0x0 0xfd58a000 0x0 0x2000>;
- };
-
- sys_grf: syscon@fd58c000 {
- compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd58c000 0x0 0x1000>;
-
- rgb: rgb {
- compatible = "rockchip,rk3588-rgb";
- pinctrl-names = "default";
- pinctrl-0 = <&bt1120_pins>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rgb_in_vp3: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp3_out_rgb>;
- status = "disabled";
- };
- };
- };
- };
- };
-
- bigcore0_grf: syscon@fd590000 {
- compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
- reg = <0x0 0xfd590000 0x0 0x100>;
- };
-
- bigcore1_grf: syscon@fd592000 {
- compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
- reg = <0x0 0xfd592000 0x0 0x100>;
- };
-
- litcore_grf: syscon@fd594000 {
- compatible = "rockchip,rk3588-litcore-grf", "syscon";
- reg = <0x0 0xfd594000 0x0 0x100>;
- };
-
- dsu_grf: syscon@fd598000 {
- compatible = "rockchip,rk3588-dsu-grf", "syscon";
- reg = <0x0 0xfd598000 0x0 0x100>;
- };
-
- gpu_grf: syscon@fd5a0000 {
- compatible = "rockchip,rk3588-gpu-grf", "syscon";
- reg = <0x0 0xfd5a0000 0x0 0x100>;
- };
-
- npu_grf: syscon@fd5a2000 {
- compatible = "rockchip,rk3588-npu-grf", "syscon";
- reg = <0x0 0xfd5a2000 0x0 0x100>;
- };
-
- vop_grf: syscon@fd5a4000 {
- compatible = "rockchip,rk3588-vop-grf", "syscon";
- reg = <0x0 0xfd5a4000 0x0 0x2000>;
- };
-
- vo0_grf: syscon@fd5a6000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a6000 0x0 0x2000>;
- clocks = <&pclk_vo0_grf>;
- };
-
- vo1_grf: syscon@fd5a8000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a8000 0x0 0x100>;
- clocks = <&pclk_vo1_grf>;
- };
-
- usb_grf: syscon@fd5ac000 {
- compatible = "rockchip,rk3588-usb-grf", "syscon";
- reg = <0x0 0xfd5ac000 0x0 0x4000>;
- };
-
- php_grf: syscon@fd5b0000 {
- compatible = "rockchip,rk3588-php-grf", "syscon";
- reg = <0x0 0xfd5b0000 0x0 0x1000>;
- };
-
- mipidphy0_grf: syscon@fd5b4000 {
- compatible = "rockchip,mipi-dphy-grf", "syscon";
- reg = <0x0 0xfd5b4000 0x0 0x1000>;
- };
-
- mipidphy1_grf: syscon@fd5b5000 {
- compatible = "rockchip,mipi-dphy-grf", "syscon";
- reg = <0x0 0xfd5b5000 0x0 0x1000>;
- };
-
- pipe_phy0_grf: syscon@fd5bc000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5bc000 0x0 0x100>;
- };
-
- pipe_phy2_grf: syscon@fd5c4000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5c4000 0x0 0x100>;
- };
-
- usbdpphy0_grf: syscon@fd5c8000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5c8000 0x0 0x4000>;
- };
-
- usb2phy0_grf: syscon@fd5d0000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xfd5d0000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy0: usb2-phy@0 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x0 0x10>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
- reset-names = "phy", "apb";
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy0";
- #clock-cells = <0>;
- rockchip,usbctrl-grf = <&usb_grf>;
- status = "disabled";
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- usb2phy2_grf: syscon@fd5d8000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xfd5d8000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy2: usb2-phy@8000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy2";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy2_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- usb2phy3_grf: syscon@fd5dc000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xfd5dc000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy3: usb2-phy@c000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy3";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy3_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- hdptxphy0_grf: syscon@fd5e0000 {
- compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
- reg = <0x0 0xfd5e0000 0x0 0x100>;
- };
-
- mipidcphy0_grf: syscon@fd5e8000 {
- compatible = "rockchip,mipi-dcphy-grf", "syscon";
- reg = <0x0 0xfd5e8000 0x0 0x4000>;
- };
-
- mipidcphy1_grf: syscon@fd5ec000 {
- compatible = "rockchip,mipi-dcphy-grf", "syscon";
- reg = <0x0 0xfd5ec000 0x0 0x4000>;
- };
-
- ioc: syscon@fd5f0000 {
- compatible = "rockchip,rk3588-ioc", "syscon";
- reg = <0x0 0xfd5f0000 0x0 0x10000>;
- };
-
- cru: clock-controller@fd7c0000 {
- compatible = "rockchip,rk3588-cru";
- rockchip,grf = <&php_grf>;
- reg = <0x0 0xfd7c0000 0x0 0x5c000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- assigned-clocks =
- <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
- <&cru PLL_NPLL>, <&cru PLL_GPLL>,
- <&cru ACLK_CENTER_ROOT>,
- <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
- <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
- <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
- <&cru HCLK_PMU_CM0_ROOT>,
- <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
- <&cru CLK_GPU>;
- assigned-clock-rates =
- <1100000000>, <786432000>,
- <850000000>, <1188000000>,
- <702000000>,
- <400000000>, <500000000>,
- <800000000>, <100000000>,
- <400000000>, <100000000>,
- <200000000>,
- <375000000>, <150000000>,
- <200000000>;
- };
-
- i2c0: i2c@fd880000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfd880000 0x0 0x1000>;
- clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart0: serial@fd890000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfd890000 0x0 0x100>;
- interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac0 6>, <&dmac0 7>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0m1_xfer>;
- status = "disabled";
- };
-
- pwm0: pwm@fd8b0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm0m0_pins>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm1: pwm@fd8b0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm1m0_pins>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm2: pwm@fd8b0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2m0_pins>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm3: pwm@fd8b0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0030 0x0 0x10>;
- interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm3m0_pins>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pmu: power-management@fd8d8000 {
- compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
- reg = <0x0 0xfd8d8000 0x0 0x400>;
-
- power: power-controller {
- compatible = "rockchip,rk3588-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- /* These power domains are grouped by VD_NPU */
- power-domain@RK3588_PD_NPU {
- reg = <RK3588_PD_NPU>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3588_PD_NPUTOP {
- reg = <RK3588_PD_NPUTOP>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru HCLK_NPU_ROOT>,
- <&cru PCLK_NPU_ROOT>,
- <&cru CLK_NPU_DSU0>,
- <&cru HCLK_NPU_CM0_ROOT>;
- pm_qos = <&qos_npu0_mwr>,
- <&qos_npu0_mro>,
- <&qos_mcu_npu>;
-
- power-domain@RK3588_PD_NPU1 {
- reg = <RK3588_PD_NPU1>;
- clocks = <&cru HCLK_NPU_ROOT>,
- <&cru PCLK_NPU_ROOT>,
- <&cru CLK_NPU_DSU0>;
- pm_qos = <&qos_npu1>;
- };
- power-domain@RK3588_PD_NPU2 {
- reg = <RK3588_PD_NPU2>;
- clocks = <&cru HCLK_NPU_ROOT>,
- <&cru PCLK_NPU_ROOT>,
- <&cru CLK_NPU_DSU0>;
- pm_qos = <&qos_npu2>;
- };
- };
- };
- /* These power domains are grouped by VD_GPU */
- power-domain@RK3588_PD_GPU {
- reg = <RK3588_PD_GPU>;
- clocks = <&cru CLK_GPU>,
- <&cru CLK_GPU_COREGROUP>,
- <&cru CLK_GPU_STACKS>;
- pm_qos = <&qos_gpu_m0>,
- <&qos_gpu_m1>,
- <&qos_gpu_m2>,
- <&qos_gpu_m3>;
- };
- /* These power domains are grouped by VD_VCODEC */
- power-domain@RK3588_PD_VCODEC {
- reg = <RK3588_PD_VCODEC>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3588_PD_RKVDEC0 {
- reg = <RK3588_PD_RKVDEC0>;
- clocks = <&cru HCLK_RKVDEC0>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_RKVDEC0>,
- <&cru ACLK_RKVDEC_CCU>;
- pm_qos = <&qos_rkvdec0>;
- };
- power-domain@RK3588_PD_RKVDEC1 {
- reg = <RK3588_PD_RKVDEC1>;
- clocks = <&cru HCLK_RKVDEC1>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_RKVDEC1>;
- pm_qos = <&qos_rkvdec1>;
- };
- power-domain@RK3588_PD_VENC0 {
- reg = <RK3588_PD_VENC0>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru HCLK_RKVENC0>,
- <&cru ACLK_RKVENC0>;
- pm_qos = <&qos_rkvenc0_m0ro>,
- <&qos_rkvenc0_m1ro>,
- <&qos_rkvenc0_m2wo>;
-
- power-domain@RK3588_PD_VENC1 {
- reg = <RK3588_PD_VENC1>;
- clocks = <&cru HCLK_RKVENC1>,
- <&cru HCLK_RKVENC0>,
- <&cru ACLK_RKVENC0>,
- <&cru ACLK_RKVENC1>;
- pm_qos = <&qos_rkvenc1_m0ro>,
- <&qos_rkvenc1_m1ro>,
- <&qos_rkvenc1_m2wo>;
- };
- };
- };
- /* These power domains are grouped by VD_LOGIC */
- power-domain@RK3588_PD_VDPU {
- reg = <RK3588_PD_VDPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_LOW_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_JPEG_DECODER_ROOT>,
- <&cru ACLK_IEP2P0>,
- <&cru HCLK_IEP2P0>,
- <&cru ACLK_JPEG_ENCODER0>,
- <&cru HCLK_JPEG_ENCODER0>,
- <&cru ACLK_JPEG_ENCODER1>,
- <&cru HCLK_JPEG_ENCODER1>,
- <&cru ACLK_JPEG_ENCODER2>,
- <&cru HCLK_JPEG_ENCODER2>,
- <&cru ACLK_JPEG_ENCODER3>,
- <&cru HCLK_JPEG_ENCODER3>,
- <&cru ACLK_JPEG_DECODER>,
- <&cru HCLK_JPEG_DECODER>,
- <&cru ACLK_RGA2>,
- <&cru HCLK_RGA2>;
- pm_qos = <&qos_iep>,
- <&qos_jpeg_dec>,
- <&qos_jpeg_enc0>,
- <&qos_jpeg_enc1>,
- <&qos_jpeg_enc2>,
- <&qos_jpeg_enc3>,
- <&qos_rga2_mro>,
- <&qos_rga2_mwo>;
-
- power-domain@RK3588_PD_AV1 {
- reg = <RK3588_PD_AV1>;
- clocks = <&cru PCLK_AV1>,
- <&cru ACLK_AV1>,
- <&cru HCLK_VDPU_ROOT>;
- pm_qos = <&qos_av1>;
- };
- power-domain@RK3588_PD_RKVDEC0 {
- reg = <RK3588_PD_RKVDEC0>;
- clocks = <&cru HCLK_RKVDEC0>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_RKVDEC0>;
- pm_qos = <&qos_rkvdec0>;
- };
- power-domain@RK3588_PD_RKVDEC1 {
- reg = <RK3588_PD_RKVDEC1>;
- clocks = <&cru HCLK_RKVDEC1>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>;
- pm_qos = <&qos_rkvdec1>;
- };
- power-domain@RK3588_PD_RGA30 {
- reg = <RK3588_PD_RGA30>;
- clocks = <&cru ACLK_RGA3_0>,
- <&cru HCLK_RGA3_0>;
- pm_qos = <&qos_rga3_0>;
- };
- };
- power-domain@RK3588_PD_VOP {
- reg = <RK3588_PD_VOP>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru PCLK_VOP_ROOT>,
- <&cru HCLK_VOP_ROOT>,
- <&cru ACLK_VOP>;
- pm_qos = <&qos_vop_m0>,
- <&qos_vop_m1>;
-
- power-domain@RK3588_PD_VO0 {
- reg = <RK3588_PD_VO0>;
- clocks = <&cru PCLK_VO0_ROOT>,
- <&cru PCLK_VO0_S_ROOT>,
- <&cru HCLK_VO0_S_ROOT>,
- <&cru ACLK_VO0_ROOT>,
- <&cru HCLK_HDCP0>,
- <&cru ACLK_HDCP0>,
- <&cru HCLK_VOP_ROOT>;
- pm_qos = <&qos_hdcp0>;
- };
- };
- power-domain@RK3588_PD_VO1 {
- reg = <RK3588_PD_VO1>;
- clocks = <&cru PCLK_VO1_ROOT>,
- <&cru PCLK_VO1_S_ROOT>,
- <&cru HCLK_VO1_S_ROOT>,
- <&cru HCLK_HDCP1>,
- <&cru ACLK_HDCP1>,
- <&cru ACLK_HDMIRX_ROOT>,
- <&cru HCLK_VO1USB_TOP_ROOT>;
- pm_qos = <&qos_hdcp1>,
- <&qos_hdmirx>;
- };
- power-domain@RK3588_PD_VI {
- reg = <RK3588_PD_VI>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru HCLK_VI_ROOT>,
- <&cru PCLK_VI_ROOT>,
- <&cru HCLK_ISP0>,
- <&cru ACLK_ISP0>,
- <&cru HCLK_VICAP>,
- <&cru ACLK_VICAP>;
- pm_qos = <&qos_isp0_mro>,
- <&qos_isp0_mwo>,
- <&qos_vicap_m0>,
- <&qos_vicap_m1>;
-
- power-domain@RK3588_PD_ISP1 {
- reg = <RK3588_PD_ISP1>;
- clocks = <&cru HCLK_ISP1>,
- <&cru ACLK_ISP1>,
- <&cru HCLK_VI_ROOT>,
- <&cru PCLK_VI_ROOT>;
- pm_qos = <&qos_isp1_mwo>,
- <&qos_isp1_mro>;
- };
- power-domain@RK3588_PD_FEC {
- reg = <RK3588_PD_FEC>;
- clocks = <&cru HCLK_FISHEYE0>,
- <&cru ACLK_FISHEYE0>,
- <&cru HCLK_FISHEYE1>,
- <&cru ACLK_FISHEYE1>,
- <&cru PCLK_VI_ROOT>;
- pm_qos = <&qos_fisheye0>,
- <&qos_fisheye1>;
- };
- };
- power-domain@RK3588_PD_RGA31 {
- reg = <RK3588_PD_RGA31>;
- clocks = <&cru HCLK_RGA3_1>,
- <&cru ACLK_RGA3_1>;
- pm_qos = <&qos_rga3_1>;
- };
- power-domain@RK3588_PD_USB {
- reg = <RK3588_PD_USB>;
- clocks = <&cru PCLK_PHP_ROOT>,
- <&cru ACLK_USB_ROOT>,
- <&cru HCLK_USB_ROOT>,
- <&cru HCLK_HOST0>,
- <&cru HCLK_HOST_ARB0>,
- <&cru HCLK_HOST1>,
- <&cru HCLK_HOST_ARB1>;
- pm_qos = <&qos_usb3_0>,
- <&qos_usb3_1>,
- <&qos_usb2host_0>,
- <&qos_usb2host_1>;
- };
- power-domain@RK3588_PD_GMAC {
- reg = <RK3588_PD_GMAC>;
- clocks = <&cru PCLK_PHP_ROOT>,
- <&cru ACLK_PCIE_ROOT>,
- <&cru ACLK_PHP_ROOT>;
- };
- power-domain@RK3588_PD_PCIE {
- reg = <RK3588_PD_PCIE>;
- clocks = <&cru PCLK_PHP_ROOT>,
- <&cru ACLK_PCIE_ROOT>,
- <&cru ACLK_PHP_ROOT>;
- };
- power-domain@RK3588_PD_SDIO {
- reg = <RK3588_PD_SDIO>;
- clocks = <&cru HCLK_SDIO>,
- <&cru HCLK_NVM_ROOT>;
- pm_qos = <&qos_sdio>;
- };
- power-domain@RK3588_PD_AUDIO {
- reg = <RK3588_PD_AUDIO>;
- clocks = <&cru HCLK_AUDIO_ROOT>,
- <&cru PCLK_AUDIO_ROOT>;
- };
- power-domain@RK3588_PD_SDMMC {
- reg = <RK3588_PD_SDMMC>;
- pm_qos = <&qos_sdmmc>;
- };
- };
- };
-
- pvtm@fda40000 {
- compatible = "rockchip,rk3588-bigcore0-pvtm";
- reg = <0x0 0xfda40000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- pvtm@0 {
- reg = <0>;
- clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>;
- clock-names = "clk", "pclk";
- };
- };
-
- pvtm@fda50000 {
- compatible = "rockchip,rk3588-bigcore1-pvtm";
- reg = <0x0 0xfda50000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- pvtm@1 {
- reg = <1>;
- clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>;
- clock-names = "clk", "pclk";
- };
- };
-
- pvtm@fda60000 {
- compatible = "rockchip,rk3588-litcore-pvtm";
- reg = <0x0 0xfda60000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- pvtm@2 {
- reg = <2>;
- clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>;
- clock-names = "clk", "pclk";
- };
- };
-
- pvtm@fdaf0000 {
- compatible = "rockchip,rk3588-npu-pvtm";
- reg = <0x0 0xfdaf0000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- pvtm@3 {
- reg = <3>;
- clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>;
- clock-names = "clk", "pclk";
- resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
- reset-names = "rts", "rst-p";
- };
- };
-
- pvtm@fdb30000 {
- compatible = "rockchip,rk3588-gpu-pvtm";
- reg = <0x0 0xfdb30000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- pvtm@4 {
- reg = <4>;
- clocks = <&cru CLK_GPU_PVTM>;
- clock-names = "clk";
- resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
- reset-names = "rts", "rst-p";
- };
- };
-
- rknpu: npu@fdab0000 {
- compatible = "rockchip,rk3588-rknpu";
- reg = <0x0 0xfdab0000 0x0 0x10000>,
- <0x0 0xfdac0000 0x0 0x10000>,
- <0x0 0xfdad0000 0x0 0x10000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
- clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>,
- <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
- <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
- <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>;
- clock-names = "clk_npu", "aclk0",
- "aclk1", "aclk2",
- "hclk0", "hclk1",
- "hclk2", "pclk";
- assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
- assigned-clock-rates = <200000000>;
- resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>,
- <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
- reset-names = "srst_a0", "srst_a1", "srst_a2",
- "srst_h0", "srst_h1", "srst_h2";
- power-domains = <&power RK3588_PD_NPUTOP>,
- <&power RK3588_PD_NPU1>,
- <&power RK3588_PD_NPU2>;
- power-domain-names = "npu0", "npu1", "npu2";
- operating-points-v2 = <&npu_opp_table>;
- iommus = <&rknpu_mmu>;
- status = "disabled";
- };
-
- npu_opp_table: npu-opp-table {
- compatible = "operating-points-v2";
-
- nvmem-cells = <&npu_leakage>;
- nvmem-cell-names = "leakage";
-
- rockchip,pvtm-voltage-sel = <
- 0 815 0
- 816 835 1
- 836 860 2
- 861 885 3
- 886 910 4
- 911 9999 5
- >;
- rockchip,pvtm-pvtpll;
- rockchip,pvtm-offset = <0x50>;
- rockchip,pvtm-sample-time = <1100>;
- rockchip,pvtm-freq = <800000>;
- rockchip,pvtm-volt = <750000>;
- rockchip,pvtm-ref-temp = <25>;
- rockchip,pvtm-temp-prop = <(-113) (-113)>;
- rockchip,pvtm-thermal-zone = "npu-thermal";
-
- clocks = <&cru PCLK_NPU_GRF>;
- clock-names = "pclk";
- rockchip,grf = <&npu_grf>;
- volt-mem-read-margin = <
- 855000 1
- 765000 2
- 675000 3
- 495000 4
- >;
- low-volt-read-margin = <4>;
- intermediate-threshold-freq = <500000>; /* KHz*/
- rockchip,init-freq = <1000000>; /* KHz */
-
- rockchip,temp-hysteresis = <5000>;
- rockchip,low-temp = <10000>;
- rockchip,low-temp-min-volt = <750000>;
- rockchip,high-temp = <85000>;
- rockchip,high-temp-max-freq = <800000>;
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L1 = <687500 687500 850000>,
- <687500 687500 850000>;
- opp-microvolt-L2 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L3 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L4 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L5 = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L1 = <687500 687500 850000>,
- <687500 687500 850000>;
- opp-microvolt-L2 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L3 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L4 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L5 = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L1 = <687500 687500 850000>,
- <687500 687500 850000>;
- opp-microvolt-L2 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L3 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L4 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L5 = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L1 = <687500 687500 850000>,
- <687500 687500 850000>;
- opp-microvolt-L2 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L3 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L4 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L5 = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <700000 700000 850000>,
- <700000 700000 850000>;
- opp-microvolt-L3 = <687500 687500 850000>,
- <687500 687500 850000>;
- opp-microvolt-L4 = <675000 675000 850000>,
- <675000 675000 850000>;
- opp-microvolt-L5 = <675000 675000 850000>,
- <675000 675000 850000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <750000 750000 850000>,
- <750000 750000 850000>;
- opp-microvolt-L2 = <737500 737500 850000>,
- <737500 737500 850000>;
- opp-microvolt-L3 = <725000 725000 850000>,
- <725000 725000 850000>;
- opp-microvolt-L4 = <712500 712500 850000>,
- <712500 712500 850000>;
- opp-microvolt-L5 = <700000 700000 850000>,
- <700000 700000 850000>;
- };
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = <800000 800000 850000>,
- <800000 800000 850000>;
- opp-microvolt-L1 = <787500 787500 850000>,
- <787500 787500 850000>;
- opp-microvolt-L2 = <775000 775000 850000>,
- <775000 775000 850000>;
- opp-microvolt-L3 = <762500 762500 850000>,
- <762500 762500 850000>;
- opp-microvolt-L4 = <750000 750000 850000>,
- <750000 750000 850000>;
- opp-microvolt-L5 = <737500 737500 850000>,
- <737500 737500 850000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <850000 850000 850000>,
- <850000 850000 850000>;
- opp-microvolt-L1 = <837500 837500 850000>,
- <837500 837500 850000>;
- opp-microvolt-L2 = <825000 825000 850000>,
- <825000 825000 850000>;
- opp-microvolt-L3 = <812500 812500 850000>,
- <812500 812500 850000>;
- opp-microvolt-L4 = <800000 800000 850000>,
- <800000 800000 850000>;
- opp-microvolt-L5 = <787500 787500 850000>,
- <787500 787500 850000>;
- };
- };
-
- rknpu_mmu: iommu@fdab9000 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdab9000 0x0 0x100>,
- <0x0 0xfdaba000 0x0 0x100>,
- <0x0 0xfdaca000 0x0 0x100>,
- <0x0 0xfdada000 0x0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
- clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
- <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>;
- clock-names = "aclk0", "aclk1", "aclk2",
- "iface0", "iface1", "iface2";
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- vepu: vepu@fdb50000 {
- compatible = "rockchip,vpu-encoder-v2";
- reg = <0x0 0xfdb50000 0x0 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_vepu";
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <594000000>, <0>;
- assigned-clocks = <&cru ACLK_VPU>;
- assigned-clock-rates = <594000000>;
- resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
- reset-names = "shared_video_a", "shared_video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&vdpu_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <0>;
- rockchip,resetgroup-node = <0>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- vdpu: vdpu@fdb50400 {
- compatible = "rockchip,vpu-decoder-v2";
- reg = <0x0 0xfdb50400 0x0 0x400>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_vdpu";
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <594000000>, <0>;
- assigned-clocks = <&cru ACLK_VPU>;
- assigned-clock-rates = <594000000>;
- resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
- reset-names = "shared_video_a", "shared_video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&vdpu_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <0>;
- rockchip,resetgroup-node = <0>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- vdpu_mmu: iommu@fdb50800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdb50800 0x0 0x40>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_vdpu_mmu";
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VDPU>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- avsd: avsd-plus@fdb51000 {
- compatible = "rockchip,avs-plus-decoder";
- reg = <0x0 0xfdb51000 0x0 0x200>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_avsd";
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
- reset-names = "shared_video_a", "shared_video_h";
- iommus = <&vdpu_mmu>;
- power-domains = <&power RK3588_PD_VDPU>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <0>;
- rockchip,resetgroup-node = <0>;
- status = "disabled";
- };
-
- rga3_core0: rga@fdb60000 {
- compatible = "rockchip,rga3_core0";
- reg = <0x0 0xfdb60000 0x0 0x1000>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rga3_core0_irq";
- clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>;
- clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0";
- power-domains = <&power RK3588_PD_RGA30>;
- iommus = <&rga3_0_mmu>;
- status = "disabled";
- };
-
- rga3_0_mmu: iommu@fdb60f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdb60f00 0x0 0x100>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rga3_0_mmu";
- clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_RGA30>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- rga3_core1: rga@fdb70000 {
- compatible = "rockchip,rga3_core1";
- reg = <0x0 0xfdb70000 0x0 0x1000>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rga3_core1_irq";
- clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>;
- clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1";
- power-domains = <&power RK3588_PD_RGA31>;
- iommus = <&rga3_1_mmu>;
- status = "disabled";
- };
-
- rga3_1_mmu: iommu@fdb70f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdb70f00 0x0 0x100>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rga3_1_mmu";
- clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_RGA31>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- rga2: rga@fdb80000 {
- compatible = "rockchip,rga2_core0";
- reg = <0x0 0xfdb80000 0x0 0x1000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rga2_irq";
- clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
- clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- jpegd: jpegd@fdb90000 {
- compatible = "rockchip,rkv-jpeg-decoder-v1";
- reg = <0x0 0xfdb90000 0x0 0x400>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpegd";
- clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <600000000>, <0>;
- assigned-clocks = <&cru ACLK_JPEG_DECODER>;
- assigned-clock-rates = <600000000>;
- resets = <&cru SRST_A_JPEG_DECODER>, <&cru SRST_H_JPEG_DECODER>;
- reset-names = "video_a", "video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&jpegd_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <1>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- jpegd_mmu: iommu@fdb90480 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdb90480 0x0 0x40>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpegd_mmu";
- clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VDPU>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- jpege0: jpege-core@fdba0000 {
- compatible = "rockchip,vpu-jpege-core";
- reg = <0x0 0xfdba0000 0x0 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege0";
- clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <594000000>, <0>;
- assigned-clocks = <&cru ACLK_JPEG_ENCODER0>;
- assigned-clock-rates = <594000000>;
- resets = <&cru SRST_A_JPEG_ENCODER0>, <&cru SRST_H_JPEG_ENCODER0>;
- reset-names = "video_a", "video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&jpege0_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <2>;
- rockchip,ccu = <&jpege_ccu>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- jpege0_mmu: iommu@fdba0800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdba0800 0x0 0x40>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege0_mmu";
- clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VDPU>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- jpege1: jpege-core@fdba4000 {
- compatible = "rockchip,vpu-jpege-core";
- reg = <0x0 0xfdba4000 0x0 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege1";
- clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <594000000>, <0>;
- assigned-clocks = <&cru ACLK_JPEG_ENCODER1>;
- assigned-clock-rates = <594000000>;
- resets = <&cru SRST_A_JPEG_ENCODER1>, <&cru SRST_H_JPEG_ENCODER1>;
- reset-names = "video_a", "video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&jpege1_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <2>;
- rockchip,ccu = <&jpege_ccu>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- jpege1_mmu: iommu@fdba4800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdba4800 0x0 0x40>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege1_mmu";
- clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VDPU>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- jpege2: jpege-core@fdba8000 {
- compatible = "rockchip,vpu-jpege-core";
- reg = <0x0 0xfdba8000 0x0 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege2";
- clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <594000000>, <0>;
- assigned-clocks = <&cru ACLK_JPEG_ENCODER2>;
- assigned-clock-rates = <594000000>;
- resets = <&cru SRST_A_JPEG_ENCODER2>, <&cru SRST_H_JPEG_ENCODER2>;
- reset-names = "video_a", "video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&jpege2_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <2>;
- rockchip,ccu = <&jpege_ccu>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- jpege2_mmu: iommu@fdba8800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdba8800 0x0 0x40>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege2_mmu";
- clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VDPU>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- jpege3: jpege-core@fdbac000 {
- compatible = "rockchip,vpu-jpege-core";
- reg = <0x0 0xfdbac000 0x0 0x400>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege3";
- clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <594000000>, <0>;
- assigned-clocks = <&cru ACLK_JPEG_ENCODER3>;
- assigned-clock-rates = <594000000>;
- resets = <&cru SRST_A_JPEG_ENCODER3>, <&cru SRST_H_JPEG_ENCODER3>;
- reset-names = "video_a", "video_h";
- rockchip,skip-pmu-idle-request;
- iommus = <&jpege3_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <2>;
- rockchip,ccu = <&jpege_ccu>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- jpege3_mmu: iommu@fdbac800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdbac800 0x0 0x40>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_jpege3_mmu";
- clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VDPU>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- iep: iep@fdbb0000 {
- compatible = "rockchip,iep-v2";
- reg = <0x0 0xfdbb0000 0x0 0x500>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_iep";
- clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>;
- clock-names = "aclk", "hclk", "sclk";
- resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>;
- reset-names = "rst_a", "rst_h", "rst_s";
- rockchip,skip-pmu-idle-request;
- power-domains = <&power RK3588_PD_VDPU>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <6>;
- iommus = <&iep_mmu>;
- status = "disabled";
- };
-
- iep_mmu: iommu@fdbb0800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdbb0800 0x0 0x100>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_iep_mmu";
- clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_VDPU>;
- status = "disabled";
- };
-
- rkvenc0: rkvenc-core@fdbd0000 {
- compatible = "rockchip,rkv-encoder-v2-core";
- reg = <0x0 0xfdbd0000 0x0 0x6000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvenc0";
- clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- rockchip,normal-rates = <600000000>, <0>, <800000000>;
- assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
- assigned-clock-rates = <600000000>, <800000000>;
- resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>;
- reset-names = "video_a", "video_h", "video_core";
- rockchip,skip-pmu-idle-request;
- iommus = <&rkvenc0_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,ccu = <&rkvenc_ccu>;
- rockchip,taskqueue-node = <7>;
- rockchip,task-capacity = <8>;
- power-domains = <&power RK3588_PD_VENC0>;
- status = "disabled";
- };
-
- rkvenc0_mmu: iommu@fdbdf000 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
- clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
- clock-names = "aclk", "iface";
- rockchip,disable-mmu-reset;
- rockchip,enable-cmd-retry;
- rockchip,shootdown-entire;
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_VENC0>;
- status = "disabled";
- };
-
- rkvenc1: rkvenc-core@fdbe0000 {
- compatible = "rockchip,rkv-encoder-v2-core";
- reg = <0x0 0xfdbe0000 0x0 0x6000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvenc1";
- clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- rockchip,normal-rates = <600000000>, <0>, <800000000>;
- assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
- assigned-clock-rates = <600000000>, <800000000>;
- resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>;
- reset-names = "video_a", "video_h", "video_core";
- rockchip,skip-pmu-idle-request;
- iommus = <&rkvenc1_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,ccu = <&rkvenc_ccu>;
- rockchip,taskqueue-node = <7>;
- rockchip,task-capacity = <8>;
- power-domains = <&power RK3588_PD_VENC1>;
- status = "disabled";
- };
-
- rkvenc1_mmu: iommu@fdbef000 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
- clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
- lock-names = "aclk", "iface";
- rockchip,disable-mmu-reset;
- rockchip,enable-cmd-retry;
- rockchip,shootdown-entire;
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_VENC1>;
- status = "disabled";
- };
-
- rkvdec_ccu: rkvdec-ccu@fdc30000 {
- compatible = "rockchip,rkv-decoder-v2-ccu";
- reg = <0x0 0xfdc30000 0x0 0x100>;
- reg-names = "ccu";
- clocks = <&cru ACLK_RKVDEC_CCU>;
- clock-names = "aclk_ccu";
- assigned-clocks = <&cru ACLK_RKVDEC_CCU>;
- assigned-clock-rates = <600000000>;
- resets = <&cru SRST_A_RKVDEC_CCU>;
- reset-names = "video_ccu";
- rockchip,skip-pmu-idle-request;
- power-domains = <&power RK3588_PD_RKVDEC0>;
- status = "disabled";
- };
-
- rkvdec0: rkvdec-core@fdc38000 {
- compatible = "rockchip,rkv-decoder-v2";
- reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>;
- reg-names = "regs", "link";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvdec0";
- clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
- <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
- "clk_cabac", "clk_hevc_cabac";
- rockchip,normal-rates = <800000000>, <0>, <600000000>,
- <600000000>, <1000000000>;
- assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
- <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
- assigned-clock-rates = <800000000>, <600000000>,
- <600000000>, <1000000000>;
- resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CORE>,
- <&cru SRST_RKVDEC0_CA>, <&cru SRST_RKVDEC0_HEVC_CA>;
- reset-names = "video_a", "video_h", "video_core",
- "video_cabac", "video_hevc_cabac";
- rockchip,skip-pmu-idle-request;
- iommus = <&rkvdec0_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,ccu = <&rkvdec_ccu>;
- rockchip,core-mask = <0x00010001>;
- rockchip,taskqueue-node = <9>;
- rockchip,sram = <&rkvdec0_sram>;
- /* rcb_iova: start and size 1M@4095M */
- rockchip,rcb-iova = <0xFFF00000 0x100000>;
- rockchip,rcb-min-width = <512>;
- power-domains = <&power RK3588_PD_RKVDEC0>;
- status = "disabled";
- };
-
- rkvdec0_mmu: iommu@fdc38700 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvdec0_mmu";
- clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
- clock-names = "aclk", "iface";
- rockchip,disable-mmu-reset;
- rockchip,enable-cmd-retry;
- rockchip,shootdown-entire;
- rockchip,master-handle-irq;
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_RKVDEC0>;
- status = "disabled";
- };
-
- rkvdec1: rkvdec-core@fdc48000 {
- compatible = "rockchip,rkv-decoder-v2";
- reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>;
- reg-names = "regs", "link";
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvdec1";
- clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
- <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
- "clk_cabac", "clk_hevc_cabac";
- rockchip,normal-rates = <800000000>, <0>, <600000000>,
- <600000000>, <1000000000>;
- assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
- <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
- assigned-clock-rates = <800000000>, <600000000>,
- <600000000>, <1000000000>;
- resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CORE>,
- <&cru SRST_RKVDEC1_CA>, <&cru SRST_RKVDEC1_HEVC_CA>;
- reset-names = "video_a", "video_h", "video_core",
- "video_cabac", "video_hevc_cabac";
- rockchip,skip-pmu-idle-request;
- iommus = <&rkvdec1_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,ccu = <&rkvdec_ccu>;
- rockchip,core-mask = <0x00020002>;
- rockchip,taskqueue-node = <9>;
- rockchip,sram = <&rkvdec1_sram>;
- /* rcb_iova: start and size 1M@4094M */
- rockchip,rcb-iova = <0xFFE00000 0x100000>;
- rockchip,rcb-min-width = <512>;
- power-domains = <&power RK3588_PD_RKVDEC1>;
- status = "disabled";
- };
-
- rkvdec1_mmu: iommu@fdc48700 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_rkvdec1_mmu";
- clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
- clock-names = "aclk", "iface";
- rockchip,disable-mmu-reset;
- rockchip,enable-cmd-retry;
- rockchip,shootdown-entire;
- rockchip,master-handle-irq;
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_RKVDEC1>;
- status = "disabled";
- };
-
- av1d: av1d@fdc70000 {
- compatible = "rockchip,av1-decoder";
- reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>,
- <0x0 0xfdc90000 0x0 0x400>;
- reg-names = "vcd", "cache", "afbc";
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_av1d", "irq_cache", "irq_afbc";
- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <400000000>, <400000000>;
- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- assigned-clock-rates = <400000000>, <400000000>;
- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>;
- reset-names = "video_a", "video_h";
- iommus = <&av1d_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <11>;
- power-domains = <&power RK3588_PD_AV1>;
- status = "disabled";
- };
-
- av1d_mmu: iommu@fdca0000 {
- compatible = "rockchip,iommu-av1";
- reg = <0x0 0xfdca0000 0x0 0x600>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_av1d_mmu";
- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_AV1>;
- status = "disabled";
- };
-
- rkisp_unite: rkisp-unite@fdcb0000 {
- compatible = "rockchip,rk3588-rkisp-unite";
- reg = <0x0 0xfdcb0000 0x0 0x10000>,
- <0x0 0xfdcc0000 0x0 0x10000>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
- clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
- <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
- <&cru CLK_ISP0_CORE_VICAP>, <&cru ACLK_ISP1>,
- <&cru HCLK_ISP1>, <&cru CLK_ISP1_CORE>,
- <&cru CLK_ISP1_CORE_MARVIN>, <&cru CLK_ISP1_CORE_VICAP>;
- clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0",
- "clk_isp_core_marvin0", "clk_isp_core_vicap0",
- "aclk_isp1", "hclk_isp1", "clk_isp_core1",
- "clk_isp_core_marvin1", "clk_isp_core_vicap1";
- power-domains = <&power RK3588_PD_ISP1>;
- iommus = <&rkisp_unite_mmu>;
- status = "disabled";
- };
-
- rkisp0: rkisp@fdcb0000 {
- compatible = "rockchip,rk3588-rkisp";
- reg = <0x0 0xfdcb0000 0x0 0x7f00>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
- clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
- <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
- <&cru CLK_ISP0_CORE_VICAP>;
- clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
- "clk_isp_core_marvin", "clk_isp_core_vicap";
- power-domains = <&power RK3588_PD_VI>;
- iommus = <&isp0_mmu>;
- status = "disabled";
- };
-
- rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>;
- interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp0_mmu", "isp1_mmu";
- clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
- <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
- clock-names = "aclk0", "iface0", "aclk1", "iface1";
- power-domains = <&power RK3588_PD_ISP1>;
- #iommu-cells = <0>;
- rockchip,disable-mmu-reset;
- status = "disabled";
- };
-
- isp0_mmu: iommu@fdcb7f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdcb7f00 0x0 0x100>;
- interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp0_mmu";
- clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VI>;
- #iommu-cells = <0>;
- rockchip,disable-mmu-reset;
- status = "disabled";
- };
-
- rkisp1: rkisp@fdcc0000 {
- compatible = "rockchip,rk3588-rkisp";
- reg = <0x0 0xfdcc0000 0x0 0x7f00>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
- clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
- <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>,
- <&cru CLK_ISP1_CORE_VICAP>;
- clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
- "clk_isp_core_marvin", "clk_isp_core_vicap";
- power-domains = <&power RK3588_PD_ISP1>;
- iommus = <&isp1_mmu>;
- status = "disabled";
- };
-
- isp1_mmu: iommu@fdcc7f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdcc7f00 0x0 0x100>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp1_mmu";
- clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_ISP1>;
- #iommu-cells = <0>;
- rockchip,disable-mmu-reset;
- status = "disabled";
- };
-
- rkispp0: rkispp@fdcd0000 {
- compatible = "rockchip,rk3588-rkispp";
- reg = <0x0 0xfdcd0000 0x0 0x0f00>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "fec_irq";
- clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>,
- <&cru CLK_FISHEYE0_CORE>;
- clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
- power-domains = <&power RK3588_PD_FEC>;
- iommus = <&fec0_mmu>;
- status = "disabled";
- };
-
- fec0_mmu: iommu@fdcd0f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdcd0f00 0x0 0x100>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "fec0_mmu";
- clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, <&cru CLK_FISHEYE0_CORE>;
- clock-names = "aclk", "iface", "pclk";
- power-domains = <&power RK3588_PD_FEC>;
- #iommu-cells = <0>;
- rockchip,disable-mmu-reset;
- status = "disabled";
- };
-
- rkispp1: rkispp@fdcd8000 {
- compatible = "rockchip,rk3588-rkispp";
- reg = <0x0 0xfdcd8000 0x0 0x0f00>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "fec_irq";
- clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>,
- <&cru CLK_FISHEYE1_CORE>;
- clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
- power-domains = <&power RK3588_PD_FEC>;
- iommus = <&fec1_mmu>;
- status = "disabled";
- };
-
- fec1_mmu: iommu@fdcd8f00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdcd8f00 0x0 0x100>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "fec1_mmu";
- clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, <&cru CLK_FISHEYE1_CORE>;
- clock-names = "aclk", "iface", "pclk";
- power-domains = <&power RK3588_PD_FEC>;
- #iommu-cells = <0>;
- rockchip,disable-mmu-reset;
- status = "disabled";
- };
-
- rkcif: rkcif@fdce0000 {
- compatible = "rockchip,rk3588-cif";
- reg = <0x0 0xfdce0000 0x0 0x800>;
- reg-names = "cif_regs";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cif-intr";
- clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>;
- clock-names = "aclk_cif", "hclk_cif", "dclk_cif";
- resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>;
- reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d";
- assigned-clocks = <&cru DCLK_VICAP>;
- assigned-clock-rates = <600000000>;
- power-domains = <&power RK3588_PD_VI>;
- rockchip,grf = <&sys_grf>;
- iommus = <&rkcif_mmu>;
- status = "disabled";
- };
-
- rkcif_mmu: iommu@fdce0800 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdce0800 0x0 0x100>,
- <0x0 0xfdce0900 0x0 0x100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cif_mmu";
- clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3588_PD_VI>;
- rockchip,disable-mmu-reset;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- mipi0_csi2: mipi0-csi2@fdd10000 {
- compatible = "rockchip,rk3588-mipi-csi2";
- reg = <0x0 0xfdd10000 0x0 0x10000>;
- reg-names = "csihost_regs";
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "csi-intr1", "csi-intr2";
- clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>;
- clock-names = "pclk_csi2host", "iclk_csi2host";
- resets = <&cru SRST_P_CSI_HOST_0>, <&cru SRST_CSIHOST0_VICAP>;
- reset-names = "srst_csihost_p", "srst_csihost_vicap";
- status = "disabled";
- };
-
- mipi1_csi2: mipi1-csi2@fdd20000 {
- compatible = "rockchip,rk3588-mipi-csi2";
- reg = <0x0 0xfdd20000 0x0 0x10000>;
- reg-names = "csihost_regs";
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "csi-intr1", "csi-intr2";
- clocks = <&cru PCLK_CSI_HOST_1>, <&cru ICLK_CSIHOST1>;
- clock-names = "pclk_csi2host", "iclk_csi2host";
- resets = <&cru SRST_P_CSI_HOST_1>, <&cru SRST_CSIHOST1_VICAP>;
- reset-names = "srst_csihost_p", "srst_csihost_vicap";
- status = "disabled";
- };
-
- mipi2_csi2: mipi2-csi2@fdd30000 {
- compatible = "rockchip,rk3588-mipi-csi2";
- reg = <0x0 0xfdd30000 0x0 0x10000>;
- reg-names = "csihost_regs";
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "csi-intr1", "csi-intr2";
- clocks = <&cru PCLK_CSI_HOST_2>;
- clock-names = "pclk_csi2host";
- resets = <&cru SRST_P_CSI_HOST_2>, <&cru SRST_CSIHOST2_VICAP>;
- reset-names = "srst_csihost_p", "srst_csihost_vicap";
- status = "disabled";
- };
-
- mipi3_csi2: mipi3-csi2@fdd40000 {
- compatible = "rockchip,rk3588-mipi-csi2";
- reg = <0x0 0xfdd40000 0x0 0x10000>;
- reg-names = "csihost_regs";
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "csi-intr1", "csi-intr2";
- clocks = <&cru PCLK_CSI_HOST_3>;
- clock-names = "pclk_csi2host";
- resets = <&cru SRST_P_CSI_HOST_3>, <&cru SRST_CSIHOST3_VICAP>;
- reset-names = "srst_csihost_p", "srst_csihost_vicap";
- status = "disabled";
- };
-
- vop: vop@fdd90000 {
- compatible = "rockchip,rk3588-vop";
- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
- reg-names = "regs", "gamma_lut";
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>,
- <&cru HCLK_VOP>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>,
- <&cru DCLK_VOP0_SRC>,
- <&cru DCLK_VOP1_SRC>,
- <&cru DCLK_VOP2_SRC>;
- clock-names = "aclk_vop",
- "hclk_vop",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
- "pclk_vop",
- "dclk_src_vp0",
- "dclk_src_vp1",
- "dclk_src_vp2";
- assigned-clocks = <&cru ACLK_VOP>;
- assigned-clock-rates = <800000000>;
- resets = <&cru SRST_A_VOP>,
- <&cru SRST_H_VOP>,
- <&cru SRST_D_VOP0>,
- <&cru SRST_D_VOP1>,
- <&cru SRST_D_VOP2>,
- <&cru SRST_D_VOP3>;
- reset-names = "axi",
- "ahb",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3";
- iommus = <&vop_mmu>;
- power-domains = <&power RK3588_PD_VOP>;
- rockchip,grf = <&sys_grf>;
- rockchip,vop-grf = <&vop_grf>;
- rockchip,vo1-grf = <&vo1_grf>;
- rockchip,pmu = <&pmu>;
-
- status = "disabled";
-
- vop_out: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vp0: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- vp0_out_dp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dp0_in_vp0>;
- };
-
- vp0_out_edp0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&edp0_in_vp0>;
- };
-
- vp0_out_hdmi0: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi0_in_vp0>;
- };
- };
-
- vp1: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- vp1_out_dp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dp0_in_vp1>;
- };
-
- vp1_out_edp0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&edp0_in_vp1>;
- };
-
- vp1_out_hdmi0: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi0_in_vp1>;
- };
- };
-
- vp2: port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- assigned-clocks = <&cru DCLK_VOP2_SRC>;
- assigned-clock-parents = <&cru PLL_V0PLL>;
-
- vp2_out_dp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dp0_in_vp2>;
- };
-
- vp2_out_edp0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&edp0_in_vp2>;
- };
-
- vp2_out_hdmi0: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi0_in_vp2>;
- };
-
- vp2_out_dsi0: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&dsi0_in_vp2>;
- };
-
- vp2_out_dsi1: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&dsi1_in_vp2>;
- };
- };
-
- vp3: port@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- vp3_out_dsi0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi0_in_vp3>;
- };
-
- vp3_out_dsi1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dsi1_in_vp3>;
- };
-
- vp3_out_rgb: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&rgb_in_vp3>;
- };
- };
- };
- };
-
- vop_mmu: iommu@fdd97e00 {
- compatible = "rockchip,iommu-v2";
- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- rockchip,disable-device-link-resume;
- rockchip,shootdown-entire;
- status = "disabled";
- };
-
- spdif_tx2: spdif-tx@fddb0000 {
- compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
- reg = <0x0 0xfddb0000 0x0 0x1000>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac1 6>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
- assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- power-domains = <&power RK3588_PD_VO0>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s4_8ch: i2s@fddc0000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddc0000 0x0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 0>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO0>;
- resets = <&cru SRST_M_I2S4_8CH_TX>;
- reset-names = "tx-m";
- rockchip,playback-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_tx3: spdif-tx@fdde0000 {
- compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
- reg = <0x0 0xfdde0000 0x0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac1 7>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
- assigned-clocks = <&cru CLK_SPDIF3_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- power-domains = <&power RK3588_PD_VO1>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s5_8ch: i2s@fddf0000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddf0000 0x0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 2>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S5_8CH_TX>;
- reset-names = "tx-m";
- rockchip,always-on;
- rockchip,hdmi-path;
- rockchip,playback-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s9_8ch: i2s@fddfc000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddfc000 0x0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 23>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S9_8CH_RX>;
- reset-names = "rx-m";
- rockchip,capture-only;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_rx0: spdif-rx@fde08000 {
- compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
- reg = <0x0 0xfde08000 0x0 0x1000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>;
- clock-names = "mclk", "hclk";
- assigned-clocks = <&cru MCLK_SPDIFRX0>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac0 21>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_SPDIFRX0>;
- reset-names = "spdifrx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- dsi0: dsi@fde20000 {
- compatible = "rockchip,rk3588-mipi-dsi2";
- reg = <0x0 0xfde20000 0x0 0x10000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
- clock-names = "pclk", "sys_clk";
- resets = <&cru SRST_P_DSIHOST0>;
- reset-names = "apb";
- power-domains = <&power RK3588_PD_VOP>;
- phys = <&mipi_dcphy0>;
- phy-names = "dcphy";
- rockchip,grf = <&vop_grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_in_vp2: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp2_out_dsi0>;
- status = "disabled";
- };
-
- dsi0_in_vp3: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp3_out_dsi0>;
- status = "disabled";
- };
- };
- };
- };
-
- dsi1: dsi@fde30000 {
- compatible = "rockchip,rk3588-mipi-dsi2";
- reg = <0x0 0xfde30000 0x0 0x10000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
- clock-names = "pclk", "sys_clk";
- resets = <&cru SRST_P_DSIHOST1>;
- reset-names = "apb";
- power-domains = <&power RK3588_PD_VOP>;
- phys = <&mipi_dcphy1>;
- phy-names = "dcphy";
- rockchip,grf = <&vop_grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi1_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi1_in_vp2: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp2_out_dsi1>;
- status = "disabled";
- };
-
- dsi1_in_vp3: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp3_out_dsi1>;
- status = "disabled";
- };
- };
- };
- };
-
- hdcp0: hdcp@fde40000 {
- compatible = "rockchip,rk3588-hdcp";
- reg = <0x0 0xfde40000 0x0 0x80>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_HDCP0>, <&cru PCLK_HDCP0>,
- <&cru HCLK_HDCP0>, <&cru HCLK_HDCP_KEY0>,
- <&cru ACLK_TRNG0>, <&cru PCLK_TRNG0>;
- clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
- resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>,
- <&cru SRST_A_HDCP0>, <&cru SRST_H_HDCP_KEY0>,
- <&cru SRST_P_TRNG0>;
- reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
- power-domains = <&power RK3588_PD_VO0>;
- rockchip,vo-grf = <&vo0_grf>;
- status = "disabled";
- };
-
- dp0: dp@fde50000 {
- compatible = "rockchip,rk3588-dp";
- reg = <0x0 0xfde50000 0x0 0x4000>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
- <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_SPDIF2_DP0>,
- <&hclk_vo0>;
- clock-names = "apb", "aux", "i2s", "spdif", "hclk";
- assigned-clocks = <&cru CLK_AUX16M_0>;
- assigned-clock-rates = <16000000>;
- resets = <&cru SRST_DP0>;
- phys = <&usbdp_phy0_dp>;
- power-domains = <&power RK3588_PD_VO0>;
- #sound-dai-cells = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dp0_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dp0_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_dp0>;
- status = "disabled";
- };
-
- dp0_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_dp0>;
- status = "disabled";
- };
-
- dp0_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_dp0>;
- status = "disabled";
- };
- };
- };
- };
-
- hdcp1: hdcp@fde70000 {
- compatible = "rockchip,rk3588-hdcp";
- reg = <0x0 0xfde70000 0x0 0x80>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_HDCP1>, <&cru PCLK_HDCP1>,
- <&cru HCLK_HDCP1>, <&cru HCLK_HDCP_KEY1>,
- <&cru ACLK_TRNG1>, <&cru PCLK_TRNG1>;
- clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
- resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>,
- <&cru SRST_A_HDCP1>, <&cru SRST_H_HDCP_KEY1>,
- <&cru SRST_P_TRNG1>;
- reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
- power-domains = <&power RK3588_PD_VO1>;
- rockchip,vo-grf = <&vo1_grf>;
- status = "disabled";
- };
-
- hdmi0: hdmi@fde80000 {
- compatible = "rockchip,rk3588-dw-hdmi";
- reg = <0x0 0xfde80000 0x0 0x20000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMITX0>,
- <&cru CLK_HDMIHDP0>,
- <&cru CLK_HDMITX0_EARC>,
- <&cru CLK_HDMITX0_REF>,
- <&cru MCLK_I2S5_8CH_TX>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
- <&hclk_vo1>,
- <&hdptxphy_hdmi_clk0>;
- clock-names = "pclk",
- "hpd",
- "earc",
- "hdmitx_ref",
- "aud",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
- "hclk_vo1",
- "link_clk";
- resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
- reset-names = "ref", "hdp";
- power-domains = <&power RK3588_PD_VO1>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
- reg-io-width = <4>;
- rockchip,grf = <&sys_grf>;
- rockchip,vo1_grf = <&vo1_grf>;
- phys = <&hdptxphy_hdmi0>;
- phy-names = "hdmi";
- #sound-dai-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi0_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi0_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_hdmi0>;
- status = "disabled";
- };
-
- hdmi0_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_hdmi0>;
- status = "disabled";
- };
-
- hdmi0_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_hdmi0>;
- status = "disabled";
- };
- };
- };
- };
-
- edp0: edp@fdec0000 {
- compatible = "rockchip,rk3588-edp";
- reg = <0x0 0xfdec0000 0x0 0x1000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
- <&cru CLK_EDP0_200M>, <&hclk_vo1>;
- clock-names = "dp", "pclk", "spdif", "hclk";
- resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
- reset-names = "dp", "apb";
- phys = <&hdptxphy0>;
- phy-names = "dp";
- power-domains = <&power RK3588_PD_VO1>;
- rockchip,grf = <&vo1_grf>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp0_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp0_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_edp0>;
- status = "disabled";
- };
-
- edp0_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_edp0>;
- status = "disabled";
- };
-
- edp0_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_edp0>;
- status = "disabled";
- };
- };
- };
- };
-
- qos_gpu_m0: qos@fdf35000 {
- compatible = "syscon";
- reg = <0x0 0xfdf35000 0x0 0x20>;
- };
-
- qos_gpu_m1: qos@fdf35200 {
- compatible = "syscon";
- reg = <0x0 0xfdf35200 0x0 0x20>;
- };
-
- qos_gpu_m2: qos@fdf35400 {
- compatible = "syscon";
- reg = <0x0 0xfdf35400 0x0 0x20>;
- };
-
- qos_gpu_m3: qos@fdf35600 {
- compatible = "syscon";
- reg = <0x0 0xfdf35600 0x0 0x20>;
- };
-
- qos_rga3_1: qos@fdf36000 {
- compatible = "syscon";
- reg = <0x0 0xfdf36000 0x0 0x20>;
- };
-
- qos_sdio: qos@fdf39000 {
- compatible = "syscon";
- reg = <0x0 0xfdf39000 0x0 0x20>;
- };
-
- qos_sdmmc: qos@fdf3d800 {
- compatible = "syscon";
- reg = <0x0 0xfdf3d800 0x0 0x20>;
- };
-
- qos_usb3_1: qos@fdf3e000 {
- compatible = "syscon";
- reg = <0x0 0xfdf3e000 0x0 0x20>;
- };
-
- qos_usb3_0: qos@fdf3e200 {
- compatible = "syscon";
- reg = <0x0 0xfdf3e200 0x0 0x20>;
- };
-
- qos_usb2host_0: qos@fdf3e400 {
- compatible = "syscon";
- reg = <0x0 0xfdf3e400 0x0 0x20>;
- };
-
- qos_usb2host_1: qos@fdf3e600 {
- compatible = "syscon";
- reg = <0x0 0xfdf3e600 0x0 0x20>;
- };
-
- qos_fisheye0: qos@fdf40000 {
- compatible = "syscon";
- reg = <0x0 0xfdf40000 0x0 0x20>;
- };
-
- qos_fisheye1: qos@fdf40200 {
- compatible = "syscon";
- reg = <0x0 0xfdf40200 0x0 0x20>;
- };
-
- qos_isp0_mro: qos@fdf40400 {
- compatible = "syscon";
- reg = <0x0 0xfdf40400 0x0 0x20>;
- };
-
- qos_isp0_mwo: qos@fdf40500 {
- compatible = "syscon";
- reg = <0x0 0xfdf40500 0x0 0x20>;
- };
-
- qos_vicap_m0: qos@fdf40600 {
- compatible = "syscon";
- reg = <0x0 0xfdf40600 0x0 0x20>;
- };
-
- qos_vicap_m1: qos@fdf40800 {
- compatible = "syscon";
- reg = <0x0 0xfdf40800 0x0 0x20>;
- };
-
- qos_isp1_mwo: qos@fdf41000 {
- compatible = "syscon";
- reg = <0x0 0xfdf41000 0x0 0x20>;
- };
-
- qos_isp1_mro: qos@fdf41100 {
- compatible = "syscon";
- reg = <0x0 0xfdf41100 0x0 0x20>;
- };
-
- qos_rkvenc0_m0ro: qos@fdf60000 {
- compatible = "syscon";
- reg = <0x0 0xfdf60000 0x0 0x20>;
- };
-
- qos_rkvenc0_m1ro: qos@fdf60200 {
- compatible = "syscon";
- reg = <0x0 0xfdf60200 0x0 0x20>;
- };
-
- qos_rkvenc0_m2wo: qos@fdf60400 {
- compatible = "syscon";
- reg = <0x0 0xfdf60400 0x0 0x20>;
- };
-
- qos_rkvenc1_m0ro: qos@fdf61000 {
- compatible = "syscon";
- reg = <0x0 0xfdf61000 0x0 0x20>;
- };
-
- qos_rkvenc1_m1ro: qos@fdf61200 {
- compatible = "syscon";
- reg = <0x0 0xfdf61200 0x0 0x20>;
- };
-
- qos_rkvenc1_m2wo: qos@fdf61400 {
- compatible = "syscon";
- reg = <0x0 0xfdf61400 0x0 0x20>;
- };
-
- qos_rkvdec0: qos@fdf62000 {
- compatible = "syscon";
- reg = <0x0 0xfdf62000 0x0 0x20>;
- };
-
- qos_rkvdec1: qos@fdf63000 {
- compatible = "syscon";
- reg = <0x0 0xfdf63000 0x0 0x20>;
- };
-
- qos_av1: qos@fdf64000 {
- compatible = "syscon";
- reg = <0x0 0xfdf64000 0x0 0x20>;
- };
-
- qos_iep: qos@fdf66000 {
- compatible = "syscon";
- reg = <0x0 0xfdf66000 0x0 0x20>;
- };
-
- qos_jpeg_dec: qos@fdf66200 {
- compatible = "syscon";
- reg = <0x0 0xfdf66200 0x0 0x20>;
- };
-
- qos_jpeg_enc0: qos@fdf66400 {
- compatible = "syscon";
- reg = <0x0 0xfdf66400 0x0 0x20>;
- };
-
- qos_jpeg_enc1: qos@fdf66600 {
- compatible = "syscon";
- reg = <0x0 0xfdf66600 0x0 0x20>;
- };
-
- qos_jpeg_enc2: qos@fdf66800 {
- compatible = "syscon";
- reg = <0x0 0xfdf66800 0x0 0x20>;
- };
-
- qos_jpeg_enc3: qos@fdf66a00 {
- compatible = "syscon";
- reg = <0x0 0xfdf66a00 0x0 0x20>;
- };
-
- qos_rga2_mro: qos@fdf66c00 {
- compatible = "syscon";
- reg = <0x0 0xfdf66c00 0x0 0x20>;
- };
-
- qos_rga2_mwo: qos@fdf66e00 {
- compatible = "syscon";
- reg = <0x0 0xfdf66e00 0x0 0x20>;
- };
-
- qos_rga3_0: qos@fdf67000 {
- compatible = "syscon";
- reg = <0x0 0xfdf67000 0x0 0x20>;
- };
-
- qos_vdpu: qos@fdf67200 {
- compatible = "syscon";
- reg = <0x0 0xfdf67200 0x0 0x20>;
- };
-
- qos_npu1: qos@fdf70000 {
- compatible = "syscon";
- reg = <0x0 0xfdf70000 0x0 0x20>;
- };
-
- qos_npu2: qos@fdf71000 {
- compatible = "syscon";
- reg = <0x0 0xfdf71000 0x0 0x20>;
- };
-
- qos_npu0_mwr: qos@fdf72000 {
- compatible = "syscon";
- reg = <0x0 0xfdf72000 0x0 0x20>;
- };
-
- qos_npu0_mro: qos@fdf72200 {
- compatible = "syscon";
- reg = <0x0 0xfdf72200 0x0 0x20>;
- };
-
- qos_mcu_npu: qos@fdf72400 {
- compatible = "syscon";
- reg = <0x0 0xfdf72400 0x0 0x20>;
- };
-
- qos_hdcp0: qos@fdf80000 {
- compatible = "syscon";
- reg = <0x0 0xfdf80000 0x0 0x20>;
- };
-
- qos_hdcp1: qos@fdf81000 {
- compatible = "syscon";
- reg = <0x0 0xfdf81000 0x0 0x20>;
- };
-
- qos_hdmirx: qos@fdf81200 {
- compatible = "syscon";
- reg = <0x0 0xfdf81200 0x0 0x20>;
- };
-
- qos_vop_m0: qos@fdf82000 {
- compatible = "syscon";
- reg = <0x0 0xfdf82000 0x0 0x20>;
- };
-
- qos_vop_m1: qos@fdf82200 {
- compatible = "syscon";
- reg = <0x0 0xfdf82200 0x0 0x20>;
- };
-
- dfi: dfi@fe060000 {
- compatible = "rockchip,rk3588-dfi";
- reg = <0x00 0xfe060000 0x00 0x10000>;
- rockchip,pmu_grf = <&pmu1_grf>;
- status = "disabled";
- };
-
- pcie2x1l1: pcie@fe180000 {
- compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x30 0x3f>;
- clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
- <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
- <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
- <0 0 0 2 &pcie2x1l1_intc 1>,
- <0 0 0 3 &pcie2x1l1_intc 2>,
- <0 0 0 4 &pcie2x1l1_intc 3>;
- linux,pci-domain = <3>;
- num-ib-windows = <8>;
- num-ob-windows = <8>;
- num-viewport = <4>;
- max-link-speed = <2>;
- msi-map = <0x3000 &its0 0x3000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy2_psu PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
- 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
- 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
- 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
- reg = <0x0 0xfe180000 0x0 0x10000>,
- <0xa 0x40c00000 0x0 0x400000>;
- reg-names = "pcie-apb", "pcie-dbi";
- resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
- reset-names = "pcie", "periph";
- rockchip,pipe-grf = <&php_grf>;
- status = "disabled";
-
- pcie2x1l1_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- pcie2x1l2: pcie@fe190000 {
- compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x40 0x4f>;
- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
- <0 0 0 2 &pcie2x1l2_intc 1>,
- <0 0 0 3 &pcie2x1l2_intc 2>,
- <0 0 0 4 &pcie2x1l2_intc 3>;
- linux,pci-domain = <4>;
- num-ib-windows = <8>;
- num-ob-windows = <8>;
- num-viewport = <4>;
- max-link-speed = <2>;
- msi-map = <0x4000 &its0 0x4000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy0_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
- 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
- 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
- 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
- reg = <0x0 0xfe190000 0x0 0x10000>,
- <0xa 0x41000000 0x0 0x400000>;
- reg-names = "pcie-apb", "pcie-dbi";
- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
- reset-names = "pcie", "periph";
- rockchip,pipe-grf = <&php_grf>;
- status = "disabled";
-
- pcie2x1l2_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- gmac1: ethernet@fe1c0000 {
- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe1c0000 0x0 0x10000>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- rockchip,grf = <&sys_grf>;
- rockchip,php_grf = <&php_grf>;
- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
- <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
- <&cru CLK_GMAC1_PTP_REF>;
- clock-names = "stmmaceth", "clk_mac_ref",
- "pclk_mac", "aclk_mac",
- "ptp_ref";
- resets = <&cru SRST_A_GMAC1>;
- reset-names = "stmmaceth";
- power-domains = <&power RK3588_PD_GMAC>;
-
- snps,mixed-burst;
- snps,tso;
-
- snps,axi-config = <&gmac1_stmmac_axi_setup>;
- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
- status = "disabled";
-
- mdio1: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- gmac1_stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <4>;
- snps,rd_osr_lmt = <8>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
- gmac1_mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
-
- gmac1_mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
- };
-
- sata0: sata@fe210000 {
- compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
- reg = <0 0xfe210000 0 0x1000>;
- clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
- <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
- <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
- phys = <&combphy0_ps PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- status = "disabled";
- };
-
- sata2: sata@fe230000 {
- compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
- reg = <0 0xfe230000 0 0x1000>;
- clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
- <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
- <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
- phys = <&combphy2_psu PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- status = "disabled";
- };
-
- sfc: spi@fe2b0000 {
- compatible = "rockchip,sfc";
- reg = <0x0 0xfe2b0000 0x0 0x4000>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- assigned-clocks = <&cru SCLK_SFC>;
- assigned-clock-rates = <100000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sdmmc: mmc@fe2c0000 {
- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
- power-domains = <&power RK3588_PD_SDMMC>;
- status = "disabled";
- };
-
- sdio: mmc@fe2d0000 {
- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2d0000 0x0 0x4000>;
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdiom1_pins>;
- power-domains = <&power RK3588_PD_SDIO>;
- status = "disabled";
- };
-
- sdhci: mmc@fe2e0000 {
- compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
- reg = <0x0 0xfe2e0000 0x0 0x10000>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
- assigned-clock-rates = <200000000>, <24000000>, <200000000>;
- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
- <&cru TMCLK_EMMC>;
- clock-names = "core", "bus", "axi", "block", "timer";
- resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
- <&cru SRST_T_EMMC>;
- reset-names = "core", "bus", "axi", "block", "timer";
- max-frequency = <200000000>;
- status = "disabled";
- };
-
- crypto: crypto@fe370000 {
- compatible = "rockchip,rk3588-crypto";
- reg = <0x0 0xfe370000 0x0 0x2000>;
- interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scmi_clk SCMI_ACLK_SECURE_NS>, <&scmi_clk SCMI_HCLK_SECURE_NS>,
- <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>;
- clock-names = "aclk", "hclk", "sclk", "pka";
- resets = <&scmi_reset SRST_CRYPTO_CORE>;
- reset-names = "crypto-rst";
- status = "disabled";
- };
-
- rng: rng@fe378000 {
- compatible = "rockchip,trngv1";
- reg = <0x0 0xfe378000 0x0 0x200>;
- interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
- clock-names = "hclk_trng";
- resets = <&scmi_reset SRST_H_TRNG_NS>;
- reset-names = "reset";
- status = "disabled";
- };
-
- i2s0_8ch: i2s@fe470000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfe470000 0x0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
- dmas = <&dmac0 0>, <&dmac0 1>;
- dma-names = "tx", "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,clk-trcm = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdi1
- &i2s0_sdi2
- &i2s0_sdi3
- &i2s0_sdo0
- &i2s0_sdo1
- &i2s0_sdo2
- &i2s0_sdo3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s1_8ch: i2s@fe480000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfe480000 0x0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- dmas = <&dmac0 2>, <&dmac0 3>;
- dma-names = "tx", "rx";
- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,clk-trcm = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_lrck
- &i2s1m0_sclk
- &i2s1m0_sdi0
- &i2s1m0_sdi1
- &i2s1m0_sdi2
- &i2s1m0_sdi3
- &i2s1m0_sdo0
- &i2s1m0_sdo1
- &i2s1m0_sdo2
- &i2s1m0_sdo3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s2_2ch: i2s@fe490000 {
- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xfe490000 0x0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac1 0>, <&dmac1 1>;
- dma-names = "tx", "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- rockchip,clk-trcm = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s2m1_lrck
- &i2s2m1_sclk
- &i2s2m1_sdi
- &i2s2m1_sdo>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s3_2ch: i2s@fe4a0000 {
- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xfe4a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac1 2>, <&dmac1 3>;
- dma-names = "tx", "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- rockchip,clk-trcm = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s3_lrck
- &i2s3_sclk
- &i2s3_sdi
- &i2s3_sdo>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- pdm0: pdm@fe4b0000 {
- compatible = "rockchip,rk3588-pdm";
- reg = <0x0 0xfe4b0000 0x0 0x1000>;
- clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>;
- clock-names = "pdm_clk", "pdm_hclk";
- dmas = <&dmac0 4>;
- dma-names = "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&pdm0m0_clk
- &pdm0m0_clk1
- &pdm0m0_sdi0
- &pdm0m0_sdi1
- &pdm0m0_sdi2
- &pdm0m0_sdi3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- pdm1: pdm@fe4c0000 {
- compatible = "rockchip,rk3588-pdm";
- reg = <0x0 0xfe4c0000 0x0 0x1000>;
- clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>;
- clock-names = "pdm_clk", "pdm_hclk";
- assigned-clocks = <&cru MCLK_PDM1>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac1 4>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- pinctrl-names = "default";
- pinctrl-0 = <&pdm1m0_clk
- &pdm1m0_clk1
- &pdm1m0_sdi0
- &pdm1m0_sdi1
- &pdm1m0_sdi2
- &pdm1m0_sdi3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- vad: vad@fe4d0000 {
- compatible = "rockchip,rk3588-vad";
- reg = <0x0 0xfe4d0000 0x0 0x1000>;
- reg-names = "vad";
- clocks = <&cru HCLK_VAD>;
- clock-names = "hclk";
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,audio-src = <0>;
- rockchip,det-channel = <0>;
- rockchip,mode = <0>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_tx0: spdif-tx@fe4e0000 {
- compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
- reg = <0x0 0xfe4e0000 0x0 0x1000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac0 5>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
- assigned-clocks = <&cru CLK_SPDIF0_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- power-domains = <&power RK3588_PD_AUDIO>;
- pinctrl-names = "default";
- pinctrl-0 = <&spdif0m0_tx>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif_tx1: spdif-tx@fe4f0000 {
- compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
- reg = <0x0 0xfe4f0000 0x0 0x1000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac1 5>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
- assigned-clocks = <&cru CLK_SPDIF1_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- power-domains = <&power RK3588_PD_AUDIO>;
- pinctrl-names = "default";
- pinctrl-0 = <&spdif1m0_tx>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- acdcdig_dsm: codec-digital@fe500000 {
- compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
- reg = <0x0 0xfe500000 0x0 0x1000>;
- clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>;
- clock-names = "dac", "pclk";
- power-domains = <&power RK3588_PD_AUDIO>;
- resets = <&cru SRST_DAC_ACDCDIG>;
- reset-names = "reset" ;
- rockchip,grf = <&sys_grf>;
- rockchip,pwm-output-mode;
- pinctrl-names = "default";
- pinctrl-0 = <&auddsm_pins>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- hwlock: hwspinlock@fe5a0000 {
- compatible = "rockchip,hwspinlock";
- reg = <0 0xfe5a0000 0 0x100>;
- #hwlock-cells = <1>;
- };
-
- gic: interrupt-controller@fe600000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- interrupt-controller;
-
- reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
- <0x0 0xfe680000 0 0x100000>; /* GICR */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- its0: msi-controller@fe640000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cells = <1>;
- reg = <0x0 0xfe640000 0x0 0x20000>;
- };
- its1: msi-controller@fe660000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cells = <1>;
- reg = <0x0 0xfe660000 0x0 0x20000>;
- };
- };
-
- dmac0: dma-controller@fea10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfea10000 0x0 0x4000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- };
-
- dmac1: dma-controller@fea30000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfea30000 0x0 0x4000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- };
-
- can0: can@fea50000 {
- compatible = "rockchip,can-2.0";
- reg = <0x0 0xfea50000 0x0 0x1000>;
- interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
- clock-names = "baudclk", "apb_pclk";
- resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
- reset-names = "can", "can-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&can0m0_pins>;
- tx-fifo-depth = <1>;
- rx-fifo-depth = <6>;
- status = "disabled";
- };
-
- can1: can@fea60000 {
- compatible = "rockchip,can-2.0";
- reg = <0x0 0xfea60000 0x0 0x1000>;
- interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
- clock-names = "baudclk", "apb_pclk";
- resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
- reset-names = "can", "can-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&can1m0_pins>;
- tx-fifo-depth = <1>;
- rx-fifo-depth = <6>;
- status = "disabled";
- };
-
- can2: can@fea70000 {
- compatible = "rockchip,can-2.0";
- reg = <0x0 0xfea70000 0x0 0x1000>;
- interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
- clock-names = "baudclk", "apb_pclk";
- resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
- reset-names = "can", "can-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&can2m0_pins>;
- tx-fifo-depth = <1>;
- rx-fifo-depth = <6>;
- status = "disabled";
- };
-
- hw_decompress: decompress@fea80000 {
- compatible = "rockchip,hw-decompress";
- reg = <0x0 0xfea80000 0x0 0x1000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
- clock-names = "aclk", "dclk", "pclk";
- resets = <&cru SRST_D_DECOM>;
- reset-names = "dresetn";
- status = "disabled";
- };
-
- i2c1: i2c@fea90000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfea90000 0x0 0x1000>;
- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@feaa0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeaa0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@feab0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeab0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@feac0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeac0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@fead0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfead0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- rktimer: timer@feae0000 {
- compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
- reg = <0x0 0xfeae0000 0x0 0x20>;
- interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
- clock-names = "pclk", "timer";
- };
-
- wdt: watchdog@feaf0000 {
- compatible = "snps,dw-wdt";
- reg = <0x0 0xfeaf0000 0x0 0x100>;
- clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
- clock-names = "tclk", "pclk";
- interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- spi0: spi@feb00000 {
- compatible = "rockchip,rk3066-spi";
- reg = <0x0 0xfeb00000 0x0 0x1000>;
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 14>, <&dmac0 15>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
- num-cs = <2>;
- status = "disabled";
- };
-
- spi1: spi@feb10000 {
- compatible = "rockchip,rk3066-spi";
- reg = <0x0 0xfeb10000 0x0 0x1000>;
- interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 16>, <&dmac0 17>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
- num-cs = <2>;
- status = "disabled";
- };
-
- spi2: spi@feb20000 {
- compatible = "rockchip,rk3066-spi";
- reg = <0x0 0xfeb20000 0x0 0x1000>;
- interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac1 15>, <&dmac1 16>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
- num-cs = <2>;
- status = "disabled";
- };
-
- spi3: spi@feb30000 {
- compatible = "rockchip,rk3066-spi";
- reg = <0x0 0xfeb30000 0x0 0x1000>;
- interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac1 17>, <&dmac1 18>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
- num-cs = <2>;
- status = "disabled";
- };
-
- uart1: serial@feb40000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb40000 0x0 0x100>;
- interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac0 8>, <&dmac0 9>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m1_xfer>;
- status = "disabled";
- };
-
- uart2: serial@feb50000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb50000 0x0 0x100>;
- interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac0 10>, <&dmac0 11>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- status = "disabled";
- };
-
- uart3: serial@feb60000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb60000 0x0 0x100>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac0 12>, <&dmac0 13>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m1_xfer>;
- status = "disabled";
- };
-
- uart4: serial@feb70000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb70000 0x0 0x100>;
- interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac1 9>, <&dmac1 10>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m1_xfer>;
- status = "disabled";
- };
-
- uart5: serial@feb80000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb80000 0x0 0x100>;
- interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac1 11>, <&dmac1 12>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart5m1_xfer>;
- status = "disabled";
- };
-
- uart6: serial@feb90000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb90000 0x0 0x100>;
- interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac1 13>, <&dmac1 14>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart6m1_xfer>;
- status = "disabled";
- };
-
- uart7: serial@feba0000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeba0000 0x0 0x100>;
- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac2 7>, <&dmac2 8>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart7m1_xfer>;
- status = "disabled";
- };
-
- uart8: serial@febb0000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfebb0000 0x0 0x100>;
- interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac2 9>, <&dmac2 10>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart8m1_xfer>;
- status = "disabled";
- };
-
- uart9: serial@febc0000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfebc0000 0x0 0x100>;
- interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&dmac2 11>, <&dmac2 12>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart9m1_xfer>;
- status = "disabled";
- };
-
- pwm4: pwm@febd0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm4m0_pins>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm5: pwm@febd0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm5m0_pins>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm6: pwm@febd0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm6m0_pins>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm7: pwm@febd0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0030 0x0 0x10>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm7m0_pins>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm8: pwm@febe0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm8m0_pins>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm9: pwm@febe0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm9m0_pins>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm10: pwm@febe0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm10m0_pins>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm11: pwm@febe0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0030 0x0 0x10>;
- interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm11m0_pins>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm12: pwm@febf0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm12m0_pins>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm13: pwm@febf0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm13m0_pins>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm14: pwm@febf0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm14m0_pins>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- pwm15: pwm@febf0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0030 0x0 0x10>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm15m0_pins>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- status = "disabled";
- };
-
- tsadc: tsadc@fec00000 {
- compatible = "rockchip,rk3588-tsadc";
- reg = <0x0 0xfec00000 0x0 0x400>;
- interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
- assigned-clocks = <&cru CLK_TSADC>;
- assigned-clock-rates = <2000000>;
- resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
- reset-names = "tsadc", "tsadc-apb";
- #thermal-sensor-cells = <1>;
- rockchip,hw-tshut-temp = <120000>;
- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
- pinctrl-names = "gpio", "otpout";
- pinctrl-0 = <&tsadc_gpio_func>;
- pinctrl-1 = <&tsadc_shut>;
- status = "disabled";
- };
-
- saradc: saradc@fec10000 {
- compatible = "rockchip,rk3588-saradc";
- reg = <0x0 0xfec10000 0x0 0x10000>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_P_SARADC>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- mailbox0: mailbox@fec60000 {
- compatible = "rockchip,rk3588-mailbox",
- "rockchip,rk3368-mailbox";
- reg = <0x0 0xfec60000 0x0 0x200>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MAILBOX0>;
- clock-names = "pclk_mailbox";
- #mbox-cells = <1>;
- status = "disabled";
- };
-
- mailbox1: mailbox@fec70000 {
- compatible = "rockchip,rk3588-mailbox",
- "rockchip,rk3368-mailbox";
- reg = <0x0 0xfec70000 0x0 0x200>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MAILBOX1>;
- clock-names = "pclk_mailbox";
- #mbox-cells = <1>;
- status = "disabled";
- };
-
- i2c6: i2c@fec80000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfec80000 0x0 0x1000>;
- clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c7: i2c@fec90000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfec90000 0x0 0x1000>;
- clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c8: i2c@feca0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeca0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c8m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi4: spi@fecb0000 {
- compatible = "rockchip,rk3066-spi";
- reg = <0x0 0xfecb0000 0x0 0x1000>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac2 13>, <&dmac2 14>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
- num-cs = <2>;
- status = "disabled";
- };
-
- otp: otp@fecc0000 {
- compatible = "rockchip,rk3588-otp";
- reg = <0x0 0xfecc0000 0x0 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
- <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
- clock-names = "otpc", "apb", "arb", "phy";
- resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
- <&cru SRST_OTPC_ARB>;
- reset-names = "otpc", "apb", "arb";
-
- /* Data cells */
- cpu_code: cpu-code@2 {
- reg = <0x02 0x2>;
- };
- specification_serial_number: specification-serial-number@6 {
- reg = <0x06 0x1>;
- bits = <0 5>;
- };
- otp_id: id@7 {
- reg = <0x07 0x10>;
- };
- otp_cpu_version: cpu-version@1c {
- reg = <0x1c 0x1>;
- bits = <3 3>;
- };
- cpub0_leakage: cpub0-leakage@17 {
- reg = <0x17 0x1>;
- };
- cpub1_leakage: cpub1-leakage@18 {
- reg = <0x18 0x1>;
- };
- cpul_leakage: cpul-leakage@19 {
- reg = <0x19 0x1>;
- };
- log_leakage: log-leakage@1a {
- reg = <0x1a 0x1>;
- };
- gpu_leakage: gpu-leakage@1b {
- reg = <0x1b 0x1>;
- };
- npu_leakage: npu-leakage@28 {
- reg = <0x28 0x1>;
- };
- codec_leakage: codec-leakage@29 {
- reg = <0x29 0x1>;
- };
- };
-
- mailbox2: mailbox@fece0000 {
- compatible = "rockchip,rk3588-mailbox",
- "rockchip,rk3368-mailbox";
- reg = <0x0 0xfece0000 0x0 0x200>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MAILBOX2>;
- clock-names = "pclk_mailbox";
- #mbox-cells = <1>;
- status = "disabled";
- };
-
- dmac2: dma-controller@fed10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfed10000 0x0 0x4000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC2>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- };
-
- hdptxphy0: phy@fed60000 {
- compatible = "rockchip,rk3588-hdptx-phy";
- reg = <0x0 0xfed60000 0x0 0x2000>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
- clock-names = "ref", "apb";
- resets = <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>,
- <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>;
- reset-names = "apb", "init", "cmn", "lane";
- rockchip,grf = <&hdptxphy0_grf>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- hdptxphy_hdmi0: hdmiphy@fed60000 {
- compatible = "rockchip,rk3588-hdptx-phy-hdmi";
- reg = <0x0 0xfed60000 0x0 0x2000>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
- clock-names = "ref", "apb";
- resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
- <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
- <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
- <&cru SRST_HDPTX0_LCPLL>;
- reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
- "lcpll";
- rockchip,grf = <&hdptxphy0_grf>;
- #phy-cells = <0>;
- status = "disabled";
-
- hdptxphy_hdmi_clk0: clk-port {
- #clock-cells = <0>;
- status = "okay";
- };
- };
-
- usbdp_phy0: phy@fed80000 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed80000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy0_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
- <&cru CLK_USBDP_PHY0_IMMORTAL>,
- <&cru PCLK_USBDPPHY0>,
- <&u2phy0>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
- <&cru SRST_USBDP_COMBO_PHY0_CMN>,
- <&cru SRST_USBDP_COMBO_PHY0_LANE>,
- <&cru SRST_USBDP_COMBO_PHY0_PCS>,
- <&cru SRST_P_USBDPPHY0>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- status = "disabled";
-
- usbdp_phy0_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy0_u3: u3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
-
- mipi_dcphy0: phy@feda0000 {
- compatible = "rockchip,rk3588-mipi-dcphy";
- reg = <0x0 0xfeda0000 0x0 0x10000>;
- rockchip,grf = <&mipidcphy0_grf>;
- clocks = <&cru PCLK_MIPI_DCPHY0>,
- <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
- clock-names = "pclk", "ref";
- resets = <&cru SRST_M_MIPI_DCPHY0>,
- <&cru SRST_P_MIPI_DCPHY0>,
- <&cru SRST_P_MIPI_DCPHY0_GRF>,
- <&cru SRST_S_MIPI_DCPHY0>;
- reset-names = "m_phy", "apb", "grf", "s_phy";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- mipi_dcphy1: phy@fedb0000 {
- compatible = "rockchip,rk3588-mipi-dcphy";
- reg = <0x0 0xfedb0000 0x0 0x10000>;
- rockchip,grf = <&mipidcphy1_grf>;
- clocks = <&cru PCLK_MIPI_DCPHY1>,
- <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
- clock-names = "pclk", "ref";
- resets = <&cru SRST_M_MIPI_DCPHY1>,
- <&cru SRST_P_MIPI_DCPHY1>,
- <&cru SRST_P_MIPI_DCPHY1_GRF>,
- <&cru SRST_S_MIPI_DCPHY1>;
- reset-names = "m_phy", "apb", "grf", "s_phy";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 {
- compatible = "rockchip,rk3588-csi2-dphy-hw";
- reg = <0x0 0xfedc0000 0x0 0x8000>;
- clocks = <&cru PCLK_CSIPHY0>;
- clock-names = "pclk";
- resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>;
- reset-names = "srst_csiphy0", "srst_p_csiphy0";
- rockchip,grf = <&mipidphy0_grf>;
- rockchip,sys_grf = <&sys_grf>;
- status = "disabled";
- };
-
- combphy0_ps: phy@fee00000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee00000 0x0 0x100>;
- #phy-cells = <1>;
- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "refclk", "apbclk", "phpclk";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
- reset-names = "combphy-apb", "combphy";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
- status = "disabled";
- };
-
- combphy2_psu: phy@fee20000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee20000 0x0 0x100>;
- #phy-cells = <1>;
- clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "refclk", "apbclk", "phpclk";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
- reset-names = "combphy-apb", "combphy";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
- rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
- status = "disabled";
- };
-
- syssram: sram@ff001000 {
- compatible = "mmio-sram";
- reg = <0x0 0xff001000 0x0 0xef000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff001000 0xef000>;
- /* start address and size should be 4k algin */
- rkvdec0_sram: rkvdec-sram@0 {
- reg = <0x0 0x78000>;
- };
- rkvdec1_sram: rkvdec-sram@78000 {
- reg = <0x78000 0x77000>;
- };
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3588-pinctrl";
- rockchip,grf = <&ioc>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@fd8a0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfd8a0000 0x0 0x100>;
- interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@fec20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec20000 0x0 0x100>;
- interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@fec30000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec30000 0x0 0x100>;
- interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@fec40000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec40000 0x0 0x100>;
- interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@fec50000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec50000 0x0 0x100>;
- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-};
-
-#include "rk3588s-pinctrl.dtsi"
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi (nonexistent)
@@ -1,777 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-
- rk806master: rk806master@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default", "pmic-power-off";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- pinctrl-1 = <&rk806_dvs1_pwrdn>;
-
- /* 2800mv-3500mv */
- low_voltage_threshold = <3000>;
- /* 2700mv-3400mv */
- shutdown_voltage_threshold = <2700>;
- /* 140 160 */
- shutdown_temperture_threshold = <160>;
- hotdie_temperture_threshold = <115>;
-
- /* 0: restart PMU;
- * 1: reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode;
- * 2: Reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode,
- * and simultaneously pull down the RESETB PIN for 5mS before releasing
- */
- pmic-reset-func = <1>;
-
- /* PWRON_ON_TIME: 0:500mS; 1:20mS */
- pwron-on-time-20ms;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc5v0_sys>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- pwrkey {
- status = "okay";
- };
-
- pinctrl_rk806: pinctrl_rk806 {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: rk806_dvs1_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs1_slp: rk806_dvs1_slp {
- pins = "gpio_pwrctrl1";
- function = "pin_fun1";
- };
-
- rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
- pins = "gpio_pwrctrl1";
- function = "pin_fun2";
- };
-
- rk806_dvs1_rst: rk806_dvs1_rst {
- pins = "gpio_pwrctrl1";
- function = "pin_fun3";
- };
-
- rk806_dvs2_null: rk806_dvs2_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_slp: rk806_dvs2_slp {
- pins = "gpio_pwrctrl2";
- function = "pin_fun1";
- };
-
- rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
- pins = "gpio_pwrctrl2";
- function = "pin_fun2";
- };
-
- rk806_dvs2_rst: rk806_dvs2_rst {
- pins = "gpio_pwrctrl2";
- function = "pin_fun3";
- };
-
- rk806_dvs2_dvs: rk806_dvs2_dvs {
- pins = "gpio_pwrctrl2";
- function = "pin_fun4";
- };
-
- rk806_dvs2_gpio: rk806_dvs2_gpio {
- pins = "gpio_pwrctrl2";
- function = "pin_fun5";
- };
-
- rk806_dvs3_null: rk806_dvs3_null {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- rk806_dvs3_slp: rk806_dvs3_slp {
- pins = "gpio_pwrctrl3";
- function = "pin_fun1";
- };
-
- rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
- pins = "gpio_pwrctrl3";
- function = "pin_fun2";
- };
-
- rk806_dvs3_rst: rk806_dvs3_rst {
- pins = "gpio_pwrctrl3";
- function = "pin_fun3";
- };
-
- rk806_dvs3_dvs: rk806_dvs3_dvs {
- pins = "gpio_pwrctrl3";
- function = "pin_fun4";
- };
-
- rk806_dvs3_gpio: rk806_dvs3_gpio {
- pins = "gpio_pwrctrl3";
- function = "pin_fun5";
- };
- };
-
- regulators {
- vdd_gpu_s0: DCDC_REG1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
- regulator-name = "vdd_gpu_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_npu_s0: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_npu_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu_mem_s0: DCDC_REG5 {
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
- regulator-name = "vdd_gpu_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_npu_mem_s0: DCDC_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_npu_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: DCDC_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vdd_vdenc_mem_s0: DCDC_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd2_ddr_s3: DCDC_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v1_nldo_s3: DCDC_REG10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1100000>;
- };
- };
-
- avcc_1v8_s0: PLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd1_1v8_ddr_s3: PLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd1_1v8_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_1v8_s3: PLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_3v3_s0: PLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: PLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- master_pldo6_s3: PLDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "master_pldo6_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: NLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_0v75_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd2l_0v9_ddr_s3: NLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdd2l_0v9_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- master_nldo3: NLDO_REG3 {
- regulator-name = "master_nldo3";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v75_s0: NLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: NLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- rk806slave: rk806slave@1 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x01>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default", "pmic-sleep";
- pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
- pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
-
- /* 0: restart PMU;
- * 1: reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode;
- * 2: Reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode,
- * and simultaneously pull down the RESETB PIN for 5mS before releasing
- */
- pmic-reset-func = <1>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_2v0_pldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- pwrkey {
- status = "disabled";
- };
-
- pinctrl_slave_rk806: pinctrl_slave_rk806 {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_slave_dvs1_null: rk806_slave_dvs1_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs1_slp: rk806_slave_dvs1_slp {
- pins = "gpio_pwrctrl1";
- function = "pin_fun1";
- };
-
- rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn {
- pins = "gpio_pwrctrl1";
- function = "pin_fun2";
- };
-
- rk806_slave_dvs1_rst: rk806_slave_dvs1_rst {
- pins = "gpio_pwrctrl1";
- function = "pin_fun3";
- };
-
- rk806_slave_dvs2_null: rk806_slave_dvs2_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs2_slp: rk806_slave_dvs2_slp {
- pins = "gpio_pwrctrl2";
- function = "pin_fun1";
- };
-
- rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn {
- pins = "gpio_pwrctrl2";
- function = "pin_fun2";
- };
-
- rk806_slave_dvs2_rst: rk806_slave_dvs2_rst {
- pins = "gpio_pwrctrl2";
- function = "pin_fun3";
- };
-
- rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs {
- pins = "gpio_pwrctrl2";
- function = "pin_fun4";
- };
-
- rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio {
- pins = "gpio_pwrctrl2";
- function = "pin_fun5";
- };
-
- rk806_slave_dvs3_null: rk806_slave_dvs3_null {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs3_slp: rk806_slave_dvs3_slp {
- pins = "gpio_pwrctrl3";
- function = "pin_fun1";
- };
-
- rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn {
- pins = "gpio_pwrctrl3";
- function = "pin_fun2";
- };
-
- rk806_slave_dvs3_rst: rk806_slave_dvs3_rst {
- pins = "gpio_pwrctrl3";
- function = "pin_fun3";
- };
-
- rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs {
- pins = "gpio_pwrctrl3";
- function = "pin_fun4";
- };
-
- rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio {
- pins = "gpio_pwrctrl3";
- function = "pin_fun5";
- };
- };
-
- regulators {
- vdd_cpu_big1_s0: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big0_s0: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s3: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vdd_cpu_big1_mem_s0: DCDC_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big1_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
-
- vdd_cpu_big0_mem_s0: DCDC_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big0_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: DCDC_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_mem_s0: DCDC_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vddq_ddr_s0: DCDC_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: DCDC_REG10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_cam_s0: PLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd1v8_ddr_pll_s0: PLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd1v8_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_1v8_pll_s0: PLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_1v8_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_sd_s0: PLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_2v8_cam_s0: PLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_2v8_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: PLDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_pll_s0: NLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_0v75_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_pll_s0: NLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- slave_nldo3: NLDO_REG3 {
- regulator-name = "slave_nldo3";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_cam_s0: NLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_1v2_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_s0: NLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_1v2_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi (nonexistent)
@@ -1,516 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- clk32k {
- /omit-if-no-ref/
- clk32k_out1: clk32k-out1 {
- rockchip,pins =
- /* clk32k_out1 */
- <2 RK_PC5 1 &pcfg_pull_none>;
- };
-
- };
-
- eth0 {
- /omit-if-no-ref/
- eth0_pins: eth0-pins {
- rockchip,pins =
- /* eth0_refclko_25m */
- <2 RK_PC3 1 &pcfg_pull_none>;
- };
-
- };
-
- fspi {
- /omit-if-no-ref/
- fspim1_pins: fspim1-pins {
- rockchip,pins =
- /* fspi_clk_m1 */
- <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_cs0n_m1 */
- <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d0_m1 */
- <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d1_m1 */
- <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d2_m1 */
- <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d3_m1 */
- <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim1_cs1: fspim1-cs1 {
- rockchip,pins =
- /* fspi_cs1n_m1 */
- <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
- };
- };
-
- gmac0 {
- /omit-if-no-ref/
- gmac0_miim: gmac0-miim {
- rockchip,pins =
- /* gmac0_mdc */
- <4 RK_PC4 1 &pcfg_pull_none>,
- /* gmac0_mdio */
- <4 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_clkinout: gmac0-clkinout {
- rockchip,pins =
- /* gmac0_mclkinout */
- <4 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rx_bus2: gmac0-rx-bus2 {
- rockchip,pins =
- /* gmac0_rxd0 */
- <2 RK_PC1 1 &pcfg_pull_none>,
- /* gmac0_rxd1 */
- <2 RK_PC2 1 &pcfg_pull_none>,
- /* gmac0_rxdv_crs */
- <4 RK_PC2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_tx_bus2: gmac0-tx-bus2 {
- rockchip,pins =
- /* gmac0_txd0 */
- <2 RK_PB6 1 &pcfg_pull_none>,
- /* gmac0_txd1 */
- <2 RK_PB7 1 &pcfg_pull_none>,
- /* gmac0_txen */
- <2 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_clk: gmac0-rgmii-clk {
- rockchip,pins =
- /* gmac0_rxclk */
- <2 RK_PB0 1 &pcfg_pull_none>,
- /* gmac0_txclk */
- <2 RK_PB3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_bus: gmac0-rgmii-bus {
- rockchip,pins =
- /* gmac0_rxd2 */
- <2 RK_PA6 1 &pcfg_pull_none>,
- /* gmac0_rxd3 */
- <2 RK_PA7 1 &pcfg_pull_none>,
- /* gmac0_txd2 */
- <2 RK_PB1 1 &pcfg_pull_none>,
- /* gmac0_txd3 */
- <2 RK_PB2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_ppsclk: gmac0-ppsclk {
- rockchip,pins =
- /* gmac0_ppsclk */
- <2 RK_PC4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_ppstring: gmac0-ppstring {
- rockchip,pins =
- /* gmac0_ppstring */
- <2 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_ptp_refclk: gmac0-ptp-refclk {
- rockchip,pins =
- /* gmac0_ptp_refclk */
- <2 RK_PB4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_txer: gmac0-txer {
- rockchip,pins =
- /* gmac0_txer */
- <4 RK_PC6 1 &pcfg_pull_none>;
- };
-
- };
-
- hdmi {
- /omit-if-no-ref/
- hdmim0_tx1_cec: hdmim0-tx1-cec {
- rockchip,pins =
- /* hdmim0_tx1_cec */
- <2 RK_PC4 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx1_scl: hdmim0-tx1-scl {
- rockchip,pins =
- /* hdmim0_tx1_scl */
- <2 RK_PB5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx1_sda: hdmim0-tx1-sda {
- rockchip,pins =
- /* hdmim0_tx1_sda */
- <2 RK_PB4 4 &pcfg_pull_none>;
- };
- };
-
- i2c0 {
- /omit-if-no-ref/
- i2c0m1_xfer: i2c0m1-xfer {
- rockchip,pins =
- /* i2c0_scl_m1 */
- <4 RK_PC5 9 &pcfg_pull_none_smt>,
- /* i2c0_sda_m1 */
- <4 RK_PC6 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c2 {
- /omit-if-no-ref/
- i2c2m1_xfer: i2c2m1-xfer {
- rockchip,pins =
- /* i2c2_scl_m1 */
- <2 RK_PC1 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m1 */
- <2 RK_PC0 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3 {
- /omit-if-no-ref/
- i2c3m3_xfer: i2c3m3-xfer {
- rockchip,pins =
- /* i2c3_scl_m3 */
- <2 RK_PB2 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m3 */
- <2 RK_PB3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c4 {
- /omit-if-no-ref/
- i2c4m1_xfer: i2c4m1-xfer {
- rockchip,pins =
- /* i2c4_scl_m1 */
- <2 RK_PB5 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m1 */
- <2 RK_PB4 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c5 {
- /omit-if-no-ref/
- i2c5m4_xfer: i2c5m4-xfer {
- rockchip,pins =
- /* i2c5_scl_m4 */
- <2 RK_PB6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m4 */
- <2 RK_PB7 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c6 {
- /omit-if-no-ref/
- i2c6m2_xfer: i2c6m2-xfer {
- rockchip,pins =
- /* i2c6_scl_m2 */
- <2 RK_PC3 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m2 */
- <2 RK_PC2 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c7 {
- /omit-if-no-ref/
- i2c7m1_xfer: i2c7m1-xfer {
- rockchip,pins =
- /* i2c7_scl_m1 */
- <4 RK_PC3 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m1 */
- <4 RK_PC4 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c8 {
- /omit-if-no-ref/
- i2c8m1_xfer: i2c8m1-xfer {
- rockchip,pins =
- /* i2c8_scl_m1 */
- <2 RK_PB0 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m1 */
- <2 RK_PB1 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2s2 {
- /omit-if-no-ref/
- i2s2m0_lrck: i2s2m0-lrck {
- rockchip,pins =
- /* i2s2m0_lrck */
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_mclk: i2s2m0-mclk {
- rockchip,pins =
- /* i2s2m0_mclk */
- <2 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sclk: i2s2m0-sclk {
- rockchip,pins =
- /* i2s2m0_sclk */
- <2 RK_PB7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdi: i2s2m0-sdi {
- rockchip,pins =
- /* i2s2m0_sdi */
- <2 RK_PC3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdo: i2s2m0-sdo {
- rockchip,pins =
- /* i2s2m0_sdo */
- <4 RK_PC3 2 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- /omit-if-no-ref/
- pwm2m2_pins: pwm2m2-pins {
- rockchip,pins =
- /* pwm2_m2 */
- <4 RK_PC2 11 &pcfg_pull_none>;
- };
- };
-
- pwm4 {
- /omit-if-no-ref/
- pwm4m1_pins: pwm4m1-pins {
- rockchip,pins =
- /* pwm4_m1 */
- <4 RK_PC3 11 &pcfg_pull_none>;
- };
- };
-
- pwm5 {
- /omit-if-no-ref/
- pwm5m2_pins: pwm5m2-pins {
- rockchip,pins =
- /* pwm5_m2 */
- <4 RK_PC4 11 &pcfg_pull_none>;
- };
- };
-
- pwm6 {
- /omit-if-no-ref/
- pwm6m2_pins: pwm6m2-pins {
- rockchip,pins =
- /* pwm6_m2 */
- <4 RK_PC5 11 &pcfg_pull_none>;
- };
- };
-
- pwm7 {
- /omit-if-no-ref/
- pwm7m3_pins: pwm7m3-pins {
- rockchip,pins =
- /* pwm7_ir_m3 */
- <4 RK_PC6 11 &pcfg_pull_none>;
- };
- };
-
- sdio {
- /omit-if-no-ref/
- sdiom0_pins: sdiom0-pins {
- rockchip,pins =
- /* sdio_clk_m0 */
- <2 RK_PB3 2 &pcfg_pull_none>,
- /* sdio_cmd_m0 */
- <2 RK_PB2 2 &pcfg_pull_up>,
- /* sdio_d0_m0 */
- <2 RK_PA6 2 &pcfg_pull_up>,
- /* sdio_d1_m0 */
- <2 RK_PA7 2 &pcfg_pull_up>,
- /* sdio_d2_m0 */
- <2 RK_PB0 2 &pcfg_pull_up>,
- /* sdio_d3_m0 */
- <2 RK_PB1 2 &pcfg_pull_up>;
- };
- };
-
- spi1 {
- /omit-if-no-ref/
- spi1m0_pins: spi1m0-pins {
- rockchip,pins =
- /* spi1_clk_m0 */
- <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_miso_m0 */
- <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_mosi_m0 */
- <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs0: spi1m0-cs0 {
- rockchip,pins =
- /* spi1_cs0_m0 */
- <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs1: spi1m0-cs1 {
- rockchip,pins =
- /* spi1_cs1_m0 */
- <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi3 {
- /omit-if-no-ref/
- spi3m0_pins: spi3m0-pins {
- rockchip,pins =
- /* spi3_clk_m0 */
- <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_miso_m0 */
- <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosi_m0 */
- <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs0: spi3m0-cs0 {
- rockchip,pins =
- /* spi3_cs0_m0 */
- <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs1: spi3m0-cs1 {
- rockchip,pins =
- /* spi3_cs1_m0 */
- <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- uart1 {
- /omit-if-no-ref/
- uart1m0_xfer: uart1m0-xfer {
- rockchip,pins =
- /* uart1_rx_m0 */
- <2 RK_PB6 10 &pcfg_pull_up>,
- /* uart1_tx_m0 */
- <2 RK_PB7 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m0_ctsn: uart1m0-ctsn {
- rockchip,pins =
- /* uart1m0_ctsn */
- <2 RK_PC1 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m0_rtsn: uart1m0-rtsn {
- rockchip,pins =
- /* uart1m0_rtsn */
- <2 RK_PC0 10 &pcfg_pull_none>;
- };
- };
-
- uart6 {
- /omit-if-no-ref/
- uart6m0_xfer: uart6m0-xfer {
- rockchip,pins =
- /* uart6_rx_m0 */
- <2 RK_PA6 10 &pcfg_pull_up>,
- /* uart6_tx_m0 */
- <2 RK_PA7 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart6m0_ctsn: uart6m0-ctsn {
- rockchip,pins =
- /* uart6m0_ctsn */
- <2 RK_PB1 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m0_rtsn: uart6m0-rtsn {
- rockchip,pins =
- /* uart6m0_rtsn */
- <2 RK_PB0 10 &pcfg_pull_none>;
- };
- };
-
- uart7 {
- /omit-if-no-ref/
- uart7m0_xfer: uart7m0-xfer {
- rockchip,pins =
- /* uart7_rx_m0 */
- <2 RK_PB4 10 &pcfg_pull_up>,
- /* uart7_tx_m0 */
- <2 RK_PB5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart7m0_ctsn: uart7m0-ctsn {
- rockchip,pins =
- /* uart7m0_ctsn */
- <4 RK_PC6 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m0_rtsn: uart7m0-rtsn {
- rockchip,pins =
- /* uart7m0_rtsn */
- <4 RK_PC2 10 &pcfg_pull_none>;
- };
- };
-
- uart9 {
- /omit-if-no-ref/
- uart9m0_xfer: uart9m0-xfer {
- rockchip,pins =
- /* uart9_rx_m0 */
- <2 RK_PC4 10 &pcfg_pull_up>,
- /* uart9_tx_m0 */
- <2 RK_PC2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m0_ctsn: uart9m0-ctsn {
- rockchip,pins =
- /* uart9m0_ctsn */
- <4 RK_PC5 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m0_rtsn: uart9m0-rtsn {
- rockchip,pins =
- /* uart9m0_rtsn */
- <4 RK_PC4 10 &pcfg_pull_none>;
- };
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi (nonexistent)
@@ -1,782 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-
- rk806master: rk806master@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default", "pmic-power-off";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- pinctrl-1 = <&rk806_dvs1_pwrdn>;
-
- /* 2800mv-3500mv */
- low_voltage_threshold = <3000>;
- /* 2700mv-3400mv */
- shutdown_voltage_threshold = <2700>;
- /* 140 160 */
- shutdown_temperture_threshold = <160>;
- hotdie_temperture_threshold = <115>;
-
- /* 0: restart PMU;
- * 1: reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode;
- * 2: Reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode,
- * and simultaneously pull down the RESETB PIN for 5mS before releasing
- */
- pmic-reset-func = <1>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc5v0_sys>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- pwrkey {
- status = "okay";
- };
-
- pinctrl_rk806: pinctrl_rk806 {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: rk806_dvs1_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs1_slp: rk806_dvs1_slp {
- pins = "gpio_pwrctrl1";
- function = "pin_fun1";
- };
-
- rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
- pins = "gpio_pwrctrl1";
- function = "pin_fun2";
- };
-
- rk806_dvs1_rst: rk806_dvs1_rst {
- pins = "gpio_pwrctrl1";
- function = "pin_fun3";
- };
-
- rk806_dvs2_null: rk806_dvs2_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_slp: rk806_dvs2_slp {
- pins = "gpio_pwrctrl2";
- function = "pin_fun1";
- };
-
- rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
- pins = "gpio_pwrctrl2";
- function = "pin_fun2";
- };
-
- rk806_dvs2_rst: rk806_dvs2_rst {
- pins = "gpio_pwrctrl2";
- function = "pin_fun3";
- };
-
- rk806_dvs2_dvs: rk806_dvs2_dvs {
- pins = "gpio_pwrctrl2";
- function = "pin_fun4";
- };
-
- rk806_dvs2_gpio: rk806_dvs2_gpio {
- pins = "gpio_pwrctrl2";
- function = "pin_fun5";
- };
-
- rk806_dvs3_null: rk806_dvs3_null {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- rk806_dvs3_slp: rk806_dvs3_slp {
- pins = "gpio_pwrctrl3";
- function = "pin_fun1";
- };
-
- rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
- pins = "gpio_pwrctrl3";
- function = "pin_fun2";
- };
-
- rk806_dvs3_rst: rk806_dvs3_rst {
- pins = "gpio_pwrctrl3";
- function = "pin_fun3";
- };
-
- rk806_dvs3_dvs: rk806_dvs3_dvs {
- pins = "gpio_pwrctrl3";
- function = "pin_fun4";
- };
-
- rk806_dvs3_gpio: rk806_dvs3_gpio {
- pins = "gpio_pwrctrl3";
- function = "pin_fun5";
- };
- };
-
- regulators {
- vdd_gpu_s0: DCDC_REG1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_npu_s0: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_npu_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu_mem_s0: DCDC_REG5 {
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
- regulator-name = "vdd_gpu_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_npu_mem_s0: DCDC_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_npu_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: DCDC_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vdd_vdenc_mem_s0: DCDC_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd2_ddr_s3: DCDC_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v1_nldo_s3: DCDC_REG10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1100000>;
- };
- };
-
- avcc_1v8_s0: PLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd1_1v8_ddr_s3: PLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd1_1v8_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_codec_s0: PLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avcc_1v8_codec_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s3: PLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd_s0: PLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_1v8_s3: PLDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_1v8_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: NLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_0v75_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd2l_0v9_ddr_s3: NLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdd2l_0v9_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_0v75_hdmi_edp_s0: NLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <837500>;
- regulator-max-microvolt = <837500>;
- regulator-name = "vdd_0v75_hdmi_edp_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v75_s0: NLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: NLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- rk806slave: rk806slave@1 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x01>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
-
- /* 0: restart PMU;
- * 1: reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode;
- * 2: Reset all the power off reset registers,
- * forcing the state to switch to ACTIVE mode,
- * and simultaneously pull down the RESETB PIN for 5mS before releasing
- */
- pmic-reset-func = <1>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_2v0_pldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- pwrkey {
- status = "disabled";
- };
-
- pinctrl_slave_rk806: pinctrl_slave_rk806 {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_slave_dvs1_null: rk806_slave_dvs1_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs1_slp: rk806_slave_dvs1_slp {
- pins = "gpio_pwrctrl1";
- function = "pin_fun1";
- };
-
- rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn {
- pins = "gpio_pwrctrl1";
- function = "pin_fun2";
- };
-
- rk806_slave_dvs1_rst: rk806_slave_dvs1_rst {
- pins = "gpio_pwrctrl1";
- function = "pin_fun3";
- };
-
- rk806_slave_dvs2_null: rk806_slave_dvs2_null {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs2_slp: rk806_slave_dvs2_slp {
- pins = "gpio_pwrctrl2";
- function = "pin_fun1";
- };
-
- rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn {
- pins = "gpio_pwrctrl2";
- function = "pin_fun2";
- };
-
- rk806_slave_dvs2_rst: rk806_slave_dvs2_rst {
- pins = "gpio_pwrctrl2";
- function = "pin_fun3";
- };
-
- rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs {
- pins = "gpio_pwrctrl2";
- function = "pin_fun4";
- };
-
- rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio {
- pins = "gpio_pwrctrl2";
- function = "pin_fun5";
- };
-
- rk806_slave_dvs3_null: rk806_slave_dvs3_null {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs3_slp: rk806_slave_dvs3_slp {
- pins = "gpio_pwrctrl3";
- function = "pin_fun1";
- };
-
- rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn {
- pins = "gpio_pwrctrl3";
- function = "pin_fun2";
- };
-
- rk806_slave_dvs3_rst: rk806_slave_dvs3_rst {
- pins = "gpio_pwrctrl3";
- function = "pin_fun3";
- };
-
- rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs {
- pins = "gpio_pwrctrl3";
- function = "pin_fun4";
- };
-
- rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio {
- pins = "gpio_pwrctrl3";
- function = "pin_fun5";
- };
- };
-
- regulators {
- vdd_cpu_big1_s0: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big0_s0: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_mem_s0: DCDC_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big1_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
-
- vdd_cpu_big0_mem_s0: DCDC_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big0_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: DCDC_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_mem_s0: DCDC_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vddq_ddr_s0: DCDC_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: DCDC_REG10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_cam_s0: PLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd1v8_ddr_pll_s0: PLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd1v8_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_1v8_pll_s0: PLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_1v8_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_sd_s0: PLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_2v8_cam_s0: PLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_2v8_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: PLDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_pll_s0: NLDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_0v75_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_pll_s0: NLDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v85_s0: NLDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_0v85_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_cam_s0: NLDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_1v2_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_s0: NLDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_1v2_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-lcd.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-lcd.dtsi (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-lcd.dtsi (nonexistent)
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-&dsi1 {
- status = "disabled";
-};
-
-&dsi1_panel {
- status = "disabled";
- reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>;
- enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_rst_gpio>;
-};
-
-&dsi1_in_vp2 {
- status = "disabled";
-};
-
-&dsi1_in_vp3 {
- status = "disabled";
-};
-
-&route_dsi1 {
- status = "disabled";
- connect = <&vp3_out_dsi1>;
-};
-
-&i2c7 {
- status = "okay";
-
- gt9xx_0: touchscreen@14 {
- compatible = "goodix,gt9271";
- reg = <0x14>;
- interrupt-parent = <&gpio2>;
- interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- irq-gpios = <&gpio2 RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
- touchscreen-inverted-x;
- //touchscreen-inverted-y;
- touchscreen-swapped-x-y;
- touchscreen-size-x = <1280>;
- touchscreen-size-y = <800>;
- status = "okay";
- };
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts (revision 152)
@@ -1,325 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
/dts-v1/;
-#include "rk3588-orangepi-5-plus.dtsi"
-#include "rk3588-linux.dtsi"
-#include "rk3588-orangepi-5-plus-lcd.dtsi"
-#include "rk3588-orangepi-5-plus-camera1.dtsi"
+#include "rk3588.dtsi"
/ {
- model = "RK3588 OPi 5 Plus";
+ model = "Orange Pi 5 Plus";
compatible = "rockchip,rk3588-orangepi-5-plus", "rockchip,rk3588";
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 =<&leds_rgb>;
- status = "okay";
+ aliases {
+ mmc0 = &sdhci;
+ serial2 = &uart2;
+ };
- blue_led@1 {
- gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
- label = "blue_led";
- linux,default-trigger = "heartbeat";
- linux,default-trigger-delay-ms = <0>;
- };
-
- green_led@2 {
- gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
- label = "green_led";
- linux,default-trigger = "heartbeat";
- linux,default-trigger-delay-ms = <0>;
- };
+ chosen {
+ stdout-path = "serial2:1500000n8";
};
- fan: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- pwms = <&pwm3 0 50000 0>;
- cooling-levels = <0 50 100 150 200 255>;
- rockchip,temp-trips = <
- 50000 1
- 55000 2
- 60000 3
- 65000 4
- 70000 5
- >;
-
- status = "okay";
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
};
&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
status = "okay";
};
-&mipi_dcphy0 {
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
-
-&mipi_dcphy1 {
- status = "okay";
-};
-
-&rkcif {
- status = "okay";
-};
-
-&rkcif_mmu {
- status = "okay";
-};
-
-&rkisp0 {
- status = "okay";
-};
-
-&isp0_mmu {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* Fan */
-&pwm3 {
- status = "okay";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm3m1_pins>;
-};
-
-/* watchdog */
-&wdt {
- status = "okay";
-};
-
-&sfc {
- status = "okay";
- max-freq = <100000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&fspim1_pins>;
-
- spi_flash: spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <100000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- status = "okay";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- loader@0 {
- label = "loader";
- reg = <0x0 0x1000000>;
- };
- };
- };
-};
-
-&pwm15 {
- compatible = "rockchip,remotectl-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm15m1_pins>;
- remote_pwm_id = <3>;
- handle_cpu_id = <1>;
- remote_support_psci = <0>;
- status = "okay";
-
- ir_key1 {
- rockchip,usercode = <0xfb04>;
- rockchip,key_table =
- <0xa3 KEY_ENTER>,
- <0xe4 388>,
- <0xf5 KEY_BACK>,
- <0xbb KEY_UP>,
- <0xe2 KEY_DOWN>,
- <0xe3 KEY_LEFT>,
- <0xb7 KEY_RIGHT>,
- <0xe0 KEY_HOME>,
- <0xba KEY_VOLUMEUP>,
- <0xda KEY_VOLUMEUP>,
- <0xe6 KEY_VOLUMEDOWN>,
- <0xdb KEY_VOLUMEDOWN>,
- <0xbc KEY_SEARCH>,
- <0xb2 KEY_POWER>,
- <0xe5 KEY_POWER>,
- <0xde KEY_POWER>,
- <0xdc KEY_MUTE>,
- <0xa2 KEY_MENU>,
- <0xec KEY_1>,
- <0xef KEY_2>,
- <0xee KEY_3>,
- <0xf0 KEY_4>,
- <0xf3 KEY_5>,
- <0xf2 KEY_6>,
- <0xf4 KEY_7>,
- <0xf7 KEY_8>,
- <0xf6 KEY_9>,
- <0xb8 KEY_0>;
- };
-};
-
-&pinctrl {
- leds_gpio {
- leds_rgb: leds-rgb {
- rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-/*** 40 pins ***/
-&i2c2 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m0_xfer>;
-};
-
-&can0 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can0m0_pins>;
- assigned-clocks = <&cru CLK_CAN0>;
- assigned-clock-rates = <200000000>;
-};
-
-&can1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can1m0_pins>;
- assigned-clocks = <&cru CLK_CAN1>;
- assigned-clock-rates = <200000000>;
-};
-
-&pwm0 {
- status = "disabled";
-};
-
-&pwm1 {
- status = "disabled";
-};
-
-&pwm14 {
- status = "disabled";
-};
-
-&spi0 {
- status = "disabled";
- assigned-clocks = <&cru CLK_SPI0>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-};
-
-&uart3 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m1_xfer>;
-};
-
-&uart4 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m2_xfer>;
-};
-
-&i2c2 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m4_xfer>;
-};
-
-&i2c4 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4m3_xfer>;
-};
-
-&i2c5 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5m3_xfer>;
-};
-
-&i2c8 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c8m2_xfer>;
-};
-
-&uart1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m1_xfer>;
-};
-
-&uart6 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart6m1_xfer>;
-};
-
-&uart7 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7m2_xfer>;
-};
-
-&uart8 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart8m1_xfer>;
-};
-
-&pwm10 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm10m0_pins>;
-};
-
-&pwm11 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm11m0_pins>;
-};
-
-&pwm12 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm12m0_pins>;
-};
-
-&pwm13 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm13m2_pins>;
- //pinctrl-0 = <&pwm13m0_pins>;
-};
-
-&spi4 {
- status = "disabled";
- assigned-clocks = <&cru CLK_SPI4>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-};
-/*** 40 pins ***/
-
-&hdmirx_ctrler {
- status = "disabled";
-};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts (revision 152)
@@ -1,434 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
/dts-v1/;
-#include "rk3588s-orangepi-5.dtsi"
-#include "rk3588-linux.dtsi"
-#include "rk3588s-orangepi-5-lcd.dtsi"
+#include "rk3588.dtsi"
-#include "rk3588s-orangepi-5-camera1.dtsi"
-#include "rk3588s-orangepi-5-camera2.dtsi"
-#include "rk3588s-orangepi-5-camera3.dtsi"
-
/ {
model = "Orange Pi 5";
compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
- vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sd_s0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
- enable-active-low;
- vin-supply = <&vcc_3v3_s3>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
+ aliases {
+ mmc0 = &sdhci;
+ serial2 = &uart2;
};
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
+ chosen {
+ stdout-path = "serial2:1500000n8";
};
- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 {
+ vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie2x1l2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- regulator-boot-on;
+ regulator-name = "vcc5v0_sys";
regulator-always-on;
- gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 =<&leds_gpio>;
- status = "okay";
-
- led@1 {
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
- label = "status_led";
- linux,default-trigger = "heartbeat";
- linux,default-trigger-delay-ms = <0>;
- };
- };
-};
-
-&gmac1 {
- /* Use rgmii-rxid mode to disable rx delay inside Soc */
- phy-mode = "rgmii-rxid";
- clock_in_out = "output";
-
- snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1_miim
- &gmac1_tx_bus2
- &gmac1_rx_bus2
- &gmac1_rgmii_clk
- &gmac1_rgmii_bus>;
-
- tx_delay = <0x42>;
- /* rx_delay = <0x3f>; */
-
- phy-handle = <&rgmii_phy1>;
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- };
-};
-
-&hdmi0 {
- enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- cec-enable;
- status = "okay";
-};
-
-&hdmi0_in_vp0 {
- status = "okay";
-};
-
-&hdmi0_sound {
- status = "okay";
-};
-
-&hdptxphy_hdmi0 {
- status = "okay";
-};
-
-&route_hdmi0{
- status = "okay";
-};
-
-&i2s5_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- status = "okay";
- rockchip,i2s-tx-route = <3 2 1 0>;
- rockchip,i2s-rx-route = <1 3 2 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclk
- &i2s1m0_lrck
- &i2s1m0_sdi1
- &i2s1m0_sdo3>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
-
- vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_cpu_big0_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
-
- vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
- compatible = "rockchip,rk8603";
- reg = <0x43>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_cpu_big1_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
};
-&i2c2 {
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
status = "okay";
-
- vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_npu_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
};
-/*
- pin3: GPIO1_B7
- pin5: GPIO1_B6
-*/
-&i2c5 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5m3_xfer>;
-};
-
-&uart1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m1_xfer>;
-};
-
-&pwm13 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm13m2_pins>;
-};
-
-/*
- pin7: GPIO1_C6
-*/
-&pwm15 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm15m2_pins>;
-};
-
-/*
- pin11: GPIO4_B2
- pin13: GPIO4_B3
-*/
-&pwm14 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm14m1_pins>;
-};
-
-&can1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can1m1_pins>;
- assigned-clocks = <&cru CLK_CAN1>;
- assigned-clock-rates = <200000000>;
-};
-
-/*
- pin15: GPIO0_D4
- pin12: GPIO0_D5
-*/
-&can2 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can2m1_pins>;
- assigned-clocks = <&cru CLK_CAN2>;
- assigned-clock-rates = <200000000>;
-};
-
-/*
- pin19: GPIO1_C1
- pin21: GPIO1_C0
- pin23: GPIO1_C2
- pin24: GPIO1_C4
-*/
-&spi4 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
- assigned-clocks = <&cru CLK_SPI4>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-
- spi_dev@1 {
- compatible = "rockchip,spidev";
- reg = <1>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&i2c3 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m0_xfer>;
-};
-
-&uart3 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m0_xfer>;
-};
-
-&pwm3 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm3m2_pins>;
- //pinctrl-0 = <&pwm3m0_pins>;
-};
-
-/*
- pin8: GPIO4_A3
- pin10: GPIO4_A4
-*/
-&uart0 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0m2_xfer>;
-};
-
-/*
- pin16: GPIO1_D3
- pin18: GPIO1_D2
-*/
-&uart4 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m0_xfer>;
-};
-
-&i2c1 {
- status = "disabled";
- pinctrl-names = "default";
- //pinctrl-0 = <&i2c1m4_xfer>;
- pinctrl-0 = <&i2c1m2_xfer>;
-};
-
-&pwm0 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm0m1_pins>;
-};
-
-/*
- pin26: GPIO1_A3
-*/
-&pwm1 {
- status = "disabled";
- pinctrl-names = "active";
- //pinctrl-0 = <&pwm1m2_pins>;
- pinctrl-0 = <&pwm1m1_pins>;
-};
-
-/* watchdog */
-&wdt {
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
-
-&sfc {
- status = "okay";
- max-freq = <100000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&fspim0_pins>;
-
- spi_flash: spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <100000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- status = "okay";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- loader@0 {
- label = "loader";
- reg = <0x0 0x1000000>;
- };
- };
- };
-};
-
-&mipi_dcphy0 {
- status = "okay";
-};
-
-&mipi_dcphy1 {
- status = "okay";
-};
-
-&rkcif {
- status = "okay";
-};
-
-&rkcif_mmu {
- status = "okay";
-};
-
-&rkisp0 {
- status = "okay";
-};
-
-&isp0_mmu {
- status = "okay";
-};
-
-&rkisp1 {
- status = "okay";
-};
-
-&isp1_mmu {
- status = "okay";
-};
-
-&sata0 {
- pinctrl-names = "default";
- pinctrl-0 = <&sata_reset>;
- status = "disabled";
-};
-
-&pcie2x1l2 {
- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
- rockchip,skip-scan-in-resume;
- status = "okay";
-};
-
-&pinctrl
-{
- gpio-func {
- leds_gpio: leds-gpio {
- rockchip,pins =
- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts (revision 151)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts (revision 152)
@@ -1,417 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
/dts-v1/;
-#include "rk3588s-orangepi-5.dtsi"
-#include "rk3588-linux.dtsi"
-#include "rk3588s-orangepi-5-lcd.dtsi"
+#include "rk3588.dtsi"
-#include "rk3588s-orangepi-5-camera1.dtsi"
-#include "rk3588s-orangepi-5-camera2.dtsi"
-#include "rk3588s-orangepi-5-camera3.dtsi"
-
/ {
- model = "Orange Pi 5";
- compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
+ model = "Orange Pi 5B";
+ compatible = "rockchip,rk3588s-orangepi-5b", "rockchip,rk3588";
- vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sd_s0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
- enable-active-low;
- vin-supply = <&vcc_3v3_s3>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
+ aliases {
+ mmc0 = &sdhci;
+ serial2 = &uart2;
};
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
+ chosen {
+ stdout-path = "serial2:1500000n8";
};
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 =<&leds_gpio>;
- status = "okay";
-
- led@1 {
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
- label = "status_led";
- linux,default-trigger = "heartbeat";
- linux,default-trigger-delay-ms = <0>;
- };
- };
-};
-
-&gmac1 {
- /* Use rgmii-rxid mode to disable rx delay inside Soc */
- phy-mode = "rgmii-rxid";
- clock_in_out = "output";
-
- snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1_miim
- &gmac1_tx_bus2
- &gmac1_rx_bus2
- &gmac1_rgmii_clk
- &gmac1_rgmii_bus>;
-
- tx_delay = <0x42>;
- /* rx_delay = <0x3f>; */
-
- phy-handle = <&rgmii_phy1>;
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- };
-};
-
-&hdmi0 {
- enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- cec-enable;
- status = "okay";
-};
-
-&hdmi0_in_vp0 {
- status = "okay";
-};
-
-&hdmi0_sound {
- status = "okay";
-};
-
-&hdptxphy_hdmi0 {
- status = "okay";
-};
-
-&route_hdmi0{
- status = "okay";
-};
-
-&i2s5_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- status = "okay";
- rockchip,i2s-tx-route = <3 2 1 0>;
- rockchip,i2s-rx-route = <1 3 2 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclk
- &i2s1m0_lrck
- &i2s1m0_sdi1
- &i2s1m0_sdo3>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
-
- vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_cpu_big0_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
- compatible = "rockchip,rk8603";
- reg = <0x43>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_cpu_big1_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
};
-&i2c2 {
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
status = "okay";
-
- vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "rk860x-reg";
- regulator-name = "vdd_npu_s0";
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-boot-on;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
};
-/*
- pin3: GPIO1_B7
- pin5: GPIO1_B6
-*/
-&i2c5 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5m3_xfer>;
-};
-
-&uart1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m1_xfer>;
-};
-
-&pwm13 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm13m2_pins>;
-};
-
-/*
- pin7: GPIO1_C6
-*/
-&pwm15 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm15m2_pins>;
-};
-
-/*
- pin11: GPIO4_B2
- pin13: GPIO4_B3
-*/
-&pwm14 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm14m1_pins>;
-};
-
-&can1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can1m1_pins>;
- assigned-clocks = <&cru CLK_CAN1>;
- assigned-clock-rates = <200000000>;
-};
-
-/*
- pin15: GPIO0_D4
- pin12: GPIO0_D5
-*/
-&can2 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can2m1_pins>;
- assigned-clocks = <&cru CLK_CAN2>;
- assigned-clock-rates = <200000000>;
-};
-
-/*
- pin19: GPIO1_C1
- pin21: GPIO1_C0
- pin23: GPIO1_C2
- pin24: GPIO1_C4
-*/
-&spi4 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
- assigned-clocks = <&cru CLK_SPI4>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-
- spi_dev@1 {
- compatible = "rockchip,spidev";
- reg = <1>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&i2c3 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m0_xfer>;
-};
-
-&uart3 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m0_xfer>;
-};
-
-&pwm3 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm3m2_pins>;
- //pinctrl-0 = <&pwm3m0_pins>;
-};
-
-/*
- pin8: GPIO4_A3
- pin10: GPIO4_A4
-*/
-&uart0 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0m2_xfer>;
-};
-
-/*
- pin16: GPIO1_D3
- pin18: GPIO1_D2
-*/
-&uart4 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m0_xfer>;
-};
-
-&i2c1 {
- status = "disabled";
- pinctrl-names = "default";
- //pinctrl-0 = <&i2c1m4_xfer>;
- pinctrl-0 = <&i2c1m2_xfer>;
-};
-
-&pwm0 {
- status = "disabled";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm0m1_pins>;
-};
-
-/*
- pin26: GPIO1_A3
-*/
-&pwm1 {
- status = "disabled";
- pinctrl-names = "active";
- //pinctrl-0 = <&pwm1m2_pins>;
- pinctrl-0 = <&pwm1m1_pins>;
-};
-
-/* watchdog */
-&wdt {
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
-
-&sfc {
- status = "disabled";
-};
-
-&mipi_dcphy0 {
- status = "okay";
-};
-
-&mipi_dcphy1 {
- status = "okay";
-};
-
-&rkcif {
- status = "okay";
-};
-
-&rkcif_mmu {
- status = "okay";
-};
-
-&rkisp0 {
- status = "okay";
-};
-
-&isp0_mmu {
- status = "okay";
-};
-
-&rkisp1 {
- status = "okay";
-};
-
-&isp1_mmu {
- status = "okay";
-};
-
-&pcie2x1l2 {
- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- rockchip,skip-scan-in-resume;
- status = "okay";
-};
-
-&wireless_bluetooth {
- BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
- BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
- BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&wireless_wlan {
- WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pinctrl
-{
- wireless-bluetooth {
- uart9_gpios: uart9-gpios {
- rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_gpio: bt-gpio {
- rockchip,pins =
- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
- <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- gpio-func {
- leds_gpio: leds-gpio {
- rockchip,pins =
- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdhci {
- status = "okay";
-};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Radix cross Linux
The main Radix cross Linux repository contains the build scripts of packages, which have the most complete and common functionality for desktop machines
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