Index: v6.x/create-6.1.26-leez-p710-spi-patch/file.list
===================================================================
--- v6.x/create-6.1.26-leez-p710-spi-patch/file.list (revision 150)
+++ v6.x/create-6.1.26-leez-p710-spi-patch/file.list (nonexistent)
@@ -1 +0,0 @@
-linux-6.1.26/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
Index: v6.x/create-6.1.26-leez-p710-spi-patch/create.patch.sh
===================================================================
--- v6.x/create-6.1.26-leez-p710-spi-patch/create.patch.sh (revision 150)
+++ v6.x/create-6.1.26-leez-p710-spi-patch/create.patch.sh (nonexistent)
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-VERSION=6.1.26
-
-tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
-mv linux-$VERSION linux-$VERSION-orig
-
-cp -rf ./linux-$VERSION-new ./linux-$VERSION
-
-diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-leez-p710-spi.patch
-
-mv linux-$VERSION-leez-p710-spi.patch ../patches
-
-rm -rf ./linux-$VERSION
-rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.1.26-leez-p710-spi-patch/create.patch.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.1.26-leez-p710-spi-patch/linux-6.1.26-new/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
===================================================================
--- v6.x/create-6.1.26-leez-p710-spi-patch/linux-6.1.26-new/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts (revision 150)
+++ v6.x/create-6.1.26-leez-p710-spi-patch/linux-6.1.26-new/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts (nonexistent)
@@ -1,674 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Andy Yan <andy.yan@gmail.com>
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Leez RK3399 P710";
- compatible = "leez,p710", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- dc5v_adp: dc5v-adp {
- compatible = "regulator-fixed";
- regulator-name = "dc5v_adapter";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc3v3_lan: vcc3v3-lan {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lan";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host0: vcc5v0_host1: vcc5v0-host {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5500000>;
- regulator-max-microvolt = <5500000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host3: vcc5v0-host3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host3";
- enable-active-high;
- gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host3_en>;
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc5v_adp>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- pwm-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc3v3_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c7>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_hdmi: LDO_REG2 {
- regulator-name = "vcc1v8_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca_1v8: LDO_REG3 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vccio_sd: LDO_REG4 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcc0v9_hdmi: LDO_REG7 {
- regulator-name = "vcc0v9_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2c7 {
- status = "okay";
-};
-
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcc_1v8>;
- sdmmc-supply = <&vccio_sd>;
- gpio1830-supply = <&vcc_3v0>;
-};
-
-&pmu_io_domains {
- status = "okay";
- pmu1830-supply = <&vcc_3v0>;
-};
-
-&pinctrl {
- bt {
- bt_reg_on_h: bt-reg-on-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- usb2 {
- vcc5v0_host3_en: vcc5v0-host3-en {
- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_reg_on_h: wifi-reg-on-h {
- rockchip,pins =
- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-
- vref-supply = <&vcc_1v8>;
-};
-
-&sdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host0>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host1>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- spiflash: flash@0 {
- compatible = "winbond,w25q256", "jedec,spi-nor";
- reg = <0>;
- /* May run faster once verified: */
- spi-max-frequency = <1000000>; // 1MHz
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- spi-flash@0 {
- reg = <0x0 0x2000000>; // 32MiB (Full flash)
- label = "spi-flash";
- };
- };
- };
-};
Index: v6.x/create-6.1.26-dwmac-rk-patch/file.list
===================================================================
--- v6.x/create-6.1.26-dwmac-rk-patch/file.list (revision 150)
+++ v6.x/create-6.1.26-dwmac-rk-patch/file.list (nonexistent)
@@ -1 +0,0 @@
-linux-6.1.26/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
Index: v6.x/create-6.1.26-dwmac-rk-patch/create.patch.sh
===================================================================
--- v6.x/create-6.1.26-dwmac-rk-patch/create.patch.sh (revision 150)
+++ v6.x/create-6.1.26-dwmac-rk-patch/create.patch.sh (nonexistent)
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-VERSION=6.1.26
-
-tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
-mv linux-$VERSION linux-$VERSION-orig
-
-cp -rf ./linux-$VERSION-new ./linux-$VERSION
-
-diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-dwmac-rk.patch
-
-mv linux-$VERSION-dwmac-rk.patch ../patches
-
-rm -rf ./linux-$VERSION
-rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.1.26-dwmac-rk-patch/create.patch.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.1.26-dwmac-rk-patch/linux-6.1.26-new/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
===================================================================
--- v6.x/create-6.1.26-dwmac-rk-patch/linux-6.1.26-new/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c (revision 150)
+++ v6.x/create-6.1.26-dwmac-rk-patch/linux-6.1.26-new/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c (nonexistent)
@@ -1,1991 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/**
- * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
- *
- * Copyright (C) 2014 Chen-Zhi (Roger Chen)
- *
- * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
- */
-
-#include <linux/stmmac.h>
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/phy.h>
-#include <linux/of_net.h>
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/of_gpio.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/consumer.h>
-#include <linux/delay.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <linux/pm_runtime.h>
-
-#include "stmmac_platform.h"
-
-struct rk_priv_data;
-struct rk_gmac_ops {
- void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay);
- void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
- void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
- void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
- void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
- bool enable);
- void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
- bool regs_valid;
- u32 regs[];
-};
-
-struct rk_priv_data {
- struct platform_device *pdev;
- phy_interface_t phy_iface;
- int id;
- struct regulator *regulator;
- bool suspended;
- const struct rk_gmac_ops *ops;
-
- bool clk_enabled;
- bool clock_input;
- bool integrated_phy;
-
- struct clk *clk_mac;
- struct clk *gmac_clkin;
- struct clk *mac_clk_rx;
- struct clk *mac_clk_tx;
- struct clk *clk_mac_ref;
- struct clk *clk_mac_refout;
- struct clk *clk_mac_speed;
- struct clk *aclk_mac;
- struct clk *pclk_mac;
- struct clk *clk_phy;
-
- struct reset_control *phy_reset;
-
- int tx_delay;
- int rx_delay;
-
- struct regmap *grf;
- struct regmap *php_grf;
-};
-
-#define HIWORD_UPDATE(val, mask, shift) \
- ((val) << (shift) | (mask) << ((shift) + 16))
-
-#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
-#define GRF_CLR_BIT(nr) (BIT(nr+16))
-
-#define DELAY_ENABLE(soc, tx, rx) \
- (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
- ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
-
-#define PX30_GRF_GMAC_CON1 0x0904
-
-/* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
- GRF_BIT(6))
-#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define PX30_GMAC_SPEED_100M GRF_BIT(2)
-
-static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
- PX30_GMAC_PHY_INTF_SEL_RMII);
-}
-
-static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- int ret;
-
- if (IS_ERR(bsp_priv->clk_mac_speed)) {
- dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
- PX30_GMAC_SPEED_10M);
-
- ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
- if (ret)
- dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
- __func__, ret);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
- PX30_GMAC_SPEED_100M);
-
- ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
- if (ret)
- dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
- __func__, ret);
-
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops px30_ops = {
- .set_to_rmii = px30_set_to_rmii,
- .set_rmii_speed = px30_set_rmii_speed,
-};
-
-#define RK3128_GRF_MAC_CON0 0x0168
-#define RK3128_GRF_MAC_CON1 0x016c
-
-/* RK3128_GRF_MAC_CON0 */
-#define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
-#define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
-#define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
-#define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-/* RK3128_GRF_MAC_CON1 */
-#define RK3128_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
-#define RK3128_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
-#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
-#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
-#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
-#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
-#define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
-#define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
-#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
-#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
-
-static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_PHY_INTF_SEL_RGMII |
- RK3128_GMAC_RMII_MODE_CLR);
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
- DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
- RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
-}
-
-static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_RMII_CLK_2_5M |
- RK3128_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_RMII_CLK_25M |
- RK3128_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rk3128_ops = {
- .set_to_rgmii = rk3128_set_to_rgmii,
- .set_to_rmii = rk3128_set_to_rmii,
- .set_rgmii_speed = rk3128_set_rgmii_speed,
- .set_rmii_speed = rk3128_set_rmii_speed,
-};
-
-#define RK3228_GRF_MAC_CON0 0x0900
-#define RK3228_GRF_MAC_CON1 0x0904
-
-#define RK3228_GRF_CON_MUX 0x50
-
-/* RK3228_GRF_MAC_CON0 */
-#define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-/* RK3228_GRF_MAC_CON1 */
-#define RK3228_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RK3228_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
-#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
-#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
-#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
-#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
-#define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
-#define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
-#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
-#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
-#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
-#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
-#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
-#define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
-
-/* RK3228_GRF_COM_MUX */
-#define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
-
-static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_PHY_INTF_SEL_RGMII |
- RK3228_GMAC_RMII_MODE_CLR |
- DELAY_ENABLE(RK3228, tx_delay, rx_delay));
-
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
- RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_PHY_INTF_SEL_RMII |
- RK3228_GMAC_RMII_MODE);
-
- /* set MAC to RMII mode */
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
-}
-
-static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_RMII_CLK_2_5M |
- RK3228_GMAC_SPEED_10M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_RMII_CLK_25M |
- RK3228_GMAC_SPEED_100M);
- else
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
-}
-
-static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
-{
- regmap_write(priv->grf, RK3228_GRF_CON_MUX,
- RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
-}
-
-static const struct rk_gmac_ops rk3228_ops = {
- .set_to_rgmii = rk3228_set_to_rgmii,
- .set_to_rmii = rk3228_set_to_rmii,
- .set_rgmii_speed = rk3228_set_rgmii_speed,
- .set_rmii_speed = rk3228_set_rmii_speed,
- .integrated_phy_powerup = rk3228_integrated_phy_powerup,
-};
-
-#define RK3288_GRF_SOC_CON1 0x0248
-#define RK3288_GRF_SOC_CON3 0x0250
-
-/*RK3288_GRF_SOC_CON1*/
-#define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
- GRF_CLR_BIT(8))
-#define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
- GRF_BIT(8))
-#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
-#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
-#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
-#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
-#define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
-#define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
-#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
-#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
-
-/*RK3288_GRF_SOC_CON3*/
-#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
-#define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
-#define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
-#define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_PHY_INTF_SEL_RGMII |
- RK3288_GMAC_RMII_MODE_CLR);
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
- DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
- RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
-}
-
-static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_RMII_CLK_2_5M |
- RK3288_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_RMII_CLK_25M |
- RK3288_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rk3288_ops = {
- .set_to_rgmii = rk3288_set_to_rgmii,
- .set_to_rmii = rk3288_set_to_rmii,
- .set_rgmii_speed = rk3288_set_rgmii_speed,
- .set_rmii_speed = rk3288_set_rmii_speed,
-};
-
-#define RK3308_GRF_MAC_CON0 0x04a0
-
-/* RK3308_GRF_MAC_CON0 */
-#define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
- GRF_BIT(4))
-#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
-#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
-#define RK3308_GMAC_SPEED_100M GRF_BIT(0)
-
-static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
- RK3308_GMAC_PHY_INTF_SEL_RMII);
-}
-
-static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
- RK3308_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
- RK3308_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rk3308_ops = {
- .set_to_rmii = rk3308_set_to_rmii,
- .set_rmii_speed = rk3308_set_rmii_speed,
-};
-
-#define RK3328_GRF_MAC_CON0 0x0900
-#define RK3328_GRF_MAC_CON1 0x0904
-#define RK3328_GRF_MAC_CON2 0x0908
-#define RK3328_GRF_MACPHY_CON1 0xb04
-
-/* RK3328_GRF_MAC_CON0 */
-#define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-/* RK3328_GRF_MAC_CON1 */
-#define RK3328_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RK3328_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
-#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
-#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
-#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
-#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
-#define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
-#define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
-#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
-#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
-#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
-#define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
-#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
-#define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
-
-/* RK3328_GRF_MACPHY_CON1 */
-#define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
-
-static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
- RK3328_GMAC_PHY_INTF_SEL_RGMII |
- RK3328_GMAC_RMII_MODE_CLR |
- RK3328_GMAC_RXCLK_DLY_ENABLE |
- RK3328_GMAC_TXCLK_DLY_ENABLE);
-
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
- RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned int reg;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
- RK3328_GRF_MAC_CON1;
-
- regmap_write(bsp_priv->grf, reg,
- RK3328_GMAC_PHY_INTF_SEL_RMII |
- RK3328_GMAC_RMII_MODE);
-}
-
-static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
- RK3328_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
- RK3328_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
- RK3328_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned int reg;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
- RK3328_GRF_MAC_CON1;
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, reg,
- RK3328_GMAC_RMII_CLK_2_5M |
- RK3328_GMAC_SPEED_10M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, reg,
- RK3328_GMAC_RMII_CLK_25M |
- RK3328_GMAC_SPEED_100M);
- else
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
-}
-
-static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
-{
- regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
- RK3328_MACPHY_RMII_MODE);
-}
-
-static const struct rk_gmac_ops rk3328_ops = {
- .set_to_rgmii = rk3328_set_to_rgmii,
- .set_to_rmii = rk3328_set_to_rmii,
- .set_rgmii_speed = rk3328_set_rgmii_speed,
- .set_rmii_speed = rk3328_set_rmii_speed,
- .integrated_phy_powerup = rk3328_integrated_phy_powerup,
-};
-
-#define RK3366_GRF_SOC_CON6 0x0418
-#define RK3366_GRF_SOC_CON7 0x041c
-
-/* RK3366_GRF_SOC_CON6 */
-#define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_CLR_BIT(11))
-#define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_BIT(11))
-#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
-#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
-#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
-#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
-#define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
-#define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
-#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
-#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
-
-/* RK3366_GRF_SOC_CON7 */
-#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
-#define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
-#define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
-#define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_PHY_INTF_SEL_RGMII |
- RK3366_GMAC_RMII_MODE_CLR);
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
- DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
- RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
-}
-
-static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_RMII_CLK_2_5M |
- RK3366_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_RMII_CLK_25M |
- RK3366_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rk3366_ops = {
- .set_to_rgmii = rk3366_set_to_rgmii,
- .set_to_rmii = rk3366_set_to_rmii,
- .set_rgmii_speed = rk3366_set_rgmii_speed,
- .set_rmii_speed = rk3366_set_rmii_speed,
-};
-
-#define RK3368_GRF_SOC_CON15 0x043c
-#define RK3368_GRF_SOC_CON16 0x0440
-
-/* RK3368_GRF_SOC_CON15 */
-#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_CLR_BIT(11))
-#define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_BIT(11))
-#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
-#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
-#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
-#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
-#define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
-#define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
-#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
-#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
-
-/* RK3368_GRF_SOC_CON16 */
-#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
-#define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
-#define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
-#define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_PHY_INTF_SEL_RGMII |
- RK3368_GMAC_RMII_MODE_CLR);
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
- DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
- RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
-}
-
-static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_RMII_CLK_2_5M |
- RK3368_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_RMII_CLK_25M |
- RK3368_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rk3368_ops = {
- .set_to_rgmii = rk3368_set_to_rgmii,
- .set_to_rmii = rk3368_set_to_rmii,
- .set_rgmii_speed = rk3368_set_rgmii_speed,
- .set_rmii_speed = rk3368_set_rmii_speed,
-};
-
-#define RK3399_GRF_SOC_CON5 0xc214
-#define RK3399_GRF_SOC_CON6 0xc218
-
-/* RK3399_GRF_SOC_CON5 */
-#define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_CLR_BIT(11))
-#define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_BIT(11))
-#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
-#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
-#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
-#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
-#define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
-#define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
-#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
-#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
-
-/* RK3399_GRF_SOC_CON6 */
-#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
-#define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
-#define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
-#define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_PHY_INTF_SEL_RGMII |
- RK3399_GMAC_RMII_MODE_CLR);
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
- DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
- RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
-}
-
-static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10)
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_CLK_2_5M);
- else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_CLK_25M);
- else if (speed == 1000)
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_CLK_125M);
- else
- dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
-}
-
-static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_RMII_CLK_2_5M |
- RK3399_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_RMII_CLK_25M |
- RK3399_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rk3399_ops = {
- .set_to_rgmii = rk3399_set_to_rgmii,
- .set_to_rmii = rk3399_set_to_rmii,
- .set_rgmii_speed = rk3399_set_rgmii_speed,
- .set_rmii_speed = rk3399_set_rmii_speed,
-};
-
-#define RK3568_GRF_GMAC0_CON0 0x0380
-#define RK3568_GRF_GMAC0_CON1 0x0384
-#define RK3568_GRF_GMAC1_CON0 0x0388
-#define RK3568_GRF_GMAC1_CON1 0x038c
-
-/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
-#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RK3568_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
-#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
-#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
-#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
-#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
-#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
-
-/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
-#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- u32 con0, con1;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
- RK3568_GRF_GMAC0_CON0;
- con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
- RK3568_GRF_GMAC0_CON1;
-
- regmap_write(bsp_priv->grf, con0,
- RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
-
- regmap_write(bsp_priv->grf, con1,
- RK3568_GMAC_PHY_INTF_SEL_RGMII |
- RK3568_GMAC_RXCLK_DLY_ENABLE |
- RK3568_GMAC_TXCLK_DLY_ENABLE);
-}
-
-static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- u32 con1;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
- RK3568_GRF_GMAC0_CON1;
- regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
-}
-
-static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned long rate;
- int ret;
-
- switch (speed) {
- case 10:
- rate = 2500000;
- break;
- case 100:
- rate = 25000000;
- break;
- case 1000:
- rate = 125000000;
- break;
- default:
- dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
- return;
- }
-
- ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
- if (ret)
- dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
- __func__, rate, ret);
-}
-
-static const struct rk_gmac_ops rk3568_ops = {
- .set_to_rgmii = rk3568_set_to_rgmii,
- .set_to_rmii = rk3568_set_to_rmii,
- .set_rgmii_speed = rk3568_set_gmac_speed,
- .set_rmii_speed = rk3568_set_gmac_speed,
- .regs_valid = true,
- .regs = {
- 0xfe2a0000, /* gmac0 */
- 0xfe010000, /* gmac1 */
- 0x0, /* sentinel */
- },
-};
-
-/* sys_grf */
-#define RK3588_GRF_GMAC_CON7 0X031c
-#define RK3588_GRF_GMAC_CON8 0X0320
-#define RK3588_GRF_GMAC_CON9 0X0324
-
-#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
-#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
-#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
-#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
-
-#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
-#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
-
-/* php_grf */
-#define RK3588_GRF_GMAC_CON0 0X0008
-#define RK3588_GRF_CLK_CON1 0X0070
-
-#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
- (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
-#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
- (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
-
-#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
-#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
-
-#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
-#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
-
-#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
-#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
-
-#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
- (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
-#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
- (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
-#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
- (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
-
-#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
-#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
-
-static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- u32 offset_con, id = bsp_priv->id;
-
- if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
- dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
- return;
- }
-
- offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
- RK3588_GRF_GMAC_CON8;
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
- RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
- RK3588_GMAC_CLK_RGMII_MODE(id));
-
- regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
- RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
- RK3588_GMAC_TXCLK_DLY_ENABLE(id));
-
- regmap_write(bsp_priv->grf, offset_con,
- RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
- RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->php_grf)) {
- dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
- RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
- RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
-}
-
-static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned int val = 0, id = bsp_priv->id;
-
- switch (speed) {
- case 10:
- if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMA_CLK_RMII_DIV20(id);
- else
- val = RK3588_GMAC_CLK_RGMII_DIV50(id);
- break;
- case 100:
- if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMA_CLK_RMII_DIV2(id);
- else
- val = RK3588_GMAC_CLK_RGMII_DIV5(id);
- break;
- case 1000:
- if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMAC_CLK_RGMII_DIV1(id);
- else
- goto err;
- break;
- default:
- goto err;
- }
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
-
- return;
-err:
- dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
-}
-
-static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
- bool enable)
-{
- unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) :
- RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id);
-
- val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
- RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
-}
-
-static const struct rk_gmac_ops rk3588_ops = {
- .set_to_rgmii = rk3588_set_to_rgmii,
- .set_to_rmii = rk3588_set_to_rmii,
- .set_rgmii_speed = rk3588_set_gmac_speed,
- .set_rmii_speed = rk3588_set_gmac_speed,
- .set_clock_selection = rk3588_set_clock_selection,
- .regs_valid = true,
- .regs = {
- 0xfe1b0000, /* gmac0 */
- 0xfe1c0000, /* gmac1 */
- 0x0, /* sentinel */
- },
-};
-
-#define RV1108_GRF_GMAC_CON0 0X0900
-
-/* RV1108_GRF_GMAC_CON0 */
-#define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
- GRF_BIT(6))
-#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
-#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RV1108_GMAC_SPEED_100M GRF_BIT(2)
-#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
-#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-
-static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
- RV1108_GMAC_PHY_INTF_SEL_RMII);
-}
-
-static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- if (speed == 10) {
- regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
- RV1108_GMAC_RMII_CLK_2_5M |
- RV1108_GMAC_SPEED_10M);
- } else if (speed == 100) {
- regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
- RV1108_GMAC_RMII_CLK_25M |
- RV1108_GMAC_SPEED_100M);
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- }
-}
-
-static const struct rk_gmac_ops rv1108_ops = {
- .set_to_rmii = rv1108_set_to_rmii,
- .set_rmii_speed = rv1108_set_rmii_speed,
-};
-
-#define RV1126_GRF_GMAC_CON0 0X0070
-#define RV1126_GRF_GMAC_CON1 0X0074
-#define RV1126_GRF_GMAC_CON2 0X0078
-
-/* RV1126_GRF_GMAC_CON0 */
-#define RV1126_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RV1126_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
-#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
-#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
-#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
-#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
-#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
-#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
-#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
-#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
-#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
-#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
-
-/* RV1126_GRF_GMAC_CON1 */
-#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-/* RV1126_GRF_GMAC_CON2 */
-#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
-
-static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
- int tx_delay, int rx_delay)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "Missing rockchip,grf property\n");
- return;
- }
-
- regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
- RV1126_GMAC_PHY_INTF_SEL_RGMII |
- RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
- RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
- RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
- RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
-
- regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
- RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
- RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
-
- regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
- RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
- RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
-}
-
-static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (IS_ERR(bsp_priv->grf)) {
- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
- return;
- }
-
- regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
- RV1126_GMAC_PHY_INTF_SEL_RMII);
-}
-
-static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned long rate;
- int ret;
-
- switch (speed) {
- case 10:
- rate = 2500000;
- break;
- case 100:
- rate = 25000000;
- break;
- case 1000:
- rate = 125000000;
- break;
- default:
- dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
- return;
- }
-
- ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
- if (ret)
- dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
- __func__, rate, ret);
-}
-
-static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned long rate;
- int ret;
-
- switch (speed) {
- case 10:
- rate = 2500000;
- break;
- case 100:
- rate = 25000000;
- break;
- default:
- dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
- return;
- }
-
- ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
- if (ret)
- dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
- __func__, rate, ret);
-}
-
-static const struct rk_gmac_ops rv1126_ops = {
- .set_to_rgmii = rv1126_set_to_rgmii,
- .set_to_rmii = rv1126_set_to_rmii,
- .set_rgmii_speed = rv1126_set_rgmii_speed,
- .set_rmii_speed = rv1126_set_rmii_speed,
-};
-
-#define RK_GRF_MACPHY_CON0 0xb00
-#define RK_GRF_MACPHY_CON1 0xb04
-#define RK_GRF_MACPHY_CON2 0xb08
-#define RK_GRF_MACPHY_CON3 0xb0c
-
-#define RK_MACPHY_ENABLE GRF_BIT(0)
-#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
-#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
-
-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
-{
- if (priv->ops->integrated_phy_powerup)
- priv->ops->integrated_phy_powerup(priv);
-
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
-
- regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
- regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
-
- if (priv->phy_reset) {
- /* PHY needs to be disabled before trying to reset it */
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
- if (priv->phy_reset)
- reset_control_assert(priv->phy_reset);
- usleep_range(10, 20);
- if (priv->phy_reset)
- reset_control_deassert(priv->phy_reset);
- usleep_range(10, 20);
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
- msleep(30);
- }
-}
-
-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
-{
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
- if (priv->phy_reset)
- reset_control_assert(priv->phy_reset);
-}
-
-static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
-{
- struct rk_priv_data *bsp_priv = plat->bsp_priv;
- struct device *dev = &bsp_priv->pdev->dev;
- int ret;
-
- bsp_priv->clk_enabled = false;
-
- bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
- if (IS_ERR(bsp_priv->mac_clk_rx))
- dev_err(dev, "cannot get clock %s\n",
- "mac_clk_rx");
-
- bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
- if (IS_ERR(bsp_priv->mac_clk_tx))
- dev_err(dev, "cannot get clock %s\n",
- "mac_clk_tx");
-
- bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
- if (IS_ERR(bsp_priv->aclk_mac))
- dev_err(dev, "cannot get clock %s\n",
- "aclk_mac");
-
- bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
- if (IS_ERR(bsp_priv->pclk_mac))
- dev_err(dev, "cannot get clock %s\n",
- "pclk_mac");
-
- bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
- if (IS_ERR(bsp_priv->clk_mac))
- dev_err(dev, "cannot get clock %s\n",
- "stmmaceth");
-
- if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
- bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
- if (IS_ERR(bsp_priv->clk_mac_ref))
- dev_err(dev, "cannot get clock %s\n",
- "clk_mac_ref");
-
- if (!bsp_priv->clock_input) {
- bsp_priv->clk_mac_refout =
- devm_clk_get(dev, "clk_mac_refout");
- if (IS_ERR(bsp_priv->clk_mac_refout))
- dev_err(dev, "cannot get clock %s\n",
- "clk_mac_refout");
- }
- }
-
- bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
- if (IS_ERR(bsp_priv->clk_mac_speed))
- dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
-
- if (bsp_priv->clock_input) {
- dev_info(dev, "clock input from PHY\n");
- } else {
- if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
- clk_set_rate(bsp_priv->clk_mac, 50000000);
- }
-
- if (plat->phy_node && bsp_priv->integrated_phy) {
- bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
- if (IS_ERR(bsp_priv->clk_phy)) {
- ret = PTR_ERR(bsp_priv->clk_phy);
- dev_err(dev, "Cannot get PHY clock: %d\n", ret);
- return -EINVAL;
- }
- clk_set_rate(bsp_priv->clk_phy, 50000000);
- }
-
- return 0;
-}
-
-static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
-{
- int phy_iface = bsp_priv->phy_iface;
-
- if (enable) {
- if (!bsp_priv->clk_enabled) {
- if (phy_iface == PHY_INTERFACE_MODE_RMII) {
- if (!IS_ERR(bsp_priv->mac_clk_rx))
- clk_prepare_enable(
- bsp_priv->mac_clk_rx);
-
- if (!IS_ERR(bsp_priv->clk_mac_ref))
- clk_prepare_enable(
- bsp_priv->clk_mac_ref);
-
- if (!IS_ERR(bsp_priv->clk_mac_refout))
- clk_prepare_enable(
- bsp_priv->clk_mac_refout);
- }
-
- if (!IS_ERR(bsp_priv->clk_phy))
- clk_prepare_enable(bsp_priv->clk_phy);
-
- if (!IS_ERR(bsp_priv->aclk_mac))
- clk_prepare_enable(bsp_priv->aclk_mac);
-
- if (!IS_ERR(bsp_priv->pclk_mac))
- clk_prepare_enable(bsp_priv->pclk_mac);
-
- if (!IS_ERR(bsp_priv->mac_clk_tx))
- clk_prepare_enable(bsp_priv->mac_clk_tx);
-
- if (!IS_ERR(bsp_priv->clk_mac_speed))
- clk_prepare_enable(bsp_priv->clk_mac_speed);
-
- if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
- bsp_priv->ops->set_clock_selection(bsp_priv,
- bsp_priv->clock_input, true);
-
- /**
- * if (!IS_ERR(bsp_priv->clk_mac))
- * clk_prepare_enable(bsp_priv->clk_mac);
- */
- mdelay(5);
- bsp_priv->clk_enabled = true;
- }
- } else {
- if (bsp_priv->clk_enabled) {
- if (phy_iface == PHY_INTERFACE_MODE_RMII) {
- clk_disable_unprepare(bsp_priv->mac_clk_rx);
-
- clk_disable_unprepare(bsp_priv->clk_mac_ref);
-
- clk_disable_unprepare(bsp_priv->clk_mac_refout);
- }
-
- clk_disable_unprepare(bsp_priv->clk_phy);
-
- clk_disable_unprepare(bsp_priv->aclk_mac);
-
- clk_disable_unprepare(bsp_priv->pclk_mac);
-
- clk_disable_unprepare(bsp_priv->mac_clk_tx);
-
- clk_disable_unprepare(bsp_priv->clk_mac_speed);
-
- if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
- bsp_priv->ops->set_clock_selection(bsp_priv,
- bsp_priv->clock_input, false);
- /**
- * if (!IS_ERR(bsp_priv->clk_mac))
- * clk_disable_unprepare(bsp_priv->clk_mac);
- */
- bsp_priv->clk_enabled = false;
- }
- }
-
- return 0;
-}
-
-static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
-{
- struct regulator *ldo = bsp_priv->regulator;
- int ret;
- struct device *dev = &bsp_priv->pdev->dev;
-
- if (!ldo)
- return 0;
-
- if (enable) {
- ret = regulator_enable(ldo);
- if (ret)
- dev_err(dev, "fail to enable phy-supply\n");
- } else {
- ret = regulator_disable(ldo);
- if (ret)
- dev_err(dev, "fail to disable phy-supply\n");
- }
-
- return 0;
-}
-
-static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
- struct plat_stmmacenet_data *plat,
- const struct rk_gmac_ops *ops)
-{
- struct rk_priv_data *bsp_priv;
- struct device *dev = &pdev->dev;
- struct resource *res;
- int ret;
- const char *strings = NULL;
- int value;
-
- bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
- if (!bsp_priv)
- return ERR_PTR(-ENOMEM);
-
- of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
- bsp_priv->ops = ops;
-
- /* Some SoCs have multiple MAC controllers, which need
- * to be distinguished.
- */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res && ops->regs_valid) {
- int i = 0;
-
- while (ops->regs[i]) {
- if (ops->regs[i] == res->start) {
- bsp_priv->id = i;
- break;
- }
- i++;
- }
- }
-
- bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
- if (IS_ERR(bsp_priv->regulator)) {
- if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
- dev_err(dev, "phy regulator is not available yet, deferred probing\n");
- return ERR_PTR(-EPROBE_DEFER);
- }
- dev_err(dev, "no regulator found\n");
- bsp_priv->regulator = NULL;
- }
-
- ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
- if (ret) {
- dev_err(dev, "Can not read property: clock_in_out.\n");
- bsp_priv->clock_input = true;
- } else {
- dev_info(dev, "clock input or output? (%s).\n",
- strings);
- if (!strcmp(strings, "input"))
- bsp_priv->clock_input = true;
- else
- bsp_priv->clock_input = false;
- }
-
- ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
- if (ret) {
- bsp_priv->tx_delay = 0x30;
- dev_err(dev, "Can not read property: tx_delay.");
- dev_err(dev, "set tx_delay to 0x%x\n",
- bsp_priv->tx_delay);
- } else {
- dev_info(dev, "TX delay(0x%x).\n", value);
- bsp_priv->tx_delay = value;
- }
-
- ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
- if (ret) {
- bsp_priv->rx_delay = 0x10;
- dev_err(dev, "Can not read property: rx_delay.");
- dev_err(dev, "set rx_delay to 0x%x\n",
- bsp_priv->rx_delay);
- } else {
- dev_info(dev, "RX delay(0x%x).\n", value);
- bsp_priv->rx_delay = value;
- }
-
- bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
- "rockchip,grf");
- bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
- "rockchip,php-grf");
-
- if (plat->phy_node) {
- bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
- "phy-is-integrated");
- if (bsp_priv->integrated_phy) {
- bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
- if (IS_ERR(bsp_priv->phy_reset)) {
- dev_err(&pdev->dev, "No PHY reset control found.\n");
- bsp_priv->phy_reset = NULL;
- }
- }
- }
- dev_info(dev, "integrated PHY? (%s).\n",
- bsp_priv->integrated_phy ? "yes" : "no");
-
- bsp_priv->pdev = pdev;
-
- return bsp_priv;
-}
-
-static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
-{
- switch (bsp_priv->phy_iface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- if (!bsp_priv->ops->set_to_rgmii)
- return -EINVAL;
- break;
- case PHY_INTERFACE_MODE_RMII:
- if (!bsp_priv->ops->set_to_rmii)
- return -EINVAL;
- break;
- default:
- dev_err(&bsp_priv->pdev->dev,
- "unsupported interface %d", bsp_priv->phy_iface);
- }
- return 0;
-}
-
-static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
-{
- int ret;
- struct device *dev = &bsp_priv->pdev->dev;
-
- ret = rk_gmac_check_ops(bsp_priv);
- if (ret)
- return ret;
-
- ret = gmac_clk_enable(bsp_priv, true);
- if (ret)
- return ret;
-
- /*rmii or rgmii*/
- switch (bsp_priv->phy_iface) {
- case PHY_INTERFACE_MODE_RGMII:
- dev_info(dev, "init for RGMII\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
- bsp_priv->rx_delay);
- break;
- case PHY_INTERFACE_MODE_RGMII_ID:
- dev_info(dev, "init for RGMII_ID\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
- break;
- case PHY_INTERFACE_MODE_RGMII_RXID:
- dev_info(dev, "init for RGMII_RXID\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
- break;
- case PHY_INTERFACE_MODE_RGMII_TXID:
- dev_info(dev, "init for RGMII_TXID\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
- break;
- case PHY_INTERFACE_MODE_RMII:
- dev_info(dev, "init for RMII\n");
- bsp_priv->ops->set_to_rmii(bsp_priv);
- break;
- default:
- dev_err(dev, "NO interface defined!\n");
- }
-
- ret = phy_power_on(bsp_priv, true);
- if (ret) {
- gmac_clk_enable(bsp_priv, false);
- return ret;
- }
-
- pm_runtime_enable(dev);
- pm_runtime_get_sync(dev);
-
- if (bsp_priv->integrated_phy)
- rk_gmac_integrated_phy_powerup(bsp_priv);
-
- return 0;
-}
-
-static void rk_gmac_powerdown(struct rk_priv_data *gmac)
-{
- struct device *dev = &gmac->pdev->dev;
-
- if (gmac->integrated_phy)
- rk_gmac_integrated_phy_powerdown(gmac);
-
- pm_runtime_put_sync(dev);
- pm_runtime_disable(dev);
-
- phy_power_on(gmac, false);
- gmac_clk_enable(gmac, false);
-}
-
-static void rk_fix_speed(void *priv, unsigned int speed)
-{
- struct rk_priv_data *bsp_priv = priv;
- struct device *dev = &bsp_priv->pdev->dev;
-
- switch (bsp_priv->phy_iface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- if (bsp_priv->ops->set_rgmii_speed)
- bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
- break;
- case PHY_INTERFACE_MODE_RMII:
- if (bsp_priv->ops->set_rmii_speed)
- bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
- break;
- default:
- dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
- }
-}
-
-static int rk_gmac_probe(struct platform_device *pdev)
-{
- struct plat_stmmacenet_data *plat_dat;
- struct stmmac_resources stmmac_res;
- const struct rk_gmac_ops *data;
- int ret;
-
- data = of_device_get_match_data(&pdev->dev);
- if (!data) {
- dev_err(&pdev->dev, "no of match data provided\n");
- return -EINVAL;
- }
-
- ret = stmmac_get_platform_resources(pdev, &stmmac_res);
- if (ret)
- return ret;
-
- plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
- if (IS_ERR(plat_dat))
- return PTR_ERR(plat_dat);
-
- /* If the stmmac is not already selected as gmac4,
- * then make sure we fallback to gmac.
- */
- if (!plat_dat->has_gmac4)
- plat_dat->has_gmac = true;
- plat_dat->fix_mac_speed = rk_fix_speed;
-
- plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
- if (IS_ERR(plat_dat->bsp_priv)) {
- ret = PTR_ERR(plat_dat->bsp_priv);
- goto err_remove_config_dt;
- }
-
- ret = rk_gmac_clk_init(plat_dat);
- if (ret)
- goto err_remove_config_dt;
-
- ret = rk_gmac_powerup(plat_dat->bsp_priv);
- if (ret)
- goto err_remove_config_dt;
-
- ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
- if (ret)
- goto err_gmac_powerdown;
-
- return 0;
-
-err_gmac_powerdown:
- rk_gmac_powerdown(plat_dat->bsp_priv);
-err_remove_config_dt:
- stmmac_remove_config_dt(pdev, plat_dat);
-
- return ret;
-}
-
-static int rk_gmac_remove(struct platform_device *pdev)
-{
- struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
- int ret = stmmac_dvr_remove(&pdev->dev);
-
- rk_gmac_powerdown(bsp_priv);
-
- return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int rk_gmac_suspend(struct device *dev)
-{
- struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
- int ret = stmmac_suspend(dev);
-
- /* Keep the PHY up if we use Wake-on-Lan. */
- if (!device_may_wakeup(dev)) {
- rk_gmac_powerdown(bsp_priv);
- bsp_priv->suspended = true;
- }
-
- return ret;
-}
-
-static int rk_gmac_resume(struct device *dev)
-{
- struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
-
- /* The PHY was up for Wake-on-Lan. */
- if (bsp_priv->suspended) {
- rk_gmac_powerup(bsp_priv);
- bsp_priv->suspended = false;
- }
-
- return stmmac_resume(dev);
-}
-#endif /* CONFIG_PM_SLEEP */
-
-static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
-
-static const struct of_device_id rk_gmac_dwmac_match[] = {
- { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
- { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
- { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
- { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
- { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
- { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
- { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
- { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
- { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
- { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
- { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
- { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
- { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
- { }
-};
-MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
-
-static struct platform_driver rk_gmac_dwmac_driver = {
- .probe = rk_gmac_probe,
- .remove = rk_gmac_remove,
- .driver = {
- .name = "rk_gmac-dwmac",
- .pm = &rk_gmac_pm_ops,
- .of_match_table = rk_gmac_dwmac_match,
- },
-};
-module_platform_driver(rk_gmac_dwmac_driver);
-
-MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
-MODULE_LICENSE("GPL");
Index: v6.x/create-6.1.26-sdhci-reset-patch/file.list
===================================================================
--- v6.x/create-6.1.26-sdhci-reset-patch/file.list (revision 150)
+++ v6.x/create-6.1.26-sdhci-reset-patch/file.list (nonexistent)
@@ -1 +0,0 @@
-linux-6.1.26/drivers/mmc/host/sdhci.c
Index: v6.x/create-6.1.26-sdhci-reset-patch/create.patch.sh
===================================================================
--- v6.x/create-6.1.26-sdhci-reset-patch/create.patch.sh (revision 150)
+++ v6.x/create-6.1.26-sdhci-reset-patch/create.patch.sh (nonexistent)
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-VERSION=6.1.26
-
-tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
-mv linux-$VERSION linux-$VERSION-orig
-
-cp -rf ./linux-$VERSION-new ./linux-$VERSION
-
-diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-sdhci-reset.patch
-
-mv linux-$VERSION-sdhci-reset.patch ../patches
-
-rm -rf ./linux-$VERSION
-rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.1.26-sdhci-reset-patch/create.patch.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.1.26-sdhci-reset-patch/linux-6.1.26-new/drivers/mmc/host/sdhci.c
===================================================================
--- v6.x/create-6.1.26-sdhci-reset-patch/linux-6.1.26-new/drivers/mmc/host/sdhci.c (revision 150)
+++ v6.x/create-6.1.26-sdhci-reset-patch/linux-6.1.26-new/drivers/mmc/host/sdhci.c (nonexistent)
@@ -1,5005 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
- *
- * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
- *
- * Thanks to the following companies for their support:
- *
- * - JMicron (hardware and technical support)
- */
-
-#include <linux/bitfield.h>
-#include <linux/delay.h>
-#include <linux/dmaengine.h>
-#include <linux/ktime.h>
-#include <linux/highmem.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-#include <linux/scatterlist.h>
-#include <linux/sizes.h>
-#include <linux/regulator/consumer.h>
-#include <linux/pm_runtime.h>
-#include <linux/of.h>
-
-#include <linux/leds.h>
-
-#include <linux/mmc/mmc.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-#include <linux/mmc/sdio.h>
-#include <linux/mmc/slot-gpio.h>
-
-#include "sdhci.h"
-
-#define DRIVER_NAME "sdhci"
-
-#define DBG(f, x...) \
- pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
-
-#define SDHCI_DUMP(f, x...) \
- pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
-
-#define MAX_TUNING_LOOP 40
-
-static unsigned int debug_quirks = 0;
-static unsigned int debug_quirks2;
-
-static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
-
-static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
-
-void sdhci_dumpregs(struct sdhci_host *host)
-{
- SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
-
- SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
- sdhci_readl(host, SDHCI_DMA_ADDRESS),
- sdhci_readw(host, SDHCI_HOST_VERSION));
- SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
- sdhci_readw(host, SDHCI_BLOCK_SIZE),
- sdhci_readw(host, SDHCI_BLOCK_COUNT));
- SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
- sdhci_readl(host, SDHCI_ARGUMENT),
- sdhci_readw(host, SDHCI_TRANSFER_MODE));
- SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
- sdhci_readl(host, SDHCI_PRESENT_STATE),
- sdhci_readb(host, SDHCI_HOST_CONTROL));
- SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
- sdhci_readb(host, SDHCI_POWER_CONTROL),
- sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
- SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
- sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
- sdhci_readw(host, SDHCI_CLOCK_CONTROL));
- SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
- sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
- sdhci_readl(host, SDHCI_INT_STATUS));
- SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
- sdhci_readl(host, SDHCI_INT_ENABLE),
- sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
- SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
- sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
- sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
- SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
- sdhci_readl(host, SDHCI_CAPABILITIES),
- sdhci_readl(host, SDHCI_CAPABILITIES_1));
- SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
- sdhci_readw(host, SDHCI_COMMAND),
- sdhci_readl(host, SDHCI_MAX_CURRENT));
- SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
- sdhci_readl(host, SDHCI_RESPONSE),
- sdhci_readl(host, SDHCI_RESPONSE + 4));
- SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
- sdhci_readl(host, SDHCI_RESPONSE + 8),
- sdhci_readl(host, SDHCI_RESPONSE + 12));
- SDHCI_DUMP("Host ctl2: 0x%08x\n",
- sdhci_readw(host, SDHCI_HOST_CONTROL2));
-
- if (host->flags & SDHCI_USE_ADMA) {
- if (host->flags & SDHCI_USE_64_BIT_DMA) {
- SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
- sdhci_readl(host, SDHCI_ADMA_ERROR),
- sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
- sdhci_readl(host, SDHCI_ADMA_ADDRESS));
- } else {
- SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
- sdhci_readl(host, SDHCI_ADMA_ERROR),
- sdhci_readl(host, SDHCI_ADMA_ADDRESS));
- }
- }
-
- if (host->ops->dump_vendor_regs)
- host->ops->dump_vendor_regs(host);
-
- SDHCI_DUMP("============================================\n");
-}
-EXPORT_SYMBOL_GPL(sdhci_dumpregs);
-
-/*****************************************************************************\
- * *
- * Low level functions *
- * *
-\*****************************************************************************/
-
-static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
-{
- u16 ctrl2;
-
- ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- if (ctrl2 & SDHCI_CTRL_V4_MODE)
- return;
-
- ctrl2 |= SDHCI_CTRL_V4_MODE;
- sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
-}
-
-/*
- * This can be called before sdhci_add_host() by Vendor's host controller
- * driver to enable v4 mode if supported.
- */
-void sdhci_enable_v4_mode(struct sdhci_host *host)
-{
- host->v4_mode = true;
- sdhci_do_enable_v4_mode(host);
-}
-EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
-
-static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
-{
- return cmd->data || cmd->flags & MMC_RSP_BUSY;
-}
-
-static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
-{
- u32 present;
-
- if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
- !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
- return;
-
- if (enable) {
- present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
- SDHCI_CARD_PRESENT;
-
- host->ier |= present ? SDHCI_INT_CARD_REMOVE :
- SDHCI_INT_CARD_INSERT;
- } else {
- host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
- }
-
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-}
-
-static void sdhci_enable_card_detection(struct sdhci_host *host)
-{
- sdhci_set_card_detection(host, true);
-}
-
-static void sdhci_disable_card_detection(struct sdhci_host *host)
-{
- sdhci_set_card_detection(host, false);
-}
-
-static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
-{
- if (host->bus_on)
- return;
- host->bus_on = true;
- pm_runtime_get_noresume(mmc_dev(host->mmc));
-}
-
-static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
-{
- if (!host->bus_on)
- return;
- host->bus_on = false;
- pm_runtime_put_noidle(mmc_dev(host->mmc));
-}
-
-void sdhci_reset(struct sdhci_host *host, u8 mask)
-{
- ktime_t timeout;
-
- sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
-
- if (mask & SDHCI_RESET_ALL) {
- host->clock = 0;
- /* Reset-all turns off SD Bus Power */
- if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
- sdhci_runtime_pm_bus_off(host);
- if (host->ops->voltage_switch)
- host->ops->voltage_switch(host);
- }
-
- /* Wait max 100 ms */
- timeout = ktime_add_ms(ktime_get(), 100);
-
- /* hw clears the bit when it's done */
- while (1) {
- bool timedout = ktime_after(ktime_get(), timeout);
-
- if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
- break;
- if (timedout) {
- pr_err("%s: Reset 0x%x never completed.\n",
- mmc_hostname(host->mmc), (int)mask);
- sdhci_err_stats_inc(host, CTRL_TIMEOUT);
- sdhci_dumpregs(host);
- return;
- }
- udelay(10);
- }
-}
-EXPORT_SYMBOL_GPL(sdhci_reset);
-
-static bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
-{
- if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
- struct mmc_host *mmc = host->mmc;
-
- if (!mmc->ops->get_cd(mmc))
- return false;
- }
-
- host->ops->reset(host, mask);
-
- return true;
-}
-
-static void sdhci_reset_for_all(struct sdhci_host *host)
-{
- if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
- if (host->ops->enable_dma)
- host->ops->enable_dma(host);
- }
- /* Resetting the controller clears many */
- host->preset_enabled = false;
- }
-}
-
-enum sdhci_reset_reason {
- SDHCI_RESET_FOR_INIT,
- SDHCI_RESET_FOR_REQUEST_ERROR,
- SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
- SDHCI_RESET_FOR_TUNING_ABORT,
- SDHCI_RESET_FOR_CARD_REMOVED,
- SDHCI_RESET_FOR_CQE_RECOVERY,
-};
-
-static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
-{
- if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
- sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- return;
- }
-
- switch (reason) {
- case SDHCI_RESET_FOR_INIT:
- sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- break;
- case SDHCI_RESET_FOR_REQUEST_ERROR:
- case SDHCI_RESET_FOR_TUNING_ABORT:
- case SDHCI_RESET_FOR_CARD_REMOVED:
- case SDHCI_RESET_FOR_CQE_RECOVERY:
- sdhci_do_reset(host, SDHCI_RESET_CMD);
- sdhci_do_reset(host, SDHCI_RESET_DATA);
- break;
- case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
- sdhci_do_reset(host, SDHCI_RESET_DATA);
- break;
- }
-}
-
-#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
-
-static void sdhci_set_default_irqs(struct sdhci_host *host)
-{
- host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
- SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
- SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
- SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
- SDHCI_INT_RESPONSE;
-
- if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
- host->tuning_mode == SDHCI_TUNING_MODE_3)
- host->ier |= SDHCI_INT_RETUNE;
-
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-}
-
-static void sdhci_config_dma(struct sdhci_host *host)
-{
- u8 ctrl;
- u16 ctrl2;
-
- if (host->version < SDHCI_SPEC_200)
- return;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
-
- /*
- * Always adjust the DMA selection as some controllers
- * (e.g. JMicron) can't do PIO properly when the selection
- * is ADMA.
- */
- ctrl &= ~SDHCI_CTRL_DMA_MASK;
- if (!(host->flags & SDHCI_REQ_USE_DMA))
- goto out;
-
- /* Note if DMA Select is zero then SDMA is selected */
- if (host->flags & SDHCI_USE_ADMA)
- ctrl |= SDHCI_CTRL_ADMA32;
-
- if (host->flags & SDHCI_USE_64_BIT_DMA) {
- /*
- * If v4 mode, all supported DMA can be 64-bit addressing if
- * controller supports 64-bit system address, otherwise only
- * ADMA can support 64-bit addressing.
- */
- if (host->v4_mode) {
- ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
- sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
- } else if (host->flags & SDHCI_USE_ADMA) {
- /*
- * Don't need to undo SDHCI_CTRL_ADMA32 in order to
- * set SDHCI_CTRL_ADMA64.
- */
- ctrl |= SDHCI_CTRL_ADMA64;
- }
- }
-
-out:
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-
-static void sdhci_init(struct sdhci_host *host, int soft)
-{
- struct mmc_host *mmc = host->mmc;
- unsigned long flags;
-
- if (soft)
- sdhci_reset_for(host, INIT);
- else
- sdhci_reset_for_all(host);
-
- if (host->v4_mode)
- sdhci_do_enable_v4_mode(host);
-
- spin_lock_irqsave(&host->lock, flags);
- sdhci_set_default_irqs(host);
- spin_unlock_irqrestore(&host->lock, flags);
-
- host->cqe_on = false;
-
- if (soft) {
- /* force clock reconfiguration */
- host->clock = 0;
- host->reinit_uhs = true;
- mmc->ops->set_ios(mmc, &mmc->ios);
- }
-}
-
-static void sdhci_reinit(struct sdhci_host *host)
-{
- u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
-
- sdhci_init(host, 0);
- sdhci_enable_card_detection(host);
-
- /*
- * A change to the card detect bits indicates a change in present state,
- * refer sdhci_set_card_detection(). A card detect interrupt might have
- * been missed while the host controller was being reset, so trigger a
- * rescan to check.
- */
- if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
- mmc_detect_change(host->mmc, msecs_to_jiffies(200));
-}
-
-static void __sdhci_led_activate(struct sdhci_host *host)
-{
- u8 ctrl;
-
- if (host->quirks & SDHCI_QUIRK_NO_LED)
- return;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl |= SDHCI_CTRL_LED;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-
-static void __sdhci_led_deactivate(struct sdhci_host *host)
-{
- u8 ctrl;
-
- if (host->quirks & SDHCI_QUIRK_NO_LED)
- return;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl &= ~SDHCI_CTRL_LED;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-
-#if IS_REACHABLE(CONFIG_LEDS_CLASS)
-static void sdhci_led_control(struct led_classdev *led,
- enum led_brightness brightness)
-{
- struct sdhci_host *host = container_of(led, struct sdhci_host, led);
- unsigned long flags;
-
- spin_lock_irqsave(&host->lock, flags);
-
- if (host->runtime_suspended)
- goto out;
-
- if (brightness == LED_OFF)
- __sdhci_led_deactivate(host);
- else
- __sdhci_led_activate(host);
-out:
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-static int sdhci_led_register(struct sdhci_host *host)
-{
- struct mmc_host *mmc = host->mmc;
-
- if (host->quirks & SDHCI_QUIRK_NO_LED)
- return 0;
-
- snprintf(host->led_name, sizeof(host->led_name),
- "%s::", mmc_hostname(mmc));
-
- host->led.name = host->led_name;
- host->led.brightness = LED_OFF;
- host->led.default_trigger = mmc_hostname(mmc);
- host->led.brightness_set = sdhci_led_control;
-
- return led_classdev_register(mmc_dev(mmc), &host->led);
-}
-
-static void sdhci_led_unregister(struct sdhci_host *host)
-{
- if (host->quirks & SDHCI_QUIRK_NO_LED)
- return;
-
- led_classdev_unregister(&host->led);
-}
-
-static inline void sdhci_led_activate(struct sdhci_host *host)
-{
-}
-
-static inline void sdhci_led_deactivate(struct sdhci_host *host)
-{
-}
-
-#else
-
-static inline int sdhci_led_register(struct sdhci_host *host)
-{
- return 0;
-}
-
-static inline void sdhci_led_unregister(struct sdhci_host *host)
-{
-}
-
-static inline void sdhci_led_activate(struct sdhci_host *host)
-{
- __sdhci_led_activate(host);
-}
-
-static inline void sdhci_led_deactivate(struct sdhci_host *host)
-{
- __sdhci_led_deactivate(host);
-}
-
-#endif
-
-static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
- unsigned long timeout)
-{
- if (sdhci_data_line_cmd(mrq->cmd))
- mod_timer(&host->data_timer, timeout);
- else
- mod_timer(&host->timer, timeout);
-}
-
-static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
-{
- if (sdhci_data_line_cmd(mrq->cmd))
- del_timer(&host->data_timer);
- else
- del_timer(&host->timer);
-}
-
-static inline bool sdhci_has_requests(struct sdhci_host *host)
-{
- return host->cmd || host->data_cmd;
-}
-
-/*****************************************************************************\
- * *
- * Core functions *
- * *
-\*****************************************************************************/
-
-static void sdhci_read_block_pio(struct sdhci_host *host)
-{
- unsigned long flags;
- size_t blksize, len, chunk;
- u32 scratch;
- u8 *buf;
-
- DBG("PIO reading\n");
-
- blksize = host->data->blksz;
- chunk = 0;
-
- local_irq_save(flags);
-
- while (blksize) {
- BUG_ON(!sg_miter_next(&host->sg_miter));
-
- len = min(host->sg_miter.length, blksize);
-
- blksize -= len;
- host->sg_miter.consumed = len;
-
- buf = host->sg_miter.addr;
-
- while (len) {
- if (chunk == 0) {
- scratch = sdhci_readl(host, SDHCI_BUFFER);
- chunk = 4;
- }
-
- *buf = scratch & 0xFF;
-
- buf++;
- scratch >>= 8;
- chunk--;
- len--;
- }
- }
-
- sg_miter_stop(&host->sg_miter);
-
- local_irq_restore(flags);
-}
-
-static void sdhci_write_block_pio(struct sdhci_host *host)
-{
- unsigned long flags;
- size_t blksize, len, chunk;
- u32 scratch;
- u8 *buf;
-
- DBG("PIO writing\n");
-
- blksize = host->data->blksz;
- chunk = 0;
- scratch = 0;
-
- local_irq_save(flags);
-
- while (blksize) {
- BUG_ON(!sg_miter_next(&host->sg_miter));
-
- len = min(host->sg_miter.length, blksize);
-
- blksize -= len;
- host->sg_miter.consumed = len;
-
- buf = host->sg_miter.addr;
-
- while (len) {
- scratch |= (u32)*buf << (chunk * 8);
-
- buf++;
- chunk++;
- len--;
-
- if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
- sdhci_writel(host, scratch, SDHCI_BUFFER);
- chunk = 0;
- scratch = 0;
- }
- }
- }
-
- sg_miter_stop(&host->sg_miter);
-
- local_irq_restore(flags);
-}
-
-static void sdhci_transfer_pio(struct sdhci_host *host)
-{
- u32 mask;
-
- if (host->blocks == 0)
- return;
-
- if (host->data->flags & MMC_DATA_READ)
- mask = SDHCI_DATA_AVAILABLE;
- else
- mask = SDHCI_SPACE_AVAILABLE;
-
- /*
- * Some controllers (JMicron JMB38x) mess up the buffer bits
- * for transfers < 4 bytes. As long as it is just one block,
- * we can ignore the bits.
- */
- if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
- (host->data->blocks == 1))
- mask = ~0;
-
- while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
- if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
- udelay(100);
-
- if (host->data->flags & MMC_DATA_READ)
- sdhci_read_block_pio(host);
- else
- sdhci_write_block_pio(host);
-
- host->blocks--;
- if (host->blocks == 0)
- break;
- }
-
- DBG("PIO transfer complete.\n");
-}
-
-static int sdhci_pre_dma_transfer(struct sdhci_host *host,
- struct mmc_data *data, int cookie)
-{
- int sg_count;
-
- /*
- * If the data buffers are already mapped, return the previous
- * dma_map_sg() result.
- */
- if (data->host_cookie == COOKIE_PRE_MAPPED)
- return data->sg_count;
-
- /* Bounce write requests to the bounce buffer */
- if (host->bounce_buffer) {
- unsigned int length = data->blksz * data->blocks;
-
- if (length > host->bounce_buffer_size) {
- pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
- mmc_hostname(host->mmc), length,
- host->bounce_buffer_size);
- return -EIO;
- }
- if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
- /* Copy the data to the bounce buffer */
- if (host->ops->copy_to_bounce_buffer) {
- host->ops->copy_to_bounce_buffer(host,
- data, length);
- } else {
- sg_copy_to_buffer(data->sg, data->sg_len,
- host->bounce_buffer, length);
- }
- }
- /* Switch ownership to the DMA */
- dma_sync_single_for_device(mmc_dev(host->mmc),
- host->bounce_addr,
- host->bounce_buffer_size,
- mmc_get_dma_dir(data));
- /* Just a dummy value */
- sg_count = 1;
- } else {
- /* Just access the data directly from memory */
- sg_count = dma_map_sg(mmc_dev(host->mmc),
- data->sg, data->sg_len,
- mmc_get_dma_dir(data));
- }
-
- if (sg_count == 0)
- return -ENOSPC;
-
- data->sg_count = sg_count;
- data->host_cookie = cookie;
-
- return sg_count;
-}
-
-static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
-{
- local_irq_save(*flags);
- return kmap_atomic(sg_page(sg)) + sg->offset;
-}
-
-static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
-{
- kunmap_atomic(buffer);
- local_irq_restore(*flags);
-}
-
-void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
- dma_addr_t addr, int len, unsigned int cmd)
-{
- struct sdhci_adma2_64_desc *dma_desc = *desc;
-
- /* 32-bit and 64-bit descriptors have these members in same position */
- dma_desc->cmd = cpu_to_le16(cmd);
- dma_desc->len = cpu_to_le16(len);
- dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
-
- if (host->flags & SDHCI_USE_64_BIT_DMA)
- dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
-
- *desc += host->desc_sz;
-}
-EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
-
-static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
- void **desc, dma_addr_t addr,
- int len, unsigned int cmd)
-{
- if (host->ops->adma_write_desc)
- host->ops->adma_write_desc(host, desc, addr, len, cmd);
- else
- sdhci_adma_write_desc(host, desc, addr, len, cmd);
-}
-
-static void sdhci_adma_mark_end(void *desc)
-{
- struct sdhci_adma2_64_desc *dma_desc = desc;
-
- /* 32-bit and 64-bit descriptors have 'cmd' in same position */
- dma_desc->cmd |= cpu_to_le16(ADMA2_END);
-}
-
-static void sdhci_adma_table_pre(struct sdhci_host *host,
- struct mmc_data *data, int sg_count)
-{
- struct scatterlist *sg;
- unsigned long flags;
- dma_addr_t addr, align_addr;
- void *desc, *align;
- char *buffer;
- int len, offset, i;
-
- /*
- * The spec does not specify endianness of descriptor table.
- * We currently guess that it is LE.
- */
-
- host->sg_count = sg_count;
-
- desc = host->adma_table;
- align = host->align_buffer;
-
- align_addr = host->align_addr;
-
- for_each_sg(data->sg, sg, host->sg_count, i) {
- addr = sg_dma_address(sg);
- len = sg_dma_len(sg);
-
- /*
- * The SDHCI specification states that ADMA addresses must
- * be 32-bit aligned. If they aren't, then we use a bounce
- * buffer for the (up to three) bytes that screw up the
- * alignment.
- */
- offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
- SDHCI_ADMA2_MASK;
- if (offset) {
- if (data->flags & MMC_DATA_WRITE) {
- buffer = sdhci_kmap_atomic(sg, &flags);
- memcpy(align, buffer, offset);
- sdhci_kunmap_atomic(buffer, &flags);
- }
-
- /* tran, valid */
- __sdhci_adma_write_desc(host, &desc, align_addr,
- offset, ADMA2_TRAN_VALID);
-
- BUG_ON(offset > 65536);
-
- align += SDHCI_ADMA2_ALIGN;
- align_addr += SDHCI_ADMA2_ALIGN;
-
- addr += offset;
- len -= offset;
- }
-
- /*
- * The block layer forces a minimum segment size of PAGE_SIZE,
- * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
- * multiple descriptors, noting that the ADMA table is sized
- * for 4KiB chunks anyway, so it will be big enough.
- */
- while (len > host->max_adma) {
- int n = 32 * 1024; /* 32KiB*/
-
- __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
- addr += n;
- len -= n;
- }
-
- /* tran, valid */
- if (len)
- __sdhci_adma_write_desc(host, &desc, addr, len,
- ADMA2_TRAN_VALID);
-
- /*
- * If this triggers then we have a calculation bug
- * somewhere. :/
- */
- WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
- }
-
- if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
- /* Mark the last descriptor as the terminating descriptor */
- if (desc != host->adma_table) {
- desc -= host->desc_sz;
- sdhci_adma_mark_end(desc);
- }
- } else {
- /* Add a terminating entry - nop, end, valid */
- __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
- }
-}
-
-static void sdhci_adma_table_post(struct sdhci_host *host,
- struct mmc_data *data)
-{
- struct scatterlist *sg;
- int i, size;
- void *align;
- char *buffer;
- unsigned long flags;
-
- if (data->flags & MMC_DATA_READ) {
- bool has_unaligned = false;
-
- /* Do a quick scan of the SG list for any unaligned mappings */
- for_each_sg(data->sg, sg, host->sg_count, i)
- if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
- has_unaligned = true;
- break;
- }
-
- if (has_unaligned) {
- dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
- data->sg_len, DMA_FROM_DEVICE);
-
- align = host->align_buffer;
-
- for_each_sg(data->sg, sg, host->sg_count, i) {
- if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
- size = SDHCI_ADMA2_ALIGN -
- (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
-
- buffer = sdhci_kmap_atomic(sg, &flags);
- memcpy(buffer, align, size);
- sdhci_kunmap_atomic(buffer, &flags);
-
- align += SDHCI_ADMA2_ALIGN;
- }
- }
- }
- }
-}
-
-static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
-{
- sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
- if (host->flags & SDHCI_USE_64_BIT_DMA)
- sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
-}
-
-static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
-{
- if (host->bounce_buffer)
- return host->bounce_addr;
- else
- return sg_dma_address(host->data->sg);
-}
-
-static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
-{
- if (host->v4_mode)
- sdhci_set_adma_addr(host, addr);
- else
- sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
-}
-
-static unsigned int sdhci_target_timeout(struct sdhci_host *host,
- struct mmc_command *cmd,
- struct mmc_data *data)
-{
- unsigned int target_timeout;
-
- /* timeout in us */
- if (!data) {
- target_timeout = cmd->busy_timeout * 1000;
- } else {
- target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
- if (host->clock && data->timeout_clks) {
- unsigned long long val;
-
- /*
- * data->timeout_clks is in units of clock cycles.
- * host->clock is in Hz. target_timeout is in us.
- * Hence, us = 1000000 * cycles / Hz. Round up.
- */
- val = 1000000ULL * data->timeout_clks;
- if (do_div(val, host->clock))
- target_timeout++;
- target_timeout += val;
- }
- }
-
- return target_timeout;
-}
-
-static void sdhci_calc_sw_timeout(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- struct mmc_data *data = cmd->data;
- struct mmc_host *mmc = host->mmc;
- struct mmc_ios *ios = &mmc->ios;
- unsigned char bus_width = 1 << ios->bus_width;
- unsigned int blksz;
- unsigned int freq;
- u64 target_timeout;
- u64 transfer_time;
-
- target_timeout = sdhci_target_timeout(host, cmd, data);
- target_timeout *= NSEC_PER_USEC;
-
- if (data) {
- blksz = data->blksz;
- freq = mmc->actual_clock ? : host->clock;
- transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
- do_div(transfer_time, freq);
- /* multiply by '2' to account for any unknowns */
- transfer_time = transfer_time * 2;
- /* calculate timeout for the entire data */
- host->data_timeout = data->blocks * target_timeout +
- transfer_time;
- } else {
- host->data_timeout = target_timeout;
- }
-
- if (host->data_timeout)
- host->data_timeout += MMC_CMD_TRANSFER_TIME;
-}
-
-static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
- bool *too_big)
-{
- u8 count;
- struct mmc_data *data;
- unsigned target_timeout, current_timeout;
-
- *too_big = false;
-
- /*
- * If the host controller provides us with an incorrect timeout
- * value, just skip the check and use the maximum. The hardware may take
- * longer to time out, but that's much better than having a too-short
- * timeout value.
- */
- if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
- return host->max_timeout_count;
-
- /* Unspecified command, assume max */
- if (cmd == NULL)
- return host->max_timeout_count;
-
- data = cmd->data;
- /* Unspecified timeout, assume max */
- if (!data && !cmd->busy_timeout)
- return host->max_timeout_count;
-
- /* timeout in us */
- target_timeout = sdhci_target_timeout(host, cmd, data);
-
- /*
- * Figure out needed cycles.
- * We do this in steps in order to fit inside a 32 bit int.
- * The first step is the minimum timeout, which will have a
- * minimum resolution of 6 bits:
- * (1) 2^13*1000 > 2^22,
- * (2) host->timeout_clk < 2^16
- * =>
- * (1) / (2) > 2^6
- */
- count = 0;
- current_timeout = (1 << 13) * 1000 / host->timeout_clk;
- while (current_timeout < target_timeout) {
- count++;
- current_timeout <<= 1;
- if (count > host->max_timeout_count) {
- if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
- DBG("Too large timeout 0x%x requested for CMD%d!\n",
- count, cmd->opcode);
- count = host->max_timeout_count;
- *too_big = true;
- break;
- }
- }
-
- return count;
-}
-
-static void sdhci_set_transfer_irqs(struct sdhci_host *host)
-{
- u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
- u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
-
- if (host->flags & SDHCI_REQ_USE_DMA)
- host->ier = (host->ier & ~pio_irqs) | dma_irqs;
- else
- host->ier = (host->ier & ~dma_irqs) | pio_irqs;
-
- if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
- host->ier |= SDHCI_INT_AUTO_CMD_ERR;
- else
- host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
-
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-}
-
-void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
-{
- if (enable)
- host->ier |= SDHCI_INT_DATA_TIMEOUT;
- else
- host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
-
-void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
-{
- bool too_big = false;
- u8 count = sdhci_calc_timeout(host, cmd, &too_big);
-
- if (too_big &&
- host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
- sdhci_calc_sw_timeout(host, cmd);
- sdhci_set_data_timeout_irq(host, false);
- } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
- sdhci_set_data_timeout_irq(host, true);
- }
-
- sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
-}
-EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
-
-static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
-{
- if (host->ops->set_timeout)
- host->ops->set_timeout(host, cmd);
- else
- __sdhci_set_timeout(host, cmd);
-}
-
-static void sdhci_initialize_data(struct sdhci_host *host,
- struct mmc_data *data)
-{
- WARN_ON(host->data);
-
- /* Sanity checks */
- BUG_ON(data->blksz * data->blocks > 524288);
- BUG_ON(data->blksz > host->mmc->max_blk_size);
- BUG_ON(data->blocks > 65535);
-
- host->data = data;
- host->data_early = 0;
- host->data->bytes_xfered = 0;
-}
-
-static inline void sdhci_set_block_info(struct sdhci_host *host,
- struct mmc_data *data)
-{
- /* Set the DMA boundary value and block size */
- sdhci_writew(host,
- SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
- SDHCI_BLOCK_SIZE);
- /*
- * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
- * can be supported, in that case 16-bit block count register must be 0.
- */
- if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
- (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
- if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
- sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
- sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
- } else {
- sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
- }
-}
-
-static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
-{
- struct mmc_data *data = cmd->data;
-
- sdhci_initialize_data(host, data);
-
- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
- struct scatterlist *sg;
- unsigned int length_mask, offset_mask;
- int i;
-
- host->flags |= SDHCI_REQ_USE_DMA;
-
- /*
- * FIXME: This doesn't account for merging when mapping the
- * scatterlist.
- *
- * The assumption here being that alignment and lengths are
- * the same after DMA mapping to device address space.
- */
- length_mask = 0;
- offset_mask = 0;
- if (host->flags & SDHCI_USE_ADMA) {
- if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
- length_mask = 3;
- /*
- * As we use up to 3 byte chunks to work
- * around alignment problems, we need to
- * check the offset as well.
- */
- offset_mask = 3;
- }
- } else {
- if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
- length_mask = 3;
- if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
- offset_mask = 3;
- }
-
- if (unlikely(length_mask | offset_mask)) {
- for_each_sg(data->sg, sg, data->sg_len, i) {
- if (sg->length & length_mask) {
- DBG("Reverting to PIO because of transfer size (%d)\n",
- sg->length);
- host->flags &= ~SDHCI_REQ_USE_DMA;
- break;
- }
- if (sg->offset & offset_mask) {
- DBG("Reverting to PIO because of bad alignment\n");
- host->flags &= ~SDHCI_REQ_USE_DMA;
- break;
- }
- }
- }
- }
-
- if (host->flags & SDHCI_REQ_USE_DMA) {
- int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
-
- if (sg_cnt <= 0) {
- /*
- * This only happens when someone fed
- * us an invalid request.
- */
- WARN_ON(1);
- host->flags &= ~SDHCI_REQ_USE_DMA;
- } else if (host->flags & SDHCI_USE_ADMA) {
- sdhci_adma_table_pre(host, data, sg_cnt);
- sdhci_set_adma_addr(host, host->adma_addr);
- } else {
- WARN_ON(sg_cnt != 1);
- sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
- }
- }
-
- sdhci_config_dma(host);
-
- if (!(host->flags & SDHCI_REQ_USE_DMA)) {
- int flags;
-
- flags = SG_MITER_ATOMIC;
- if (host->data->flags & MMC_DATA_READ)
- flags |= SG_MITER_TO_SG;
- else
- flags |= SG_MITER_FROM_SG;
- sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
- host->blocks = data->blocks;
- }
-
- sdhci_set_transfer_irqs(host);
-
- sdhci_set_block_info(host, data);
-}
-
-#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
-
-static int sdhci_external_dma_init(struct sdhci_host *host)
-{
- int ret = 0;
- struct mmc_host *mmc = host->mmc;
-
- host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
- if (IS_ERR(host->tx_chan)) {
- ret = PTR_ERR(host->tx_chan);
- if (ret != -EPROBE_DEFER)
- pr_warn("Failed to request TX DMA channel.\n");
- host->tx_chan = NULL;
- return ret;
- }
-
- host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
- if (IS_ERR(host->rx_chan)) {
- if (host->tx_chan) {
- dma_release_channel(host->tx_chan);
- host->tx_chan = NULL;
- }
-
- ret = PTR_ERR(host->rx_chan);
- if (ret != -EPROBE_DEFER)
- pr_warn("Failed to request RX DMA channel.\n");
- host->rx_chan = NULL;
- }
-
- return ret;
-}
-
-static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
- struct mmc_data *data)
-{
- return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
-}
-
-static int sdhci_external_dma_setup(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- int ret, i;
- enum dma_transfer_direction dir;
- struct dma_async_tx_descriptor *desc;
- struct mmc_data *data = cmd->data;
- struct dma_chan *chan;
- struct dma_slave_config cfg;
- dma_cookie_t cookie;
- int sg_cnt;
-
- if (!host->mapbase)
- return -EINVAL;
-
- memset(&cfg, 0, sizeof(cfg));
- cfg.src_addr = host->mapbase + SDHCI_BUFFER;
- cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
- cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- cfg.src_maxburst = data->blksz / 4;
- cfg.dst_maxburst = data->blksz / 4;
-
- /* Sanity check: all the SG entries must be aligned by block size. */
- for (i = 0; i < data->sg_len; i++) {
- if ((data->sg + i)->length % data->blksz)
- return -EINVAL;
- }
-
- chan = sdhci_external_dma_channel(host, data);
-
- ret = dmaengine_slave_config(chan, &cfg);
- if (ret)
- return ret;
-
- sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
- if (sg_cnt <= 0)
- return -EINVAL;
-
- dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
- desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
- DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
- if (!desc)
- return -EINVAL;
-
- desc->callback = NULL;
- desc->callback_param = NULL;
-
- cookie = dmaengine_submit(desc);
- if (dma_submit_error(cookie))
- ret = cookie;
-
- return ret;
-}
-
-static void sdhci_external_dma_release(struct sdhci_host *host)
-{
- if (host->tx_chan) {
- dma_release_channel(host->tx_chan);
- host->tx_chan = NULL;
- }
-
- if (host->rx_chan) {
- dma_release_channel(host->rx_chan);
- host->rx_chan = NULL;
- }
-
- sdhci_switch_external_dma(host, false);
-}
-
-static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- struct mmc_data *data = cmd->data;
-
- sdhci_initialize_data(host, data);
-
- host->flags |= SDHCI_REQ_USE_DMA;
- sdhci_set_transfer_irqs(host);
-
- sdhci_set_block_info(host, data);
-}
-
-static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- if (!sdhci_external_dma_setup(host, cmd)) {
- __sdhci_external_dma_prepare_data(host, cmd);
- } else {
- sdhci_external_dma_release(host);
- pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
- mmc_hostname(host->mmc));
- sdhci_prepare_data(host, cmd);
- }
-}
-
-static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- struct dma_chan *chan;
-
- if (!cmd->data)
- return;
-
- chan = sdhci_external_dma_channel(host, cmd->data);
- if (chan)
- dma_async_issue_pending(chan);
-}
-
-#else
-
-static inline int sdhci_external_dma_init(struct sdhci_host *host)
-{
- return -EOPNOTSUPP;
-}
-
-static inline void sdhci_external_dma_release(struct sdhci_host *host)
-{
-}
-
-static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- /* This should never happen */
- WARN_ON_ONCE(1);
-}
-
-static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
-}
-
-static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
- struct mmc_data *data)
-{
- return NULL;
-}
-
-#endif
-
-void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
-{
- host->use_external_dma = en;
-}
-EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
-
-static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
- struct mmc_request *mrq)
-{
- return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
- !mrq->cap_cmd_during_tfr;
-}
-
-static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
- struct mmc_request *mrq)
-{
- return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
-}
-
-static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
- struct mmc_request *mrq)
-{
- return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
-}
-
-static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
- struct mmc_command *cmd,
- u16 *mode)
-{
- bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
- (cmd->opcode != SD_IO_RW_EXTENDED);
- bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
- u16 ctrl2;
-
- /*
- * In case of Version 4.10 or later, use of 'Auto CMD Auto
- * Select' is recommended rather than use of 'Auto CMD12
- * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
- * here because some controllers (e.g sdhci-of-dwmshc) expect it.
- */
- if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
- (use_cmd12 || use_cmd23)) {
- *mode |= SDHCI_TRNS_AUTO_SEL;
-
- ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- if (use_cmd23)
- ctrl2 |= SDHCI_CMD23_ENABLE;
- else
- ctrl2 &= ~SDHCI_CMD23_ENABLE;
- sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
-
- return;
- }
-
- /*
- * If we are sending CMD23, CMD12 never gets sent
- * on successful completion (so no Auto-CMD12).
- */
- if (use_cmd12)
- *mode |= SDHCI_TRNS_AUTO_CMD12;
- else if (use_cmd23)
- *mode |= SDHCI_TRNS_AUTO_CMD23;
-}
-
-static void sdhci_set_transfer_mode(struct sdhci_host *host,
- struct mmc_command *cmd)
-{
- u16 mode = 0;
- struct mmc_data *data = cmd->data;
-
- if (data == NULL) {
- if (host->quirks2 &
- SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
- /* must not clear SDHCI_TRANSFER_MODE when tuning */
- if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
- sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
- } else {
- /* clear Auto CMD settings for no data CMDs */
- mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
- sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
- SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
- }
- return;
- }
-
- WARN_ON(!host->data);
-
- if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
- mode = SDHCI_TRNS_BLK_CNT_EN;
-
- if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
- mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
- sdhci_auto_cmd_select(host, cmd, &mode);
- if (sdhci_auto_cmd23(host, cmd->mrq))
- sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
- }
-
- if (data->flags & MMC_DATA_READ)
- mode |= SDHCI_TRNS_READ;
- if (host->flags & SDHCI_REQ_USE_DMA)
- mode |= SDHCI_TRNS_DMA;
-
- sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
-}
-
-static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
-{
- return (!(host->flags & SDHCI_DEVICE_DEAD) &&
- ((mrq->cmd && mrq->cmd->error) ||
- (mrq->sbc && mrq->sbc->error) ||
- (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
- (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
-}
-
-static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
-{
- int i;
-
- for (i = 0; i < SDHCI_MAX_MRQS; i++) {
- if (host->mrqs_done[i] == mrq) {
- WARN_ON(1);
- return;
- }
- }
-
- for (i = 0; i < SDHCI_MAX_MRQS; i++) {
- if (!host->mrqs_done[i]) {
- host->mrqs_done[i] = mrq;
- break;
- }
- }
-
- WARN_ON(i >= SDHCI_MAX_MRQS);
-}
-
-static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
-{
- if (host->cmd && host->cmd->mrq == mrq)
- host->cmd = NULL;
-
- if (host->data_cmd && host->data_cmd->mrq == mrq)
- host->data_cmd = NULL;
-
- if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
- host->deferred_cmd = NULL;
-
- if (host->data && host->data->mrq == mrq)
- host->data = NULL;
-
- if (sdhci_needs_reset(host, mrq))
- host->pending_reset = true;
-
- sdhci_set_mrq_done(host, mrq);
-
- sdhci_del_timer(host, mrq);
-
- if (!sdhci_has_requests(host))
- sdhci_led_deactivate(host);
-}
-
-static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
-{
- __sdhci_finish_mrq(host, mrq);
-
- queue_work(host->complete_wq, &host->complete_work);
-}
-
-static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
-{
- struct mmc_command *data_cmd = host->data_cmd;
- struct mmc_data *data = host->data;
-
- host->data = NULL;
- host->data_cmd = NULL;
-
- /*
- * The controller needs a reset of internal state machines upon error
- * conditions.
- */
- if (data->error) {
- if (!host->cmd || host->cmd == data_cmd)
- sdhci_reset_for(host, REQUEST_ERROR);
- else
- sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
- }
-
- if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
- (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
- sdhci_adma_table_post(host, data);
-
- /*
- * The specification states that the block count register must
- * be updated, but it does not specify at what point in the
- * data flow. That makes the register entirely useless to read
- * back so we have to assume that nothing made it to the card
- * in the event of an error.
- */
- if (data->error)
- data->bytes_xfered = 0;
- else
- data->bytes_xfered = data->blksz * data->blocks;
-
- /*
- * Need to send CMD12 if -
- * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
- * b) error in multiblock transfer
- */
- if (data->stop &&
- ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
- data->error)) {
- /*
- * 'cap_cmd_during_tfr' request must not use the command line
- * after mmc_command_done() has been called. It is upper layer's
- * responsibility to send the stop command if required.
- */
- if (data->mrq->cap_cmd_during_tfr) {
- __sdhci_finish_mrq(host, data->mrq);
- } else {
- /* Avoid triggering warning in sdhci_send_command() */
- host->cmd = NULL;
- if (!sdhci_send_command(host, data->stop)) {
- if (sw_data_timeout) {
- /*
- * This is anyway a sw data timeout, so
- * give up now.
- */
- data->stop->error = -EIO;
- __sdhci_finish_mrq(host, data->mrq);
- } else {
- WARN_ON(host->deferred_cmd);
- host->deferred_cmd = data->stop;
- }
- }
- }
- } else {
- __sdhci_finish_mrq(host, data->mrq);
- }
-}
-
-static void sdhci_finish_data(struct sdhci_host *host)
-{
- __sdhci_finish_data(host, false);
-}
-
-static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
-{
- int flags;
- u32 mask;
- unsigned long timeout;
-
- WARN_ON(host->cmd);
-
- /* Initially, a command has no error */
- cmd->error = 0;
-
- if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
- cmd->opcode == MMC_STOP_TRANSMISSION)
- cmd->flags |= MMC_RSP_BUSY;
-
- mask = SDHCI_CMD_INHIBIT;
- if (sdhci_data_line_cmd(cmd))
- mask |= SDHCI_DATA_INHIBIT;
-
- /* We shouldn't wait for data inihibit for stop commands, even
- though they might use busy signaling */
- if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
- mask &= ~SDHCI_DATA_INHIBIT;
-
- if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
- return false;
-
- host->cmd = cmd;
- host->data_timeout = 0;
- if (sdhci_data_line_cmd(cmd)) {
- WARN_ON(host->data_cmd);
- host->data_cmd = cmd;
- sdhci_set_timeout(host, cmd);
- }
-
- if (cmd->data) {
- if (host->use_external_dma)
- sdhci_external_dma_prepare_data(host, cmd);
- else
- sdhci_prepare_data(host, cmd);
- }
-
- sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
-
- sdhci_set_transfer_mode(host, cmd);
-
- if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
- WARN_ONCE(1, "Unsupported response type!\n");
- /*
- * This does not happen in practice because 136-bit response
- * commands never have busy waiting, so rather than complicate
- * the error path, just remove busy waiting and continue.
- */
- cmd->flags &= ~MMC_RSP_BUSY;
- }
-
- if (!(cmd->flags & MMC_RSP_PRESENT))
- flags = SDHCI_CMD_RESP_NONE;
- else if (cmd->flags & MMC_RSP_136)
- flags = SDHCI_CMD_RESP_LONG;
- else if (cmd->flags & MMC_RSP_BUSY)
- flags = SDHCI_CMD_RESP_SHORT_BUSY;
- else
- flags = SDHCI_CMD_RESP_SHORT;
-
- if (cmd->flags & MMC_RSP_CRC)
- flags |= SDHCI_CMD_CRC;
- if (cmd->flags & MMC_RSP_OPCODE)
- flags |= SDHCI_CMD_INDEX;
-
- /* CMD19 is special in that the Data Present Select should be set */
- if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
- flags |= SDHCI_CMD_DATA;
-
- timeout = jiffies;
- if (host->data_timeout)
- timeout += nsecs_to_jiffies(host->data_timeout);
- else if (!cmd->data && cmd->busy_timeout > 9000)
- timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
- else
- timeout += 10 * HZ;
- sdhci_mod_timer(host, cmd->mrq, timeout);
-
- if (host->use_external_dma)
- sdhci_external_dma_pre_transfer(host, cmd);
-
- sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
-
- return true;
-}
-
-static bool sdhci_present_error(struct sdhci_host *host,
- struct mmc_command *cmd, bool present)
-{
- if (!present || host->flags & SDHCI_DEVICE_DEAD) {
- cmd->error = -ENOMEDIUM;
- return true;
- }
-
- return false;
-}
-
-static bool sdhci_send_command_retry(struct sdhci_host *host,
- struct mmc_command *cmd,
- unsigned long flags)
- __releases(host->lock)
- __acquires(host->lock)
-{
- struct mmc_command *deferred_cmd = host->deferred_cmd;
- int timeout = 10; /* Approx. 10 ms */
- bool present;
-
- while (!sdhci_send_command(host, cmd)) {
- if (!timeout--) {
- pr_err("%s: Controller never released inhibit bit(s).\n",
- mmc_hostname(host->mmc));
- sdhci_err_stats_inc(host, CTRL_TIMEOUT);
- sdhci_dumpregs(host);
- cmd->error = -EIO;
- return false;
- }
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- usleep_range(1000, 1250);
-
- present = host->mmc->ops->get_cd(host->mmc);
-
- spin_lock_irqsave(&host->lock, flags);
-
- /* A deferred command might disappear, handle that */
- if (cmd == deferred_cmd && cmd != host->deferred_cmd)
- return true;
-
- if (sdhci_present_error(host, cmd, present))
- return false;
- }
-
- if (cmd == host->deferred_cmd)
- host->deferred_cmd = NULL;
-
- return true;
-}
-
-static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
-{
- int i, reg;
-
- for (i = 0; i < 4; i++) {
- reg = SDHCI_RESPONSE + (3 - i) * 4;
- cmd->resp[i] = sdhci_readl(host, reg);
- }
-
- if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
- return;
-
- /* CRC is stripped so we need to do some shifting */
- for (i = 0; i < 4; i++) {
- cmd->resp[i] <<= 8;
- if (i != 3)
- cmd->resp[i] |= cmd->resp[i + 1] >> 24;
- }
-}
-
-static void sdhci_finish_command(struct sdhci_host *host)
-{
- struct mmc_command *cmd = host->cmd;
-
- host->cmd = NULL;
-
- if (cmd->flags & MMC_RSP_PRESENT) {
- if (cmd->flags & MMC_RSP_136) {
- sdhci_read_rsp_136(host, cmd);
- } else {
- cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
- }
- }
-
- if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
- mmc_command_done(host->mmc, cmd->mrq);
-
- /*
- * The host can send and interrupt when the busy state has
- * ended, allowing us to wait without wasting CPU cycles.
- * The busy signal uses DAT0 so this is similar to waiting
- * for data to complete.
- *
- * Note: The 1.0 specification is a bit ambiguous about this
- * feature so there might be some problems with older
- * controllers.
- */
- if (cmd->flags & MMC_RSP_BUSY) {
- if (cmd->data) {
- DBG("Cannot wait for busy signal when also doing a data transfer");
- } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
- cmd == host->data_cmd) {
- /* Command complete before busy is ended */
- return;
- }
- }
-
- /* Finished CMD23, now send actual command. */
- if (cmd == cmd->mrq->sbc) {
- if (!sdhci_send_command(host, cmd->mrq->cmd)) {
- WARN_ON(host->deferred_cmd);
- host->deferred_cmd = cmd->mrq->cmd;
- }
- } else {
-
- /* Processed actual command. */
- if (host->data && host->data_early)
- sdhci_finish_data(host);
-
- if (!cmd->data)
- __sdhci_finish_mrq(host, cmd->mrq);
- }
-}
-
-static u16 sdhci_get_preset_value(struct sdhci_host *host)
-{
- u16 preset = 0;
-
- switch (host->timing) {
- case MMC_TIMING_MMC_HS:
- case MMC_TIMING_SD_HS:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
- break;
- case MMC_TIMING_UHS_SDR12:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
- break;
- case MMC_TIMING_UHS_SDR25:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
- break;
- case MMC_TIMING_UHS_SDR50:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
- break;
- case MMC_TIMING_UHS_SDR104:
- case MMC_TIMING_MMC_HS200:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
- break;
- case MMC_TIMING_UHS_DDR50:
- case MMC_TIMING_MMC_DDR52:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
- break;
- case MMC_TIMING_MMC_HS400:
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
- break;
- default:
- pr_warn("%s: Invalid UHS-I mode selected\n",
- mmc_hostname(host->mmc));
- preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
- break;
- }
- return preset;
-}
-
-u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
- unsigned int *actual_clock)
-{
- int div = 0; /* Initialized for compiler warning */
- int real_div = div, clk_mul = 1;
- u16 clk = 0;
- bool switch_base_clk = false;
-
- if (host->version >= SDHCI_SPEC_300) {
- if (host->preset_enabled) {
- u16 pre_val;
-
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- pre_val = sdhci_get_preset_value(host);
- div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
- if (host->clk_mul &&
- (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
- clk = SDHCI_PROG_CLOCK_MODE;
- real_div = div + 1;
- clk_mul = host->clk_mul;
- } else {
- real_div = max_t(int, 1, div << 1);
- }
- goto clock_set;
- }
-
- /*
- * Check if the Host Controller supports Programmable Clock
- * Mode.
- */
- if (host->clk_mul) {
- for (div = 1; div <= 1024; div++) {
- if ((host->max_clk * host->clk_mul / div)
- <= clock)
- break;
- }
- if ((host->max_clk * host->clk_mul / div) <= clock) {
- /*
- * Set Programmable Clock Mode in the Clock
- * Control register.
- */
- clk = SDHCI_PROG_CLOCK_MODE;
- real_div = div;
- clk_mul = host->clk_mul;
- div--;
- } else {
- /*
- * Divisor can be too small to reach clock
- * speed requirement. Then use the base clock.
- */
- switch_base_clk = true;
- }
- }
-
- if (!host->clk_mul || switch_base_clk) {
- /* Version 3.00 divisors must be a multiple of 2. */
- if (host->max_clk <= clock)
- div = 1;
- else {
- for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
- div += 2) {
- if ((host->max_clk / div) <= clock)
- break;
- }
- }
- real_div = div;
- div >>= 1;
- if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
- && !div && host->max_clk <= 25000000)
- div = 1;
- }
- } else {
- /* Version 2.00 divisors must be a power of 2. */
- for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
- if ((host->max_clk / div) <= clock)
- break;
- }
- real_div = div;
- div >>= 1;
- }
-
-clock_set:
- if (real_div)
- *actual_clock = (host->max_clk * clk_mul) / real_div;
- clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
- clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
- << SDHCI_DIVIDER_HI_SHIFT;
-
- return clk;
-}
-EXPORT_SYMBOL_GPL(sdhci_calc_clk);
-
-void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
-{
- ktime_t timeout;
-
- clk |= SDHCI_CLOCK_INT_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-
- /* Wait max 150 ms */
- timeout = ktime_add_ms(ktime_get(), 150);
- while (1) {
- bool timedout = ktime_after(ktime_get(), timeout);
-
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- if (clk & SDHCI_CLOCK_INT_STABLE)
- break;
- if (timedout) {
- pr_err("%s: Internal clock never stabilised.\n",
- mmc_hostname(host->mmc));
- sdhci_err_stats_inc(host, CTRL_TIMEOUT);
- sdhci_dumpregs(host);
- return;
- }
- udelay(10);
- }
-
- if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
- clk |= SDHCI_CLOCK_PLL_EN;
- clk &= ~SDHCI_CLOCK_INT_STABLE;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-
- /* Wait max 150 ms */
- timeout = ktime_add_ms(ktime_get(), 150);
- while (1) {
- bool timedout = ktime_after(ktime_get(), timeout);
-
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- if (clk & SDHCI_CLOCK_INT_STABLE)
- break;
- if (timedout) {
- pr_err("%s: PLL clock never stabilised.\n",
- mmc_hostname(host->mmc));
- sdhci_err_stats_inc(host, CTRL_TIMEOUT);
- sdhci_dumpregs(host);
- return;
- }
- udelay(10);
- }
- }
-
- clk |= SDHCI_CLOCK_CARD_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-}
-EXPORT_SYMBOL_GPL(sdhci_enable_clk);
-
-void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
-{
- u16 clk;
-
- host->mmc->actual_clock = 0;
-
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-
- if (clock == 0)
- return;
-
- clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
- sdhci_enable_clk(host, clk);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_clock);
-
-static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
- unsigned short vdd)
-{
- struct mmc_host *mmc = host->mmc;
-
- mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
-
- if (mode != MMC_POWER_OFF)
- sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
- else
- sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
-}
-
-void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
- unsigned short vdd)
-{
- u8 pwr = 0;
-
- if (mode != MMC_POWER_OFF) {
- switch (1 << vdd) {
- case MMC_VDD_165_195:
- /*
- * Without a regulator, SDHCI does not support 2.0v
- * so we only get here if the driver deliberately
- * added the 2.0v range to ocr_avail. Map it to 1.8v
- * for the purpose of turning on the power.
- */
- case MMC_VDD_20_21:
- pwr = SDHCI_POWER_180;
- break;
- case MMC_VDD_29_30:
- case MMC_VDD_30_31:
- pwr = SDHCI_POWER_300;
- break;
- case MMC_VDD_32_33:
- case MMC_VDD_33_34:
- /*
- * 3.4 ~ 3.6V are valid only for those platforms where it's
- * known that the voltage range is supported by hardware.
- */
- case MMC_VDD_34_35:
- case MMC_VDD_35_36:
- pwr = SDHCI_POWER_330;
- break;
- default:
- WARN(1, "%s: Invalid vdd %#x\n",
- mmc_hostname(host->mmc), vdd);
- break;
- }
- }
-
- if (host->pwr == pwr)
- return;
-
- host->pwr = pwr;
-
- if (pwr == 0) {
- sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
- if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
- sdhci_runtime_pm_bus_off(host);
- } else {
- /*
- * Spec says that we should clear the power reg before setting
- * a new value. Some controllers don't seem to like this though.
- */
- if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
- sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
-
- /*
- * At least the Marvell CaFe chip gets confused if we set the
- * voltage and set turn on power at the same time, so set the
- * voltage first.
- */
- if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
- sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
-
- pwr |= SDHCI_POWER_ON;
-
- sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
-
- if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
- sdhci_runtime_pm_bus_on(host);
-
- /*
- * Some controllers need an extra 10ms delay of 10ms before
- * they can apply clock after applying power
- */
- if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
- mdelay(10);
- }
-}
-EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
-
-void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
- unsigned short vdd)
-{
- if (IS_ERR(host->mmc->supply.vmmc))
- sdhci_set_power_noreg(host, mode, vdd);
- else
- sdhci_set_power_reg(host, mode, vdd);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_power);
-
-/*
- * Some controllers need to configure a valid bus voltage on their power
- * register regardless of whether an external regulator is taking care of power
- * supply. This helper function takes care of it if set as the controller's
- * sdhci_ops.set_power callback.
- */
-void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
- unsigned char mode,
- unsigned short vdd)
-{
- if (!IS_ERR(host->mmc->supply.vmmc)) {
- struct mmc_host *mmc = host->mmc;
-
- mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
- }
- sdhci_set_power_noreg(host, mode, vdd);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
-
-/*****************************************************************************\
- * *
- * MMC callbacks *
- * *
-\*****************************************************************************/
-
-void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- struct mmc_command *cmd;
- unsigned long flags;
- bool present;
-
- /* Firstly check card presence */
- present = mmc->ops->get_cd(mmc);
-
- spin_lock_irqsave(&host->lock, flags);
-
- sdhci_led_activate(host);
-
- if (sdhci_present_error(host, mrq->cmd, present))
- goto out_finish;
-
- cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
-
- if (!sdhci_send_command_retry(host, cmd, flags))
- goto out_finish;
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- return;
-
-out_finish:
- sdhci_finish_mrq(host, mrq);
- spin_unlock_irqrestore(&host->lock, flags);
-}
-EXPORT_SYMBOL_GPL(sdhci_request);
-
-int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- struct mmc_command *cmd;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&host->lock, flags);
-
- if (sdhci_present_error(host, mrq->cmd, true)) {
- sdhci_finish_mrq(host, mrq);
- goto out_finish;
- }
-
- cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
-
- /*
- * The HSQ may send a command in interrupt context without polling
- * the busy signaling, which means we should return BUSY if controller
- * has not released inhibit bits to allow HSQ trying to send request
- * again in non-atomic context. So we should not finish this request
- * here.
- */
- if (!sdhci_send_command(host, cmd))
- ret = -EBUSY;
- else
- sdhci_led_activate(host);
-
-out_finish:
- spin_unlock_irqrestore(&host->lock, flags);
- return ret;
-}
-EXPORT_SYMBOL_GPL(sdhci_request_atomic);
-
-void sdhci_set_bus_width(struct sdhci_host *host, int width)
-{
- u8 ctrl;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- if (width == MMC_BUS_WIDTH_8) {
- ctrl &= ~SDHCI_CTRL_4BITBUS;
- ctrl |= SDHCI_CTRL_8BITBUS;
- } else {
- if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
- ctrl &= ~SDHCI_CTRL_8BITBUS;
- if (width == MMC_BUS_WIDTH_4)
- ctrl |= SDHCI_CTRL_4BITBUS;
- else
- ctrl &= ~SDHCI_CTRL_4BITBUS;
- }
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
-
-void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
-{
- u16 ctrl_2;
-
- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- /* Select Bus Speed Mode for host */
- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
- if ((timing == MMC_TIMING_MMC_HS200) ||
- (timing == MMC_TIMING_UHS_SDR104))
- ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
- else if (timing == MMC_TIMING_UHS_SDR12)
- ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
- else if (timing == MMC_TIMING_UHS_SDR25)
- ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
- else if (timing == MMC_TIMING_UHS_SDR50)
- ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
- else if ((timing == MMC_TIMING_UHS_DDR50) ||
- (timing == MMC_TIMING_MMC_DDR52))
- ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
- else if (timing == MMC_TIMING_MMC_HS400)
- ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
- sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
-
-static bool sdhci_timing_has_preset(unsigned char timing)
-{
- switch (timing) {
- case MMC_TIMING_UHS_SDR12:
- case MMC_TIMING_UHS_SDR25:
- case MMC_TIMING_UHS_SDR50:
- case MMC_TIMING_UHS_SDR104:
- case MMC_TIMING_UHS_DDR50:
- case MMC_TIMING_MMC_DDR52:
- return true;
- };
- return false;
-}
-
-static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
-{
- return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
- sdhci_timing_has_preset(timing);
-}
-
-static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
-{
- /*
- * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
- * Frequency. Check if preset values need to be enabled, or the Driver
- * Strength needs updating. Note, clock changes are handled separately.
- */
- return !host->preset_enabled &&
- (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
-}
-
-void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- bool reinit_uhs = host->reinit_uhs;
- bool turning_on_clk = false;
- u8 ctrl;
-
- host->reinit_uhs = false;
-
- if (ios->power_mode == MMC_POWER_UNDEFINED)
- return;
-
- if (host->flags & SDHCI_DEVICE_DEAD) {
- if (!IS_ERR(mmc->supply.vmmc) &&
- ios->power_mode == MMC_POWER_OFF)
- mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
- return;
- }
-
- /*
- * Reset the chip on each power off.
- * Should clear out any weird states.
- */
- if (ios->power_mode == MMC_POWER_OFF) {
- sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
- sdhci_reinit(host);
- }
-
- if (host->version >= SDHCI_SPEC_300 &&
- (ios->power_mode == MMC_POWER_UP) &&
- !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
- sdhci_enable_preset_value(host, false);
-
- if (!ios->clock || ios->clock != host->clock) {
- turning_on_clk = ios->clock && !host->clock;
-
- host->ops->set_clock(host, ios->clock);
- host->clock = ios->clock;
-
- if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
- host->clock) {
- host->timeout_clk = mmc->actual_clock ?
- mmc->actual_clock / 1000 :
- host->clock / 1000;
- mmc->max_busy_timeout =
- host->ops->get_max_timeout_count ?
- host->ops->get_max_timeout_count(host) :
- 1 << 27;
- mmc->max_busy_timeout /= host->timeout_clk;
- }
- }
-
- if (host->ops->set_power)
- host->ops->set_power(host, ios->power_mode, ios->vdd);
- else
- sdhci_set_power(host, ios->power_mode, ios->vdd);
-
- if (host->ops->platform_send_init_74_clocks)
- host->ops->platform_send_init_74_clocks(host, ios->power_mode);
-
- host->ops->set_bus_width(host, ios->bus_width);
-
- /*
- * Special case to avoid multiple clock changes during voltage
- * switching.
- */
- if (!reinit_uhs &&
- turning_on_clk &&
- host->timing == ios->timing &&
- host->version >= SDHCI_SPEC_300 &&
- !sdhci_presetable_values_change(host, ios))
- return;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
-
- if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
- if (ios->timing == MMC_TIMING_SD_HS ||
- ios->timing == MMC_TIMING_MMC_HS ||
- ios->timing == MMC_TIMING_MMC_HS400 ||
- ios->timing == MMC_TIMING_MMC_HS200 ||
- ios->timing == MMC_TIMING_MMC_DDR52 ||
- ios->timing == MMC_TIMING_UHS_SDR50 ||
- ios->timing == MMC_TIMING_UHS_SDR104 ||
- ios->timing == MMC_TIMING_UHS_DDR50 ||
- ios->timing == MMC_TIMING_UHS_SDR25)
- ctrl |= SDHCI_CTRL_HISPD;
- else
- ctrl &= ~SDHCI_CTRL_HISPD;
- }
-
- if (host->version >= SDHCI_SPEC_300) {
- u16 clk, ctrl_2;
-
- if (!host->preset_enabled) {
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
- /*
- * We only need to set Driver Strength if the
- * preset value enable is not set.
- */
- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
- if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
- ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
- else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
- ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
- else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
- ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
- else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
- ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
- else {
- pr_warn("%s: invalid driver type, default to driver type B\n",
- mmc_hostname(mmc));
- ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
- }
-
- sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
- host->drv_type = ios->drv_type;
- } else {
- /*
- * According to SDHC Spec v3.00, if the Preset Value
- * Enable in the Host Control 2 register is set, we
- * need to reset SD Clock Enable before changing High
- * Speed Enable to avoid generating clock gliches.
- */
-
- /* Reset SD Clock Enable */
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- clk &= ~SDHCI_CLOCK_CARD_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-
- /* Re-enable SD Clock */
- host->ops->set_clock(host, host->clock);
- }
-
- /* Reset SD Clock Enable */
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- clk &= ~SDHCI_CLOCK_CARD_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-
- host->ops->set_uhs_signaling(host, ios->timing);
- host->timing = ios->timing;
-
- if (sdhci_preset_needed(host, ios->timing)) {
- u16 preset;
-
- sdhci_enable_preset_value(host, true);
- preset = sdhci_get_preset_value(host);
- ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
- preset);
- host->drv_type = ios->drv_type;
- }
-
- /* Re-enable SD Clock */
- host->ops->set_clock(host, host->clock);
- } else
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-EXPORT_SYMBOL_GPL(sdhci_set_ios);
-
-static int sdhci_get_cd(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- int gpio_cd = mmc_gpio_get_cd(mmc);
-
- if (host->flags & SDHCI_DEVICE_DEAD)
- return 0;
-
- /* If nonremovable, assume that the card is always present. */
- if (!mmc_card_is_removable(mmc))
- return 1;
-
- /*
- * Try slot gpio detect, if defined it take precedence
- * over build in controller functionality
- */
- if (gpio_cd >= 0)
- return !!gpio_cd;
-
- /* If polling, assume that the card is always present. */
- if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
- return 1;
-
- /* Host native card detect */
- return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
-}
-
-int sdhci_get_cd_nogpio(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&host->lock, flags);
-
- if (host->flags & SDHCI_DEVICE_DEAD)
- goto out;
-
- ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
-out:
- spin_unlock_irqrestore(&host->lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
-
-static int sdhci_check_ro(struct sdhci_host *host)
-{
- unsigned long flags;
- int is_readonly;
-
- spin_lock_irqsave(&host->lock, flags);
-
- if (host->flags & SDHCI_DEVICE_DEAD)
- is_readonly = 0;
- else if (host->ops->get_ro)
- is_readonly = host->ops->get_ro(host);
- else if (mmc_can_gpio_ro(host->mmc))
- is_readonly = mmc_gpio_get_ro(host->mmc);
- else
- is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
- & SDHCI_WRITE_PROTECT);
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- /* This quirk needs to be replaced by a callback-function later */
- return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
- !is_readonly : is_readonly;
-}
-
-#define SAMPLE_COUNT 5
-
-static int sdhci_get_ro(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- int i, ro_count;
-
- if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
- return sdhci_check_ro(host);
-
- ro_count = 0;
- for (i = 0; i < SAMPLE_COUNT; i++) {
- if (sdhci_check_ro(host)) {
- if (++ro_count > SAMPLE_COUNT / 2)
- return 1;
- }
- msleep(30);
- }
- return 0;
-}
-
-static void sdhci_hw_reset(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
-
- if (host->ops && host->ops->hw_reset)
- host->ops->hw_reset(host);
-}
-
-static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
-{
- if (!(host->flags & SDHCI_DEVICE_DEAD)) {
- if (enable)
- host->ier |= SDHCI_INT_CARD_INT;
- else
- host->ier &= ~SDHCI_INT_CARD_INT;
-
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
- }
-}
-
-void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
-
- if (enable)
- pm_runtime_get_noresume(mmc_dev(mmc));
-
- spin_lock_irqsave(&host->lock, flags);
- sdhci_enable_sdio_irq_nolock(host, enable);
- spin_unlock_irqrestore(&host->lock, flags);
-
- if (!enable)
- pm_runtime_put_noidle(mmc_dev(mmc));
-}
-EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
-
-static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
-
- spin_lock_irqsave(&host->lock, flags);
- sdhci_enable_sdio_irq_nolock(host, true);
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
- struct mmc_ios *ios)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- u16 ctrl;
- int ret;
-
- /*
- * Signal Voltage Switching is only applicable for Host Controllers
- * v3.00 and above.
- */
- if (host->version < SDHCI_SPEC_300)
- return 0;
-
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-
- switch (ios->signal_voltage) {
- case MMC_SIGNAL_VOLTAGE_330:
- if (!(host->flags & SDHCI_SIGNALING_330))
- return -EINVAL;
- /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
- ctrl &= ~SDHCI_CTRL_VDD_180;
- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
-
- if (!IS_ERR(mmc->supply.vqmmc)) {
- ret = mmc_regulator_set_vqmmc(mmc, ios);
- if (ret < 0) {
- pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
- mmc_hostname(mmc));
- return -EIO;
- }
- }
- /* Wait for 5ms */
- usleep_range(5000, 5500);
-
- /* 3.3V regulator output should be stable within 5 ms */
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- if (!(ctrl & SDHCI_CTRL_VDD_180))
- return 0;
-
- pr_warn("%s: 3.3V regulator output did not become stable\n",
- mmc_hostname(mmc));
-
- return -EAGAIN;
- case MMC_SIGNAL_VOLTAGE_180:
- if (!(host->flags & SDHCI_SIGNALING_180))
- return -EINVAL;
- if (!IS_ERR(mmc->supply.vqmmc)) {
- ret = mmc_regulator_set_vqmmc(mmc, ios);
- if (ret < 0) {
- pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
- mmc_hostname(mmc));
- return -EIO;
- }
- }
-
- /*
- * Enable 1.8V Signal Enable in the Host Control2
- * register
- */
- ctrl |= SDHCI_CTRL_VDD_180;
- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
-
- /* Some controller need to do more when switching */
- if (host->ops->voltage_switch)
- host->ops->voltage_switch(host);
-
- /* 1.8V regulator output should be stable within 5 ms */
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- if (ctrl & SDHCI_CTRL_VDD_180)
- return 0;
-
- pr_warn("%s: 1.8V regulator output did not become stable\n",
- mmc_hostname(mmc));
-
- return -EAGAIN;
- case MMC_SIGNAL_VOLTAGE_120:
- if (!(host->flags & SDHCI_SIGNALING_120))
- return -EINVAL;
- if (!IS_ERR(mmc->supply.vqmmc)) {
- ret = mmc_regulator_set_vqmmc(mmc, ios);
- if (ret < 0) {
- pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
- mmc_hostname(mmc));
- return -EIO;
- }
- }
- return 0;
- default:
- /* No signal voltage switch required */
- return 0;
- }
-}
-EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
-
-static int sdhci_card_busy(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- u32 present_state;
-
- /* Check whether DAT[0] is 0 */
- present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
-
- return !(present_state & SDHCI_DATA_0_LVL_MASK);
-}
-
-static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
-
- spin_lock_irqsave(&host->lock, flags);
- host->flags |= SDHCI_HS400_TUNING;
- spin_unlock_irqrestore(&host->lock, flags);
-
- return 0;
-}
-
-void sdhci_start_tuning(struct sdhci_host *host)
-{
- u16 ctrl;
-
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- ctrl |= SDHCI_CTRL_EXEC_TUNING;
- if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
- ctrl |= SDHCI_CTRL_TUNED_CLK;
- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
-
- /*
- * As per the Host Controller spec v3.00, tuning command
- * generates Buffer Read Ready interrupt, so enable that.
- *
- * Note: The spec clearly says that when tuning sequence
- * is being performed, the controller does not generate
- * interrupts other than Buffer Read Ready interrupt. But
- * to make sure we don't hit a controller bug, we _only_
- * enable Buffer Read Ready interrupt here.
- */
- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
-}
-EXPORT_SYMBOL_GPL(sdhci_start_tuning);
-
-void sdhci_end_tuning(struct sdhci_host *host)
-{
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-}
-EXPORT_SYMBOL_GPL(sdhci_end_tuning);
-
-void sdhci_reset_tuning(struct sdhci_host *host)
-{
- u16 ctrl;
-
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- ctrl &= ~SDHCI_CTRL_TUNED_CLK;
- ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
-}
-EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
-
-void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
-{
- sdhci_reset_tuning(host);
-
- sdhci_reset_for(host, TUNING_ABORT);
-
- sdhci_end_tuning(host);
-
- mmc_send_abort_tuning(host->mmc, opcode);
-}
-EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
-
-/*
- * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
- * tuning command does not have a data payload (or rather the hardware does it
- * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
- * interrupt setup is different to other commands and there is no timeout
- * interrupt so special handling is needed.
- */
-void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
-{
- struct mmc_host *mmc = host->mmc;
- struct mmc_command cmd = {};
- struct mmc_request mrq = {};
- unsigned long flags;
- u32 b = host->sdma_boundary;
-
- spin_lock_irqsave(&host->lock, flags);
-
- cmd.opcode = opcode;
- cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
- cmd.mrq = &mrq;
-
- mrq.cmd = &cmd;
- /*
- * In response to CMD19, the card sends 64 bytes of tuning
- * block to the Host Controller. So we set the block size
- * to 64 here.
- */
- if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
- mmc->ios.bus_width == MMC_BUS_WIDTH_8)
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
- else
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
-
- /*
- * The tuning block is sent by the card to the host controller.
- * So we set the TRNS_READ bit in the Transfer Mode register.
- * This also takes care of setting DMA Enable and Multi Block
- * Select in the same register to 0.
- */
- sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
-
- if (!sdhci_send_command_retry(host, &cmd, flags)) {
- spin_unlock_irqrestore(&host->lock, flags);
- host->tuning_done = 0;
- return;
- }
-
- host->cmd = NULL;
-
- sdhci_del_timer(host, &mrq);
-
- host->tuning_done = 0;
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- /* Wait for Buffer Read Ready interrupt */
- wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
- msecs_to_jiffies(50));
-
-}
-EXPORT_SYMBOL_GPL(sdhci_send_tuning);
-
-static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
-{
- int i;
-
- /*
- * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
- * of loops reaches tuning loop count.
- */
- for (i = 0; i < host->tuning_loop_count; i++) {
- u16 ctrl;
-
- sdhci_send_tuning(host, opcode);
-
- if (!host->tuning_done) {
- pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
- mmc_hostname(host->mmc));
- sdhci_abort_tuning(host, opcode);
- return -ETIMEDOUT;
- }
-
- /* Spec does not require a delay between tuning cycles */
- if (host->tuning_delay > 0)
- mdelay(host->tuning_delay);
-
- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
- if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
- if (ctrl & SDHCI_CTRL_TUNED_CLK)
- return 0; /* Success! */
- break;
- }
-
- }
-
- pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
- mmc_hostname(host->mmc));
- sdhci_reset_tuning(host);
- return -EAGAIN;
-}
-
-int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- int err = 0;
- unsigned int tuning_count = 0;
- bool hs400_tuning;
-
- hs400_tuning = host->flags & SDHCI_HS400_TUNING;
-
- if (host->tuning_mode == SDHCI_TUNING_MODE_1)
- tuning_count = host->tuning_count;
-
- /*
- * The Host Controller needs tuning in case of SDR104 and DDR50
- * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
- * the Capabilities register.
- * If the Host Controller supports the HS200 mode then the
- * tuning function has to be executed.
- */
- switch (host->timing) {
- /* HS400 tuning is done in HS200 mode */
- case MMC_TIMING_MMC_HS400:
- err = -EINVAL;
- goto out;
-
- case MMC_TIMING_MMC_HS200:
- /*
- * Periodic re-tuning for HS400 is not expected to be needed, so
- * disable it here.
- */
- if (hs400_tuning)
- tuning_count = 0;
- break;
-
- case MMC_TIMING_UHS_SDR104:
- case MMC_TIMING_UHS_DDR50:
- break;
-
- case MMC_TIMING_UHS_SDR50:
- if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
- break;
- fallthrough;
-
- default:
- goto out;
- }
-
- if (host->ops->platform_execute_tuning) {
- err = host->ops->platform_execute_tuning(host, opcode);
- goto out;
- }
-
- mmc->retune_period = tuning_count;
-
- if (host->tuning_delay < 0)
- host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
-
- sdhci_start_tuning(host);
-
- host->tuning_err = __sdhci_execute_tuning(host, opcode);
-
- sdhci_end_tuning(host);
-out:
- host->flags &= ~SDHCI_HS400_TUNING;
-
- return err;
-}
-EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
-
-static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
-{
- /* Host Controller v3.00 defines preset value registers */
- if (host->version < SDHCI_SPEC_300)
- return;
-
- /*
- * We only enable or disable Preset Value if they are not already
- * enabled or disabled respectively. Otherwise, we bail out.
- */
- if (host->preset_enabled != enable) {
- u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-
- if (enable)
- ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
- else
- ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
-
- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
-
- if (enable)
- host->flags |= SDHCI_PV_ENABLED;
- else
- host->flags &= ~SDHCI_PV_ENABLED;
-
- host->preset_enabled = enable;
- }
-}
-
-static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
- int err)
-{
- struct mmc_data *data = mrq->data;
-
- if (data->host_cookie != COOKIE_UNMAPPED)
- dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
- mmc_get_dma_dir(data));
-
- data->host_cookie = COOKIE_UNMAPPED;
-}
-
-static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
-{
- struct sdhci_host *host = mmc_priv(mmc);
-
- mrq->data->host_cookie = COOKIE_UNMAPPED;
-
- /*
- * No pre-mapping in the pre hook if we're using the bounce buffer,
- * for that we would need two bounce buffers since one buffer is
- * in flight when this is getting called.
- */
- if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
- sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
-}
-
-static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
-{
- if (host->data_cmd) {
- host->data_cmd->error = err;
- sdhci_finish_mrq(host, host->data_cmd->mrq);
- }
-
- if (host->cmd) {
- host->cmd->error = err;
- sdhci_finish_mrq(host, host->cmd->mrq);
- }
-}
-
-static void sdhci_card_event(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
- int present;
-
- /* First check if client has provided their own card event */
- if (host->ops->card_event)
- host->ops->card_event(host);
-
- present = mmc->ops->get_cd(mmc);
-
- spin_lock_irqsave(&host->lock, flags);
-
- /* Check sdhci_has_requests() first in case we are runtime suspended */
- if (sdhci_has_requests(host) && !present) {
- pr_err("%s: Card removed during transfer!\n",
- mmc_hostname(mmc));
- pr_err("%s: Resetting controller.\n",
- mmc_hostname(mmc));
-
- sdhci_reset_for(host, CARD_REMOVED);
-
- sdhci_error_out_mrqs(host, -ENOMEDIUM);
- }
-
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-static const struct mmc_host_ops sdhci_ops = {
- .request = sdhci_request,
- .post_req = sdhci_post_req,
- .pre_req = sdhci_pre_req,
- .set_ios = sdhci_set_ios,
- .get_cd = sdhci_get_cd,
- .get_ro = sdhci_get_ro,
- .card_hw_reset = sdhci_hw_reset,
- .enable_sdio_irq = sdhci_enable_sdio_irq,
- .ack_sdio_irq = sdhci_ack_sdio_irq,
- .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
- .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
- .execute_tuning = sdhci_execute_tuning,
- .card_event = sdhci_card_event,
- .card_busy = sdhci_card_busy,
-};
-
-/*****************************************************************************\
- * *
- * Request done *
- * *
-\*****************************************************************************/
-
-static bool sdhci_request_done(struct sdhci_host *host)
-{
- unsigned long flags;
- struct mmc_request *mrq;
- int i;
-
- spin_lock_irqsave(&host->lock, flags);
-
- for (i = 0; i < SDHCI_MAX_MRQS; i++) {
- mrq = host->mrqs_done[i];
- if (mrq)
- break;
- }
-
- if (!mrq) {
- spin_unlock_irqrestore(&host->lock, flags);
- return true;
- }
-
- /*
- * The controller needs a reset of internal state machines
- * upon error conditions.
- */
- if (sdhci_needs_reset(host, mrq)) {
- /*
- * Do not finish until command and data lines are available for
- * reset. Note there can only be one other mrq, so it cannot
- * also be in mrqs_done, otherwise host->cmd and host->data_cmd
- * would both be null.
- */
- if (host->cmd || host->data_cmd) {
- spin_unlock_irqrestore(&host->lock, flags);
- return true;
- }
-
- /* Some controllers need this kick or reset won't work here */
- if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
- /* This is to force an update */
- host->ops->set_clock(host, host->clock);
-
- sdhci_reset_for(host, REQUEST_ERROR);
-
- host->pending_reset = false;
- }
-
- /*
- * Always unmap the data buffers if they were mapped by
- * sdhci_prepare_data() whenever we finish with a request.
- * This avoids leaking DMA mappings on error.
- */
- if (host->flags & SDHCI_REQ_USE_DMA) {
- struct mmc_data *data = mrq->data;
-
- if (host->use_external_dma && data &&
- (mrq->cmd->error || data->error)) {
- struct dma_chan *chan = sdhci_external_dma_channel(host, data);
-
- host->mrqs_done[i] = NULL;
- spin_unlock_irqrestore(&host->lock, flags);
- dmaengine_terminate_sync(chan);
- spin_lock_irqsave(&host->lock, flags);
- sdhci_set_mrq_done(host, mrq);
- }
-
- if (data && data->host_cookie == COOKIE_MAPPED) {
- if (host->bounce_buffer) {
- /*
- * On reads, copy the bounced data into the
- * sglist
- */
- if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
- unsigned int length = data->bytes_xfered;
-
- if (length > host->bounce_buffer_size) {
- pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
- mmc_hostname(host->mmc),
- host->bounce_buffer_size,
- data->bytes_xfered);
- /* Cap it down and continue */
- length = host->bounce_buffer_size;
- }
- dma_sync_single_for_cpu(
- mmc_dev(host->mmc),
- host->bounce_addr,
- host->bounce_buffer_size,
- DMA_FROM_DEVICE);
- sg_copy_from_buffer(data->sg,
- data->sg_len,
- host->bounce_buffer,
- length);
- } else {
- /* No copying, just switch ownership */
- dma_sync_single_for_cpu(
- mmc_dev(host->mmc),
- host->bounce_addr,
- host->bounce_buffer_size,
- mmc_get_dma_dir(data));
- }
- } else {
- /* Unmap the raw data */
- dma_unmap_sg(mmc_dev(host->mmc), data->sg,
- data->sg_len,
- mmc_get_dma_dir(data));
- }
- data->host_cookie = COOKIE_UNMAPPED;
- }
- }
-
- host->mrqs_done[i] = NULL;
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- if (host->ops->request_done)
- host->ops->request_done(host, mrq);
- else
- mmc_request_done(host->mmc, mrq);
-
- return false;
-}
-
-static void sdhci_complete_work(struct work_struct *work)
-{
- struct sdhci_host *host = container_of(work, struct sdhci_host,
- complete_work);
-
- while (!sdhci_request_done(host))
- ;
-}
-
-static void sdhci_timeout_timer(struct timer_list *t)
-{
- struct sdhci_host *host;
- unsigned long flags;
-
- host = from_timer(host, t, timer);
-
- spin_lock_irqsave(&host->lock, flags);
-
- if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
- pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
- mmc_hostname(host->mmc));
- sdhci_err_stats_inc(host, REQ_TIMEOUT);
- sdhci_dumpregs(host);
-
- host->cmd->error = -ETIMEDOUT;
- sdhci_finish_mrq(host, host->cmd->mrq);
- }
-
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-static void sdhci_timeout_data_timer(struct timer_list *t)
-{
- struct sdhci_host *host;
- unsigned long flags;
-
- host = from_timer(host, t, data_timer);
-
- spin_lock_irqsave(&host->lock, flags);
-
- if (host->data || host->data_cmd ||
- (host->cmd && sdhci_data_line_cmd(host->cmd))) {
- pr_err("%s: Timeout waiting for hardware interrupt.\n",
- mmc_hostname(host->mmc));
- sdhci_err_stats_inc(host, REQ_TIMEOUT);
- sdhci_dumpregs(host);
-
- if (host->data) {
- host->data->error = -ETIMEDOUT;
- __sdhci_finish_data(host, true);
- queue_work(host->complete_wq, &host->complete_work);
- } else if (host->data_cmd) {
- host->data_cmd->error = -ETIMEDOUT;
- sdhci_finish_mrq(host, host->data_cmd->mrq);
- } else {
- host->cmd->error = -ETIMEDOUT;
- sdhci_finish_mrq(host, host->cmd->mrq);
- }
- }
-
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-/*****************************************************************************\
- * *
- * Interrupt handling *
- * *
-\*****************************************************************************/
-
-static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
-{
- /* Handle auto-CMD12 error */
- if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
- struct mmc_request *mrq = host->data_cmd->mrq;
- u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
- int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
- SDHCI_INT_DATA_TIMEOUT :
- SDHCI_INT_DATA_CRC;
-
- /* Treat auto-CMD12 error the same as data error */
- if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
- *intmask_p |= data_err_bit;
- return;
- }
- }
-
- if (!host->cmd) {
- /*
- * SDHCI recovers from errors by resetting the cmd and data
- * circuits. Until that is done, there very well might be more
- * interrupts, so ignore them in that case.
- */
- if (host->pending_reset)
- return;
- pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
- mmc_hostname(host->mmc), (unsigned)intmask);
- sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
- sdhci_dumpregs(host);
- return;
- }
-
- if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
- SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
- if (intmask & SDHCI_INT_TIMEOUT) {
- host->cmd->error = -ETIMEDOUT;
- sdhci_err_stats_inc(host, CMD_TIMEOUT);
- } else {
- host->cmd->error = -EILSEQ;
- if (!mmc_op_tuning(host->cmd->opcode))
- sdhci_err_stats_inc(host, CMD_CRC);
- }
- /* Treat data command CRC error the same as data CRC error */
- if (host->cmd->data &&
- (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
- SDHCI_INT_CRC) {
- host->cmd = NULL;
- *intmask_p |= SDHCI_INT_DATA_CRC;
- return;
- }
-
- __sdhci_finish_mrq(host, host->cmd->mrq);
- return;
- }
-
- /* Handle auto-CMD23 error */
- if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
- struct mmc_request *mrq = host->cmd->mrq;
- u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
- int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
- -ETIMEDOUT :
- -EILSEQ;
-
- sdhci_err_stats_inc(host, AUTO_CMD);
-
- if (sdhci_auto_cmd23(host, mrq)) {
- mrq->sbc->error = err;
- __sdhci_finish_mrq(host, mrq);
- return;
- }
- }
-
- if (intmask & SDHCI_INT_RESPONSE)
- sdhci_finish_command(host);
-}
-
-static void sdhci_adma_show_error(struct sdhci_host *host)
-{
- void *desc = host->adma_table;
- dma_addr_t dma = host->adma_addr;
-
- sdhci_dumpregs(host);
-
- while (true) {
- struct sdhci_adma2_64_desc *dma_desc = desc;
-
- if (host->flags & SDHCI_USE_64_BIT_DMA)
- SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
- (unsigned long long)dma,
- le32_to_cpu(dma_desc->addr_hi),
- le32_to_cpu(dma_desc->addr_lo),
- le16_to_cpu(dma_desc->len),
- le16_to_cpu(dma_desc->cmd));
- else
- SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
- (unsigned long long)dma,
- le32_to_cpu(dma_desc->addr_lo),
- le16_to_cpu(dma_desc->len),
- le16_to_cpu(dma_desc->cmd));
-
- desc += host->desc_sz;
- dma += host->desc_sz;
-
- if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
- break;
- }
-}
-
-static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
-{
- u32 command;
-
- /*
- * CMD19 generates _only_ Buffer Read Ready interrupt if
- * use sdhci_send_tuning.
- * Need to exclude this case: PIO mode and use mmc_send_tuning,
- * If not, sdhci_transfer_pio will never be called, make the
- * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
- */
- if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
- command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
- if (command == MMC_SEND_TUNING_BLOCK ||
- command == MMC_SEND_TUNING_BLOCK_HS200) {
- host->tuning_done = 1;
- wake_up(&host->buf_ready_int);
- return;
- }
- }
-
- if (!host->data) {
- struct mmc_command *data_cmd = host->data_cmd;
-
- /*
- * The "data complete" interrupt is also used to
- * indicate that a busy state has ended. See comment
- * above in sdhci_cmd_irq().
- */
- if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
- if (intmask & SDHCI_INT_DATA_TIMEOUT) {
- host->data_cmd = NULL;
- data_cmd->error = -ETIMEDOUT;
- sdhci_err_stats_inc(host, CMD_TIMEOUT);
- __sdhci_finish_mrq(host, data_cmd->mrq);
- return;
- }
- if (intmask & SDHCI_INT_DATA_END) {
- host->data_cmd = NULL;
- /*
- * Some cards handle busy-end interrupt
- * before the command completed, so make
- * sure we do things in the proper order.
- */
- if (host->cmd == data_cmd)
- return;
-
- __sdhci_finish_mrq(host, data_cmd->mrq);
- return;
- }
- }
-
- /*
- * SDHCI recovers from errors by resetting the cmd and data
- * circuits. Until that is done, there very well might be more
- * interrupts, so ignore them in that case.
- */
- if (host->pending_reset)
- return;
-
- pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
- mmc_hostname(host->mmc), (unsigned)intmask);
- sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
- sdhci_dumpregs(host);
-
- return;
- }
-
- if (intmask & SDHCI_INT_DATA_TIMEOUT) {
- host->data->error = -ETIMEDOUT;
- sdhci_err_stats_inc(host, DAT_TIMEOUT);
- } else if (intmask & SDHCI_INT_DATA_END_BIT) {
- host->data->error = -EILSEQ;
- if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
- sdhci_err_stats_inc(host, DAT_CRC);
- } else if ((intmask & SDHCI_INT_DATA_CRC) &&
- SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
- != MMC_BUS_TEST_R) {
- host->data->error = -EILSEQ;
- if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
- sdhci_err_stats_inc(host, DAT_CRC);
- } else if (intmask & SDHCI_INT_ADMA_ERROR) {
- pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
- intmask);
- sdhci_adma_show_error(host);
- sdhci_err_stats_inc(host, ADMA);
- host->data->error = -EIO;
- if (host->ops->adma_workaround)
- host->ops->adma_workaround(host, intmask);
- }
-
- if (host->data->error)
- sdhci_finish_data(host);
- else {
- if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
- sdhci_transfer_pio(host);
-
- /*
- * We currently don't do anything fancy with DMA
- * boundaries, but as we can't disable the feature
- * we need to at least restart the transfer.
- *
- * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
- * should return a valid address to continue from, but as
- * some controllers are faulty, don't trust them.
- */
- if (intmask & SDHCI_INT_DMA_END) {
- dma_addr_t dmastart, dmanow;
-
- dmastart = sdhci_sdma_address(host);
- dmanow = dmastart + host->data->bytes_xfered;
- /*
- * Force update to the next DMA block boundary.
- */
- dmanow = (dmanow &
- ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
- SDHCI_DEFAULT_BOUNDARY_SIZE;
- host->data->bytes_xfered = dmanow - dmastart;
- DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
- &dmastart, host->data->bytes_xfered, &dmanow);
- sdhci_set_sdma_addr(host, dmanow);
- }
-
- if (intmask & SDHCI_INT_DATA_END) {
- if (host->cmd == host->data_cmd) {
- /*
- * Data managed to finish before the
- * command completed. Make sure we do
- * things in the proper order.
- */
- host->data_early = 1;
- } else {
- sdhci_finish_data(host);
- }
- }
- }
-}
-
-static inline bool sdhci_defer_done(struct sdhci_host *host,
- struct mmc_request *mrq)
-{
- struct mmc_data *data = mrq->data;
-
- return host->pending_reset || host->always_defer_done ||
- ((host->flags & SDHCI_REQ_USE_DMA) && data &&
- data->host_cookie == COOKIE_MAPPED);
-}
-
-static irqreturn_t sdhci_irq(int irq, void *dev_id)
-{
- struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
- irqreturn_t result = IRQ_NONE;
- struct sdhci_host *host = dev_id;
- u32 intmask, mask, unexpected = 0;
- int max_loops = 16;
- int i;
-
- spin_lock(&host->lock);
-
- if (host->runtime_suspended) {
- spin_unlock(&host->lock);
- return IRQ_NONE;
- }
-
- intmask = sdhci_readl(host, SDHCI_INT_STATUS);
- if (!intmask || intmask == 0xffffffff) {
- result = IRQ_NONE;
- goto out;
- }
-
- do {
- DBG("IRQ status 0x%08x\n", intmask);
-
- if (host->ops->irq) {
- intmask = host->ops->irq(host, intmask);
- if (!intmask)
- goto cont;
- }
-
- /* Clear selected interrupts. */
- mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
- SDHCI_INT_BUS_POWER);
- sdhci_writel(host, mask, SDHCI_INT_STATUS);
-
- if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
- u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
- SDHCI_CARD_PRESENT;
-
- /*
- * There is a observation on i.mx esdhc. INSERT
- * bit will be immediately set again when it gets
- * cleared, if a card is inserted. We have to mask
- * the irq to prevent interrupt storm which will
- * freeze the system. And the REMOVE gets the
- * same situation.
- *
- * More testing are needed here to ensure it works
- * for other platforms though.
- */
- host->ier &= ~(SDHCI_INT_CARD_INSERT |
- SDHCI_INT_CARD_REMOVE);
- host->ier |= present ? SDHCI_INT_CARD_REMOVE :
- SDHCI_INT_CARD_INSERT;
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-
- sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
- SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
-
- host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
- SDHCI_INT_CARD_REMOVE);
- result = IRQ_WAKE_THREAD;
- }
-
- if (intmask & SDHCI_INT_CMD_MASK)
- sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
-
- if (intmask & SDHCI_INT_DATA_MASK)
- sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
-
- if (intmask & SDHCI_INT_BUS_POWER)
- pr_err("%s: Card is consuming too much power!\n",
- mmc_hostname(host->mmc));
-
- if (intmask & SDHCI_INT_RETUNE)
- mmc_retune_needed(host->mmc);
-
- if ((intmask & SDHCI_INT_CARD_INT) &&
- (host->ier & SDHCI_INT_CARD_INT)) {
- sdhci_enable_sdio_irq_nolock(host, false);
- sdio_signal_irq(host->mmc);
- }
-
- intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
- SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
- SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
- SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
-
- if (intmask) {
- unexpected |= intmask;
- sdhci_writel(host, intmask, SDHCI_INT_STATUS);
- }
-cont:
- if (result == IRQ_NONE)
- result = IRQ_HANDLED;
-
- intmask = sdhci_readl(host, SDHCI_INT_STATUS);
- } while (intmask && --max_loops);
-
- /* Determine if mrqs can be completed immediately */
- for (i = 0; i < SDHCI_MAX_MRQS; i++) {
- struct mmc_request *mrq = host->mrqs_done[i];
-
- if (!mrq)
- continue;
-
- if (sdhci_defer_done(host, mrq)) {
- result = IRQ_WAKE_THREAD;
- } else {
- mrqs_done[i] = mrq;
- host->mrqs_done[i] = NULL;
- }
- }
-out:
- if (host->deferred_cmd)
- result = IRQ_WAKE_THREAD;
-
- spin_unlock(&host->lock);
-
- /* Process mrqs ready for immediate completion */
- for (i = 0; i < SDHCI_MAX_MRQS; i++) {
- if (!mrqs_done[i])
- continue;
-
- if (host->ops->request_done)
- host->ops->request_done(host, mrqs_done[i]);
- else
- mmc_request_done(host->mmc, mrqs_done[i]);
- }
-
- if (unexpected) {
- pr_err("%s: Unexpected interrupt 0x%08x.\n",
- mmc_hostname(host->mmc), unexpected);
- sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
- sdhci_dumpregs(host);
- }
-
- return result;
-}
-
-static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
-{
- struct sdhci_host *host = dev_id;
- struct mmc_command *cmd;
- unsigned long flags;
- u32 isr;
-
- while (!sdhci_request_done(host))
- ;
-
- spin_lock_irqsave(&host->lock, flags);
-
- isr = host->thread_isr;
- host->thread_isr = 0;
-
- cmd = host->deferred_cmd;
- if (cmd && !sdhci_send_command_retry(host, cmd, flags))
- sdhci_finish_mrq(host, cmd->mrq);
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
- struct mmc_host *mmc = host->mmc;
-
- mmc->ops->card_event(mmc);
- mmc_detect_change(mmc, msecs_to_jiffies(200));
- }
-
- return IRQ_HANDLED;
-}
-
-/*****************************************************************************\
- * *
- * Suspend/resume *
- * *
-\*****************************************************************************/
-
-#ifdef CONFIG_PM
-
-static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
-{
- return mmc_card_is_removable(host->mmc) &&
- !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
- !mmc_can_gpio_cd(host->mmc);
-}
-
-/*
- * To enable wakeup events, the corresponding events have to be enabled in
- * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
- * Table' in the SD Host Controller Standard Specification.
- * It is useless to restore SDHCI_INT_ENABLE state in
- * sdhci_disable_irq_wakeups() since it will be set by
- * sdhci_enable_card_detection() or sdhci_init().
- */
-static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
-{
- u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
- SDHCI_WAKE_ON_INT;
- u32 irq_val = 0;
- u8 wake_val = 0;
- u8 val;
-
- if (sdhci_cd_irq_can_wakeup(host)) {
- wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
- irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
- }
-
- if (mmc_card_wake_sdio_irq(host->mmc)) {
- wake_val |= SDHCI_WAKE_ON_INT;
- irq_val |= SDHCI_INT_CARD_INT;
- }
-
- if (!irq_val)
- return false;
-
- val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
- val &= ~mask;
- val |= wake_val;
- sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
-
- sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
-
- host->irq_wake_enabled = !enable_irq_wake(host->irq);
-
- return host->irq_wake_enabled;
-}
-
-static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
-{
- u8 val;
- u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
- | SDHCI_WAKE_ON_INT;
-
- val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
- val &= ~mask;
- sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
-
- disable_irq_wake(host->irq);
-
- host->irq_wake_enabled = false;
-}
-
-int sdhci_suspend_host(struct sdhci_host *host)
-{
- sdhci_disable_card_detection(host);
-
- mmc_retune_timer_stop(host->mmc);
-
- if (!device_may_wakeup(mmc_dev(host->mmc)) ||
- !sdhci_enable_irq_wakeups(host)) {
- host->ier = 0;
- sdhci_writel(host, 0, SDHCI_INT_ENABLE);
- sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
- free_irq(host->irq, host);
- }
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(sdhci_suspend_host);
-
-int sdhci_resume_host(struct sdhci_host *host)
-{
- struct mmc_host *mmc = host->mmc;
- int ret = 0;
-
- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
- if (host->ops->enable_dma)
- host->ops->enable_dma(host);
- }
-
- if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
- (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
- /* Card keeps power but host controller does not */
- sdhci_init(host, 0);
- host->pwr = 0;
- host->clock = 0;
- host->reinit_uhs = true;
- mmc->ops->set_ios(mmc, &mmc->ios);
- } else {
- sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
- }
-
- if (host->irq_wake_enabled) {
- sdhci_disable_irq_wakeups(host);
- } else {
- ret = request_threaded_irq(host->irq, sdhci_irq,
- sdhci_thread_irq, IRQF_SHARED,
- mmc_hostname(mmc), host);
- if (ret)
- return ret;
- }
-
- sdhci_enable_card_detection(host);
-
- return ret;
-}
-
-EXPORT_SYMBOL_GPL(sdhci_resume_host);
-
-int sdhci_runtime_suspend_host(struct sdhci_host *host)
-{
- unsigned long flags;
-
- mmc_retune_timer_stop(host->mmc);
-
- spin_lock_irqsave(&host->lock, flags);
- host->ier &= SDHCI_INT_CARD_INT;
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
- spin_unlock_irqrestore(&host->lock, flags);
-
- synchronize_hardirq(host->irq);
-
- spin_lock_irqsave(&host->lock, flags);
- host->runtime_suspended = true;
- spin_unlock_irqrestore(&host->lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
-
-int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
-{
- struct mmc_host *mmc = host->mmc;
- unsigned long flags;
- int host_flags = host->flags;
-
- if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
- if (host->ops->enable_dma)
- host->ops->enable_dma(host);
- }
-
- sdhci_init(host, soft_reset);
-
- if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
- mmc->ios.power_mode != MMC_POWER_OFF) {
- /* Force clock and power re-program */
- host->pwr = 0;
- host->clock = 0;
- host->reinit_uhs = true;
- mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
- mmc->ops->set_ios(mmc, &mmc->ios);
-
- if ((host_flags & SDHCI_PV_ENABLED) &&
- !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
- spin_lock_irqsave(&host->lock, flags);
- sdhci_enable_preset_value(host, true);
- spin_unlock_irqrestore(&host->lock, flags);
- }
-
- if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
- mmc->ops->hs400_enhanced_strobe)
- mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
- }
-
- spin_lock_irqsave(&host->lock, flags);
-
- host->runtime_suspended = false;
-
- /* Enable SDIO IRQ */
- if (sdio_irq_claimed(mmc))
- sdhci_enable_sdio_irq_nolock(host, true);
-
- /* Enable Card Detection */
- sdhci_enable_card_detection(host);
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
-
-#endif /* CONFIG_PM */
-
-/*****************************************************************************\
- * *
- * Command Queue Engine (CQE) helpers *
- * *
-\*****************************************************************************/
-
-void sdhci_cqe_enable(struct mmc_host *mmc)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
- u8 ctrl;
-
- spin_lock_irqsave(&host->lock, flags);
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl &= ~SDHCI_CTRL_DMA_MASK;
- /*
- * Host from V4.10 supports ADMA3 DMA type.
- * ADMA3 performs integrated descriptor which is more suitable
- * for cmd queuing to fetch both command and transfer descriptors.
- */
- if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
- ctrl |= SDHCI_CTRL_ADMA3;
- else if (host->flags & SDHCI_USE_64_BIT_DMA)
- ctrl |= SDHCI_CTRL_ADMA64;
- else
- ctrl |= SDHCI_CTRL_ADMA32;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
- SDHCI_BLOCK_SIZE);
-
- /* Set maximum timeout */
- sdhci_set_timeout(host, NULL);
-
- host->ier = host->cqe_ier;
-
- sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-
- host->cqe_on = true;
-
- pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
- mmc_hostname(mmc), host->ier,
- sdhci_readl(host, SDHCI_INT_STATUS));
-
- spin_unlock_irqrestore(&host->lock, flags);
-}
-EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
-
-void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
-{
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
-
- spin_lock_irqsave(&host->lock, flags);
-
- sdhci_set_default_irqs(host);
-
- host->cqe_on = false;
-
- if (recovery)
- sdhci_reset_for(host, CQE_RECOVERY);
-
- pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
- mmc_hostname(mmc), host->ier,
- sdhci_readl(host, SDHCI_INT_STATUS));
-
- spin_unlock_irqrestore(&host->lock, flags);
-}
-EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
-
-bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
- int *data_error)
-{
- u32 mask;
-
- if (!host->cqe_on)
- return false;
-
- if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
- *cmd_error = -EILSEQ;
- if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
- sdhci_err_stats_inc(host, CMD_CRC);
- } else if (intmask & SDHCI_INT_TIMEOUT) {
- *cmd_error = -ETIMEDOUT;
- sdhci_err_stats_inc(host, CMD_TIMEOUT);
- } else
- *cmd_error = 0;
-
- if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) {
- *data_error = -EILSEQ;
- if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
- sdhci_err_stats_inc(host, DAT_CRC);
- } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
- *data_error = -ETIMEDOUT;
- sdhci_err_stats_inc(host, DAT_TIMEOUT);
- } else if (intmask & SDHCI_INT_ADMA_ERROR) {
- *data_error = -EIO;
- sdhci_err_stats_inc(host, ADMA);
- } else
- *data_error = 0;
-
- /* Clear selected interrupts. */
- mask = intmask & host->cqe_ier;
- sdhci_writel(host, mask, SDHCI_INT_STATUS);
-
- if (intmask & SDHCI_INT_BUS_POWER)
- pr_err("%s: Card is consuming too much power!\n",
- mmc_hostname(host->mmc));
-
- intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
- if (intmask) {
- sdhci_writel(host, intmask, SDHCI_INT_STATUS);
- pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
- mmc_hostname(host->mmc), intmask);
- sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
- sdhci_dumpregs(host);
- }
-
- return true;
-}
-EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
-
-/*****************************************************************************\
- * *
- * Device allocation/registration *
- * *
-\*****************************************************************************/
-
-struct sdhci_host *sdhci_alloc_host(struct device *dev,
- size_t priv_size)
-{
- struct mmc_host *mmc;
- struct sdhci_host *host;
-
- WARN_ON(dev == NULL);
-
- mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
- if (!mmc)
- return ERR_PTR(-ENOMEM);
-
- host = mmc_priv(mmc);
- host->mmc = mmc;
- host->mmc_host_ops = sdhci_ops;
- mmc->ops = &host->mmc_host_ops;
-
- host->flags = SDHCI_SIGNALING_330;
-
- host->cqe_ier = SDHCI_CQE_INT_MASK;
- host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
-
- host->tuning_delay = -1;
- host->tuning_loop_count = MAX_TUNING_LOOP;
-
- host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
-
- /*
- * The DMA table descriptor count is calculated as the maximum
- * number of segments times 2, to allow for an alignment
- * descriptor for each segment, plus 1 for a nop end descriptor.
- */
- host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
- host->max_adma = 65536;
-
- host->max_timeout_count = 0xE;
-
- return host;
-}
-
-EXPORT_SYMBOL_GPL(sdhci_alloc_host);
-
-static int sdhci_set_dma_mask(struct sdhci_host *host)
-{
- struct mmc_host *mmc = host->mmc;
- struct device *dev = mmc_dev(mmc);
- int ret = -EINVAL;
-
- if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
- host->flags &= ~SDHCI_USE_64_BIT_DMA;
-
- /* Try 64-bit mask if hardware is capable of it */
- if (host->flags & SDHCI_USE_64_BIT_DMA) {
- ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
- if (ret) {
- pr_warn("%s: Failed to set 64-bit DMA mask.\n",
- mmc_hostname(mmc));
- host->flags &= ~SDHCI_USE_64_BIT_DMA;
- }
- }
-
- /* 32-bit mask as default & fallback */
- if (ret) {
- ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
- if (ret)
- pr_warn("%s: Failed to set 32-bit DMA mask.\n",
- mmc_hostname(mmc));
- }
-
- return ret;
-}
-
-void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
- const u32 *caps, const u32 *caps1)
-{
- u16 v;
- u64 dt_caps_mask = 0;
- u64 dt_caps = 0;
-
- if (host->read_caps)
- return;
-
- host->read_caps = true;
-
- if (debug_quirks)
- host->quirks = debug_quirks;
-
- if (debug_quirks2)
- host->quirks2 = debug_quirks2;
-
- sdhci_reset_for_all(host);
-
- if (host->v4_mode)
- sdhci_do_enable_v4_mode(host);
-
- device_property_read_u64(mmc_dev(host->mmc),
- "sdhci-caps-mask", &dt_caps_mask);
- device_property_read_u64(mmc_dev(host->mmc),
- "sdhci-caps", &dt_caps);
-
- v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
- host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
-
- if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
- return;
-
- if (caps) {
- host->caps = *caps;
- } else {
- host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
- host->caps &= ~lower_32_bits(dt_caps_mask);
- host->caps |= lower_32_bits(dt_caps);
- }
-
- if (host->version < SDHCI_SPEC_300)
- return;
-
- if (caps1) {
- host->caps1 = *caps1;
- } else {
- host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
- host->caps1 &= ~upper_32_bits(dt_caps_mask);
- host->caps1 |= upper_32_bits(dt_caps);
- }
-}
-EXPORT_SYMBOL_GPL(__sdhci_read_caps);
-
-static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
-{
- struct mmc_host *mmc = host->mmc;
- unsigned int max_blocks;
- unsigned int bounce_size;
- int ret;
-
- /*
- * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
- * has diminishing returns, this is probably because SD/MMC
- * cards are usually optimized to handle this size of requests.
- */
- bounce_size = SZ_64K;
- /*
- * Adjust downwards to maximum request size if this is less
- * than our segment size, else hammer down the maximum
- * request size to the maximum buffer size.
- */
- if (mmc->max_req_size < bounce_size)
- bounce_size = mmc->max_req_size;
- max_blocks = bounce_size / 512;
-
- /*
- * When we just support one segment, we can get significant
- * speedups by the help of a bounce buffer to group scattered
- * reads/writes together.
- */
- host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
- bounce_size,
- GFP_KERNEL);
- if (!host->bounce_buffer) {
- pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
- mmc_hostname(mmc),
- bounce_size);
- /*
- * Exiting with zero here makes sure we proceed with
- * mmc->max_segs == 1.
- */
- return;
- }
-
- host->bounce_addr = dma_map_single(mmc_dev(mmc),
- host->bounce_buffer,
- bounce_size,
- DMA_BIDIRECTIONAL);
- ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
- if (ret) {
- devm_kfree(mmc_dev(mmc), host->bounce_buffer);
- host->bounce_buffer = NULL;
- /* Again fall back to max_segs == 1 */
- return;
- }
-
- host->bounce_buffer_size = bounce_size;
-
- /* Lie about this since we're bouncing */
- mmc->max_segs = max_blocks;
- mmc->max_seg_size = bounce_size;
- mmc->max_req_size = bounce_size;
-
- pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
- mmc_hostname(mmc), max_blocks, bounce_size);
-}
-
-static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
-{
- /*
- * According to SD Host Controller spec v4.10, bit[27] added from
- * version 4.10 in Capabilities Register is used as 64-bit System
- * Address support for V4 mode.
- */
- if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
- return host->caps & SDHCI_CAN_64BIT_V4;
-
- return host->caps & SDHCI_CAN_64BIT;
-}
-
-int sdhci_setup_host(struct sdhci_host *host)
-{
- struct mmc_host *mmc;
- u32 max_current_caps;
- unsigned int ocr_avail;
- unsigned int override_timeout_clk;
- u32 max_clk;
- int ret = 0;
- bool enable_vqmmc = false;
-
- WARN_ON(host == NULL);
- if (host == NULL)
- return -EINVAL;
-
- mmc = host->mmc;
-
- /*
- * If there are external regulators, get them. Note this must be done
- * early before resetting the host and reading the capabilities so that
- * the host can take the appropriate action if regulators are not
- * available.
- */
- if (!mmc->supply.vqmmc) {
- ret = mmc_regulator_get_supply(mmc);
- if (ret)
- return ret;
- enable_vqmmc = true;
- }
-
- DBG("Version: 0x%08x | Present: 0x%08x\n",
- sdhci_readw(host, SDHCI_HOST_VERSION),
- sdhci_readl(host, SDHCI_PRESENT_STATE));
- DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
- sdhci_readl(host, SDHCI_CAPABILITIES),
- sdhci_readl(host, SDHCI_CAPABILITIES_1));
-
- sdhci_read_caps(host);
-
- override_timeout_clk = host->timeout_clk;
-
- if (host->version > SDHCI_SPEC_420) {
- pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
- mmc_hostname(mmc), host->version);
- }
-
- if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
- host->flags |= SDHCI_USE_SDMA;
- else if (!(host->caps & SDHCI_CAN_DO_SDMA))
- DBG("Controller doesn't have SDMA capability\n");
- else
- host->flags |= SDHCI_USE_SDMA;
-
- if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
- (host->flags & SDHCI_USE_SDMA)) {
- DBG("Disabling DMA as it is marked broken\n");
- host->flags &= ~SDHCI_USE_SDMA;
- }
-
- if ((host->version >= SDHCI_SPEC_200) &&
- (host->caps & SDHCI_CAN_DO_ADMA2))
- host->flags |= SDHCI_USE_ADMA;
-
- if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
- (host->flags & SDHCI_USE_ADMA)) {
- DBG("Disabling ADMA as it is marked broken\n");
- host->flags &= ~SDHCI_USE_ADMA;
- }
-
- if (sdhci_can_64bit_dma(host))
- host->flags |= SDHCI_USE_64_BIT_DMA;
-
- if (host->use_external_dma) {
- ret = sdhci_external_dma_init(host);
- if (ret == -EPROBE_DEFER)
- goto unreg;
- /*
- * Fall back to use the DMA/PIO integrated in standard SDHCI
- * instead of external DMA devices.
- */
- else if (ret)
- sdhci_switch_external_dma(host, false);
- /* Disable internal DMA sources */
- else
- host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
- }
-
- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
- if (host->ops->set_dma_mask)
- ret = host->ops->set_dma_mask(host);
- else
- ret = sdhci_set_dma_mask(host);
-
- if (!ret && host->ops->enable_dma)
- ret = host->ops->enable_dma(host);
-
- if (ret) {
- pr_warn("%s: No suitable DMA available - falling back to PIO\n",
- mmc_hostname(mmc));
- host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
-
- ret = 0;
- }
- }
-
- /* SDMA does not support 64-bit DMA if v4 mode not set */
- if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
- host->flags &= ~SDHCI_USE_SDMA;
-
- if (host->flags & SDHCI_USE_ADMA) {
- dma_addr_t dma;
- void *buf;
-
- if (!(host->flags & SDHCI_USE_64_BIT_DMA))
- host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
- else if (!host->alloc_desc_sz)
- host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
-
- host->desc_sz = host->alloc_desc_sz;
- host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
-
- host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
- /*
- * Use zalloc to zero the reserved high 32-bits of 128-bit
- * descriptors so that they never need to be written.
- */
- buf = dma_alloc_coherent(mmc_dev(mmc),
- host->align_buffer_sz + host->adma_table_sz,
- &dma, GFP_KERNEL);
- if (!buf) {
- pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
- mmc_hostname(mmc));
- host->flags &= ~SDHCI_USE_ADMA;
- } else if ((dma + host->align_buffer_sz) &
- (SDHCI_ADMA2_DESC_ALIGN - 1)) {
- pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
- mmc_hostname(mmc));
- host->flags &= ~SDHCI_USE_ADMA;
- dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
- host->adma_table_sz, buf, dma);
- } else {
- host->align_buffer = buf;
- host->align_addr = dma;
-
- host->adma_table = buf + host->align_buffer_sz;
- host->adma_addr = dma + host->align_buffer_sz;
- }
- }
-
- /*
- * If we use DMA, then it's up to the caller to set the DMA
- * mask, but PIO does not need the hw shim so we set a new
- * mask here in that case.
- */
- if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
- host->dma_mask = DMA_BIT_MASK(64);
- mmc_dev(mmc)->dma_mask = &host->dma_mask;
- }
-
- if (host->version >= SDHCI_SPEC_300)
- host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
- else
- host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
-
- host->max_clk *= 1000000;
- if (host->max_clk == 0 || host->quirks &
- SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
- if (!host->ops->get_max_clock) {
- pr_err("%s: Hardware doesn't specify base clock frequency.\n",
- mmc_hostname(mmc));
- ret = -ENODEV;
- goto undma;
- }
- host->max_clk = host->ops->get_max_clock(host);
- }
-
- /*
- * In case of Host Controller v3.00, find out whether clock
- * multiplier is supported.
- */
- host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
-
- /*
- * In case the value in Clock Multiplier is 0, then programmable
- * clock mode is not supported, otherwise the actual clock
- * multiplier is one more than the value of Clock Multiplier
- * in the Capabilities Register.
- */
- if (host->clk_mul)
- host->clk_mul += 1;
-
- /*
- * Set host parameters.
- */
- max_clk = host->max_clk;
-
- if (host->ops->get_min_clock)
- mmc->f_min = host->ops->get_min_clock(host);
- else if (host->version >= SDHCI_SPEC_300) {
- if (host->clk_mul)
- max_clk = host->max_clk * host->clk_mul;
- /*
- * Divided Clock Mode minimum clock rate is always less than
- * Programmable Clock Mode minimum clock rate.
- */
- mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
- } else
- mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
-
- if (!mmc->f_max || mmc->f_max > max_clk)
- mmc->f_max = max_clk;
-
- if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
- host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
-
- if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
- host->timeout_clk *= 1000;
-
- if (host->timeout_clk == 0) {
- if (!host->ops->get_timeout_clock) {
- pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
- mmc_hostname(mmc));
- ret = -ENODEV;
- goto undma;
- }
-
- host->timeout_clk =
- DIV_ROUND_UP(host->ops->get_timeout_clock(host),
- 1000);
- }
-
- if (override_timeout_clk)
- host->timeout_clk = override_timeout_clk;
-
- mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
- host->ops->get_max_timeout_count(host) : 1 << 27;
- mmc->max_busy_timeout /= host->timeout_clk;
- }
-
- if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
- !host->ops->get_max_timeout_count)
- mmc->max_busy_timeout = 0;
-
- mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
- mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
-
- if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
- host->flags |= SDHCI_AUTO_CMD12;
-
- /*
- * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
- * For v4 mode, SDMA may use Auto-CMD23 as well.
- */
- if ((host->version >= SDHCI_SPEC_300) &&
- ((host->flags & SDHCI_USE_ADMA) ||
- !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
- !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
- host->flags |= SDHCI_AUTO_CMD23;
- DBG("Auto-CMD23 available\n");
- } else {
- DBG("Auto-CMD23 unavailable\n");
- }
-
- /*
- * A controller may support 8-bit width, but the board itself
- * might not have the pins brought out. Boards that support
- * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
- * their platform code before calling sdhci_add_host(), and we
- * won't assume 8-bit width for hosts without that CAP.
- */
- if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
- mmc->caps |= MMC_CAP_4_BIT_DATA;
-
- if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
- mmc->caps &= ~MMC_CAP_CMD23;
-
- if (host->caps & SDHCI_CAN_DO_HISPD)
- mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
-
- if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
- mmc_card_is_removable(mmc) &&
- mmc_gpio_get_cd(mmc) < 0)
- mmc->caps |= MMC_CAP_NEEDS_POLL;
-
- if (!IS_ERR(mmc->supply.vqmmc)) {
- if (enable_vqmmc) {
- ret = regulator_enable(mmc->supply.vqmmc);
- host->sdhci_core_to_disable_vqmmc = !ret;
- }
-
- /* If vqmmc provides no 1.8V signalling, then there's no UHS */
- if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
- 1950000))
- host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
- SDHCI_SUPPORT_SDR50 |
- SDHCI_SUPPORT_DDR50);
-
- /* In eMMC case vqmmc might be a fixed 1.8V regulator */
- if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
- 3600000))
- host->flags &= ~SDHCI_SIGNALING_330;
-
- if (ret) {
- pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
- mmc_hostname(mmc), ret);
- mmc->supply.vqmmc = ERR_PTR(-EINVAL);
- }
-
- }
-
- if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
- host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
- SDHCI_SUPPORT_DDR50);
- /*
- * The SDHCI controller in a SoC might support HS200/HS400
- * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
- * but if the board is modeled such that the IO lines are not
- * connected to 1.8v then HS200/HS400 cannot be supported.
- * Disable HS200/HS400 if the board does not have 1.8v connected
- * to the IO lines. (Applicable for other modes in 1.8v)
- */
- mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
- mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
- }
-
- /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
- if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
- SDHCI_SUPPORT_DDR50))
- mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
-
- /* SDR104 supports also implies SDR50 support */
- if (host->caps1 & SDHCI_SUPPORT_SDR104) {
- mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
- /* SD3.0: SDR104 is supported so (for eMMC) the caps2
- * field can be promoted to support HS200.
- */
- if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
- mmc->caps2 |= MMC_CAP2_HS200;
- } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
- mmc->caps |= MMC_CAP_UHS_SDR50;
- }
-
- if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
- (host->caps1 & SDHCI_SUPPORT_HS400))
- mmc->caps2 |= MMC_CAP2_HS400;
-
- if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
- (IS_ERR(mmc->supply.vqmmc) ||
- !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
- 1300000)))
- mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
-
- if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
- !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
- mmc->caps |= MMC_CAP_UHS_DDR50;
-
- /* Does the host need tuning for SDR50? */
- if (host->caps1 & SDHCI_USE_SDR50_TUNING)
- host->flags |= SDHCI_SDR50_NEEDS_TUNING;
-
- /* Driver Type(s) (A, C, D) supported by the host */
- if (host->caps1 & SDHCI_DRIVER_TYPE_A)
- mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
- if (host->caps1 & SDHCI_DRIVER_TYPE_C)
- mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
- if (host->caps1 & SDHCI_DRIVER_TYPE_D)
- mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
-
- /* Initial value for re-tuning timer count */
- host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
- host->caps1);
-
- /*
- * In case Re-tuning Timer is not disabled, the actual value of
- * re-tuning timer will be 2 ^ (n - 1).
- */
- if (host->tuning_count)
- host->tuning_count = 1 << (host->tuning_count - 1);
-
- /* Re-tuning mode supported by the Host Controller */
- host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
-
- ocr_avail = 0;
-
- /*
- * According to SD Host Controller spec v3.00, if the Host System
- * can afford more than 150mA, Host Driver should set XPC to 1. Also
- * the value is meaningful only if Voltage Support in the Capabilities
- * register is set. The actual current value is 4 times the register
- * value.
- */
- max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
- if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
- int curr = regulator_get_current_limit(mmc->supply.vmmc);
- if (curr > 0) {
-
- /* convert to SDHCI_MAX_CURRENT format */
- curr = curr/1000; /* convert to mA */
- curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
-
- curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
- max_current_caps =
- FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
- FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
- FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
- }
- }
-
- if (host->caps & SDHCI_CAN_VDD_330) {
- ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
-
- mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
- max_current_caps) *
- SDHCI_MAX_CURRENT_MULTIPLIER;
- }
- if (host->caps & SDHCI_CAN_VDD_300) {
- ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
-
- mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
- max_current_caps) *
- SDHCI_MAX_CURRENT_MULTIPLIER;
- }
- if (host->caps & SDHCI_CAN_VDD_180) {
- ocr_avail |= MMC_VDD_165_195;
-
- mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
- max_current_caps) *
- SDHCI_MAX_CURRENT_MULTIPLIER;
- }
-
- /* If OCR set by host, use it instead. */
- if (host->ocr_mask)
- ocr_avail = host->ocr_mask;
-
- /* If OCR set by external regulators, give it highest prio. */
- if (mmc->ocr_avail)
- ocr_avail = mmc->ocr_avail;
-
- mmc->ocr_avail = ocr_avail;
- mmc->ocr_avail_sdio = ocr_avail;
- if (host->ocr_avail_sdio)
- mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
- mmc->ocr_avail_sd = ocr_avail;
- if (host->ocr_avail_sd)
- mmc->ocr_avail_sd &= host->ocr_avail_sd;
- else /* normal SD controllers don't support 1.8V */
- mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
- mmc->ocr_avail_mmc = ocr_avail;
- if (host->ocr_avail_mmc)
- mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
-
- if (mmc->ocr_avail == 0) {
- pr_err("%s: Hardware doesn't report any support voltages.\n",
- mmc_hostname(mmc));
- ret = -ENODEV;
- goto unreg;
- }
-
- if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
- MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
- MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
- (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
- host->flags |= SDHCI_SIGNALING_180;
-
- if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
- host->flags |= SDHCI_SIGNALING_120;
-
- spin_lock_init(&host->lock);
-
- /*
- * Maximum number of sectors in one transfer. Limited by SDMA boundary
- * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
- * is less anyway.
- */
- mmc->max_req_size = 524288;
-
- /*
- * Maximum number of segments. Depends on if the hardware
- * can do scatter/gather or not.
- */
- if (host->flags & SDHCI_USE_ADMA) {
- mmc->max_segs = SDHCI_MAX_SEGS;
- } else if (host->flags & SDHCI_USE_SDMA) {
- mmc->max_segs = 1;
- mmc->max_req_size = min_t(size_t, mmc->max_req_size,
- dma_max_mapping_size(mmc_dev(mmc)));
- } else { /* PIO */
- mmc->max_segs = SDHCI_MAX_SEGS;
- }
-
- /*
- * Maximum segment size. Could be one segment with the maximum number
- * of bytes. When doing hardware scatter/gather, each entry cannot
- * be larger than 64 KiB though.
- */
- if (host->flags & SDHCI_USE_ADMA) {
- if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
- host->max_adma = 65532; /* 32-bit alignment */
- mmc->max_seg_size = 65535;
- } else {
- mmc->max_seg_size = 65536;
- }
- } else {
- mmc->max_seg_size = mmc->max_req_size;
- }
-
- /*
- * Maximum block size. This varies from controller to controller and
- * is specified in the capabilities register.
- */
- if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
- mmc->max_blk_size = 2;
- } else {
- mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
- SDHCI_MAX_BLOCK_SHIFT;
- if (mmc->max_blk_size >= 3) {
- pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
- mmc_hostname(mmc));
- mmc->max_blk_size = 0;
- }
- }
-
- mmc->max_blk_size = 512 << mmc->max_blk_size;
-
- /*
- * Maximum block count.
- */
- mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
-
- if (mmc->max_segs == 1)
- /* This may alter mmc->*_blk_* parameters */
- sdhci_allocate_bounce_buffer(host);
-
- return 0;
-
-unreg:
- if (host->sdhci_core_to_disable_vqmmc)
- regulator_disable(mmc->supply.vqmmc);
-undma:
- if (host->align_buffer)
- dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
- host->adma_table_sz, host->align_buffer,
- host->align_addr);
- host->adma_table = NULL;
- host->align_buffer = NULL;
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(sdhci_setup_host);
-
-void sdhci_cleanup_host(struct sdhci_host *host)
-{
- struct mmc_host *mmc = host->mmc;
-
- if (host->sdhci_core_to_disable_vqmmc)
- regulator_disable(mmc->supply.vqmmc);
-
- if (host->align_buffer)
- dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
- host->adma_table_sz, host->align_buffer,
- host->align_addr);
-
- if (host->use_external_dma)
- sdhci_external_dma_release(host);
-
- host->adma_table = NULL;
- host->align_buffer = NULL;
-}
-EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
-
-int __sdhci_add_host(struct sdhci_host *host)
-{
- unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
- struct mmc_host *mmc = host->mmc;
- int ret;
-
- if ((mmc->caps2 & MMC_CAP2_CQE) &&
- (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
- mmc->caps2 &= ~MMC_CAP2_CQE;
- mmc->cqe_ops = NULL;
- }
-
- host->complete_wq = alloc_workqueue("sdhci", flags, 0);
- if (!host->complete_wq)
- return -ENOMEM;
-
- INIT_WORK(&host->complete_work, sdhci_complete_work);
-
- timer_setup(&host->timer, sdhci_timeout_timer, 0);
- timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
-
- init_waitqueue_head(&host->buf_ready_int);
-
- sdhci_init(host, 0);
-
- ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
- IRQF_SHARED, mmc_hostname(mmc), host);
- if (ret) {
- pr_err("%s: Failed to request IRQ %d: %d\n",
- mmc_hostname(mmc), host->irq, ret);
- goto unwq;
- }
-
- ret = sdhci_led_register(host);
- if (ret) {
- pr_err("%s: Failed to register LED device: %d\n",
- mmc_hostname(mmc), ret);
- goto unirq;
- }
-
- ret = mmc_add_host(mmc);
- if (ret)
- goto unled;
-
- pr_info("%s: SDHCI controller on %s [%s] using %s\n",
- mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
- host->use_external_dma ? "External DMA" :
- (host->flags & SDHCI_USE_ADMA) ?
- (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
- (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
-
- sdhci_enable_card_detection(host);
-
- return 0;
-
-unled:
- sdhci_led_unregister(host);
-unirq:
- sdhci_reset_for_all(host);
- sdhci_writel(host, 0, SDHCI_INT_ENABLE);
- sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
- free_irq(host->irq, host);
-unwq:
- destroy_workqueue(host->complete_wq);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(__sdhci_add_host);
-
-int sdhci_add_host(struct sdhci_host *host)
-{
- int ret;
-
- ret = sdhci_setup_host(host);
- if (ret)
- return ret;
-
- ret = __sdhci_add_host(host);
- if (ret)
- goto cleanup;
-
- return 0;
-
-cleanup:
- sdhci_cleanup_host(host);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(sdhci_add_host);
-
-void sdhci_remove_host(struct sdhci_host *host, int dead)
-{
- struct mmc_host *mmc = host->mmc;
- unsigned long flags;
-
- if (dead) {
- spin_lock_irqsave(&host->lock, flags);
-
- host->flags |= SDHCI_DEVICE_DEAD;
-
- if (sdhci_has_requests(host)) {
- pr_err("%s: Controller removed during "
- " transfer!\n", mmc_hostname(mmc));
- sdhci_error_out_mrqs(host, -ENOMEDIUM);
- }
-
- spin_unlock_irqrestore(&host->lock, flags);
- }
-
- sdhci_disable_card_detection(host);
-
- mmc_remove_host(mmc);
-
- sdhci_led_unregister(host);
-
- if (!dead)
- sdhci_reset_for_all(host);
-
- sdhci_writel(host, 0, SDHCI_INT_ENABLE);
- sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
- free_irq(host->irq, host);
-
- del_timer_sync(&host->timer);
- del_timer_sync(&host->data_timer);
-
- destroy_workqueue(host->complete_wq);
-
- if (host->sdhci_core_to_disable_vqmmc)
- regulator_disable(mmc->supply.vqmmc);
-
- if (host->align_buffer)
- dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
- host->adma_table_sz, host->align_buffer,
- host->align_addr);
-
- if (host->use_external_dma)
- sdhci_external_dma_release(host);
-
- host->adma_table = NULL;
- host->align_buffer = NULL;
-}
-
-EXPORT_SYMBOL_GPL(sdhci_remove_host);
-
-void sdhci_free_host(struct sdhci_host *host)
-{
- mmc_free_host(host->mmc);
-}
-
-EXPORT_SYMBOL_GPL(sdhci_free_host);
-
-/*****************************************************************************\
- * *
- * Driver init/exit *
- * *
-\*****************************************************************************/
-
-static int __init sdhci_drv_init(void)
-{
- pr_info(DRIVER_NAME
- ": Secure Digital Host Controller Interface driver\n");
- pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
-
- return 0;
-}
-
-static void __exit sdhci_drv_exit(void)
-{
-}
-
-module_init(sdhci_drv_init);
-module_exit(sdhci_drv_exit);
-
-module_param(debug_quirks, uint, 0444);
-module_param(debug_quirks2, uint, 0444);
-
-MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
-MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
-MODULE_LICENSE("GPL");
-
-MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
-MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Index: v6.x/create-6.1.26-host-limits-patch/file.list
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/file.list (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/file.list (nonexistent)
@@ -1,7 +0,0 @@
-linux-6.1.26/scripts/kconfig/conf.c
-linux-6.1.26/scripts/kconfig/confdata.c
-linux-6.1.26/scripts/kconfig/lexer.l
-linux-6.1.26/scripts/mod/modpost.c
-linux-6.1.26/scripts/mod/sumversion.c
-linux-6.1.26/tools/build/fixdep.c
-linux-6.1.26/usr/gen_init_cpio.c
Index: v6.x/create-6.1.26-host-limits-patch/create.patch.sh
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/create.patch.sh (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/create.patch.sh (nonexistent)
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-VERSION=6.1.26
-
-tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
-mv linux-$VERSION linux-$VERSION-orig
-
-cp -rf ./linux-$VERSION-new ./linux-$VERSION
-
-diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-host-limits.patch
-
-mv linux-$VERSION-host-limits.patch ../patches
-
-rm -rf ./linux-$VERSION
-rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.1.26-host-limits-patch/create.patch.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/mod/modpost.c
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/mod/modpost.c (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/mod/modpost.c (nonexistent)
@@ -1,2407 +0,0 @@
-/* Postprocess module symbol versions
- *
- * Copyright 2003 Kai Germaschewski
- * Copyright 2002-2004 Rusty Russell, IBM Corporation
- * Copyright 2006-2008 Sam Ravnborg
- * Based in part on module-init-tools/depmod.c,file2alias
- *
- * This software may be used and distributed according to the terms
- * of the GNU General Public License, incorporated herein by reference.
- *
- * Usage: modpost vmlinux module1.o module2.o ...
- */
-
-#define _GNU_SOURCE
-#include <elf.h>
-#include <fnmatch.h>
-#include <stdio.h>
-#include <ctype.h>
-#include <string.h>
-#include <linux/limits.h>
-#include <stdbool.h>
-#include <errno.h>
-#include "modpost.h"
-#include "../../include/linux/license.h"
-
-/* Are we using CONFIG_MODVERSIONS? */
-static bool modversions;
-/* Is CONFIG_MODULE_SRCVERSION_ALL set? */
-static bool all_versions;
-/* If we are modposting external module set to 1 */
-static bool external_module;
-/* Only warn about unresolved symbols */
-static bool warn_unresolved;
-
-static int sec_mismatch_count;
-static bool sec_mismatch_warn_only = true;
-/* ignore missing files */
-static bool ignore_missing_files;
-/* If set to 1, only warn (instead of error) about missing ns imports */
-static bool allow_missing_ns_imports;
-
-static bool error_occurred;
-
-/*
- * Cut off the warnings when there are too many. This typically occurs when
- * vmlinux is missing. ('make modules' without building vmlinux.)
- */
-#define MAX_UNRESOLVED_REPORTS 10
-static unsigned int nr_unresolved;
-
-/* In kernel, this size is defined in linux/module.h;
- * here we use Elf_Addr instead of long for covering cross-compile
- */
-
-#define MODULE_NAME_LEN (64 - sizeof(Elf_Addr))
-
-void __attribute__((format(printf, 2, 3)))
-modpost_log(enum loglevel loglevel, const char *fmt, ...)
-{
- va_list arglist;
-
- switch (loglevel) {
- case LOG_WARN:
- fprintf(stderr, "WARNING: ");
- break;
- case LOG_ERROR:
- fprintf(stderr, "ERROR: ");
- break;
- case LOG_FATAL:
- fprintf(stderr, "FATAL: ");
- break;
- default: /* invalid loglevel, ignore */
- break;
- }
-
- fprintf(stderr, "modpost: ");
-
- va_start(arglist, fmt);
- vfprintf(stderr, fmt, arglist);
- va_end(arglist);
-
- if (loglevel == LOG_FATAL)
- exit(1);
- if (loglevel == LOG_ERROR)
- error_occurred = true;
-}
-
-static inline bool strends(const char *str, const char *postfix)
-{
- if (strlen(str) < strlen(postfix))
- return false;
-
- return strcmp(str + strlen(str) - strlen(postfix), postfix) == 0;
-}
-
-void *do_nofail(void *ptr, const char *expr)
-{
- if (!ptr)
- fatal("Memory allocation failure: %s.\n", expr);
-
- return ptr;
-}
-
-char *read_text_file(const char *filename)
-{
- struct stat st;
- size_t nbytes;
- int fd;
- char *buf;
-
- fd = open(filename, O_RDONLY);
- if (fd < 0) {
- perror(filename);
- exit(1);
- }
-
- if (fstat(fd, &st) < 0) {
- perror(filename);
- exit(1);
- }
-
- buf = NOFAIL(malloc(st.st_size + 1));
-
- nbytes = st.st_size;
-
- while (nbytes) {
- ssize_t bytes_read;
-
- bytes_read = read(fd, buf, nbytes);
- if (bytes_read < 0) {
- perror(filename);
- exit(1);
- }
-
- nbytes -= bytes_read;
- }
- buf[st.st_size] = '\0';
-
- close(fd);
-
- return buf;
-}
-
-char *get_line(char **stringp)
-{
- char *orig = *stringp, *next;
-
- /* do not return the unwanted extra line at EOF */
- if (!orig || *orig == '\0')
- return NULL;
-
- /* don't use strsep here, it is not available everywhere */
- next = strchr(orig, '\n');
- if (next)
- *next++ = '\0';
-
- *stringp = next;
-
- return orig;
-}
-
-/* A list of all modules we processed */
-LIST_HEAD(modules);
-
-static struct module *find_module(const char *modname)
-{
- struct module *mod;
-
- list_for_each_entry(mod, &modules, list) {
- if (strcmp(mod->name, modname) == 0)
- return mod;
- }
- return NULL;
-}
-
-static struct module *new_module(const char *name, size_t namelen)
-{
- struct module *mod;
-
- mod = NOFAIL(malloc(sizeof(*mod) + namelen + 1));
- memset(mod, 0, sizeof(*mod));
-
- INIT_LIST_HEAD(&mod->exported_symbols);
- INIT_LIST_HEAD(&mod->unresolved_symbols);
- INIT_LIST_HEAD(&mod->missing_namespaces);
- INIT_LIST_HEAD(&mod->imported_namespaces);
-
- memcpy(mod->name, name, namelen);
- mod->name[namelen] = '\0';
- mod->is_vmlinux = (strcmp(mod->name, "vmlinux") == 0);
-
- /*
- * Set mod->is_gpl_compatible to true by default. If MODULE_LICENSE()
- * is missing, do not check the use for EXPORT_SYMBOL_GPL() becasue
- * modpost will exit wiht error anyway.
- */
- mod->is_gpl_compatible = true;
-
- list_add_tail(&mod->list, &modules);
-
- return mod;
-}
-
-/* A hash of all exported symbols,
- * struct symbol is also used for lists of unresolved symbols */
-
-#define SYMBOL_HASH_SIZE 1024
-
-struct symbol {
- struct symbol *next;
- struct list_head list; /* link to module::exported_symbols or module::unresolved_symbols */
- struct module *module;
- char *namespace;
- unsigned int crc;
- bool crc_valid;
- bool weak;
- bool is_gpl_only; /* exported by EXPORT_SYMBOL_GPL */
- char name[];
-};
-
-static struct symbol *symbolhash[SYMBOL_HASH_SIZE];
-
-/* This is based on the hash algorithm from gdbm, via tdb */
-static inline unsigned int tdb_hash(const char *name)
-{
- unsigned value; /* Used to compute the hash value. */
- unsigned i; /* Used to cycle through random values. */
-
- /* Set the initial value from the key size. */
- for (value = 0x238F13AF * strlen(name), i = 0; name[i]; i++)
- value = (value + (((unsigned char *)name)[i] << (i*5 % 24)));
-
- return (1103515243 * value + 12345);
-}
-
-/**
- * Allocate a new symbols for use in the hash of exported symbols or
- * the list of unresolved symbols per module
- **/
-static struct symbol *alloc_symbol(const char *name)
-{
- struct symbol *s = NOFAIL(malloc(sizeof(*s) + strlen(name) + 1));
-
- memset(s, 0, sizeof(*s));
- strcpy(s->name, name);
-
- return s;
-}
-
-/* For the hash of exported symbols */
-static void hash_add_symbol(struct symbol *sym)
-{
- unsigned int hash;
-
- hash = tdb_hash(sym->name) % SYMBOL_HASH_SIZE;
- sym->next = symbolhash[hash];
- symbolhash[hash] = sym;
-}
-
-static void sym_add_unresolved(const char *name, struct module *mod, bool weak)
-{
- struct symbol *sym;
-
- sym = alloc_symbol(name);
- sym->weak = weak;
-
- list_add_tail(&sym->list, &mod->unresolved_symbols);
-}
-
-static struct symbol *sym_find_with_module(const char *name, struct module *mod)
-{
- struct symbol *s;
-
- /* For our purposes, .foo matches foo. PPC64 needs this. */
- if (name[0] == '.')
- name++;
-
- for (s = symbolhash[tdb_hash(name) % SYMBOL_HASH_SIZE]; s; s = s->next) {
- if (strcmp(s->name, name) == 0 && (!mod || s->module == mod))
- return s;
- }
- return NULL;
-}
-
-static struct symbol *find_symbol(const char *name)
-{
- return sym_find_with_module(name, NULL);
-}
-
-struct namespace_list {
- struct list_head list;
- char namespace[];
-};
-
-static bool contains_namespace(struct list_head *head, const char *namespace)
-{
- struct namespace_list *list;
-
- list_for_each_entry(list, head, list) {
- if (!strcmp(list->namespace, namespace))
- return true;
- }
-
- return false;
-}
-
-static void add_namespace(struct list_head *head, const char *namespace)
-{
- struct namespace_list *ns_entry;
-
- if (!contains_namespace(head, namespace)) {
- ns_entry = NOFAIL(malloc(sizeof(*ns_entry) +
- strlen(namespace) + 1));
- strcpy(ns_entry->namespace, namespace);
- list_add_tail(&ns_entry->list, head);
- }
-}
-
-static void *sym_get_data_by_offset(const struct elf_info *info,
- unsigned int secindex, unsigned long offset)
-{
- Elf_Shdr *sechdr = &info->sechdrs[secindex];
-
- return (void *)info->hdr + sechdr->sh_offset + offset;
-}
-
-void *sym_get_data(const struct elf_info *info, const Elf_Sym *sym)
-{
- return sym_get_data_by_offset(info, get_secindex(info, sym),
- sym->st_value);
-}
-
-static const char *sech_name(const struct elf_info *info, Elf_Shdr *sechdr)
-{
- return sym_get_data_by_offset(info, info->secindex_strings,
- sechdr->sh_name);
-}
-
-static const char *sec_name(const struct elf_info *info, unsigned int secindex)
-{
- /*
- * If sym->st_shndx is a special section index, there is no
- * corresponding section header.
- * Return "" if the index is out of range of info->sechdrs[] array.
- */
- if (secindex >= info->num_sections)
- return "";
-
- return sech_name(info, &info->sechdrs[secindex]);
-}
-
-#define strstarts(str, prefix) (strncmp(str, prefix, strlen(prefix)) == 0)
-
-static void sym_update_namespace(const char *symname, const char *namespace)
-{
- struct symbol *s = find_symbol(symname);
-
- /*
- * That symbol should have been created earlier and thus this is
- * actually an assertion.
- */
- if (!s) {
- error("Could not update namespace(%s) for symbol %s\n",
- namespace, symname);
- return;
- }
-
- free(s->namespace);
- s->namespace = namespace[0] ? NOFAIL(strdup(namespace)) : NULL;
-}
-
-static struct symbol *sym_add_exported(const char *name, struct module *mod,
- bool gpl_only)
-{
- struct symbol *s = find_symbol(name);
-
- if (s && (!external_module || s->module->is_vmlinux || s->module == mod)) {
- error("%s: '%s' exported twice. Previous export was in %s%s\n",
- mod->name, name, s->module->name,
- s->module->is_vmlinux ? "" : ".ko");
- }
-
- s = alloc_symbol(name);
- s->module = mod;
- s->is_gpl_only = gpl_only;
- list_add_tail(&s->list, &mod->exported_symbols);
- hash_add_symbol(s);
-
- return s;
-}
-
-static void sym_set_crc(struct symbol *sym, unsigned int crc)
-{
- sym->crc = crc;
- sym->crc_valid = true;
-}
-
-static void *grab_file(const char *filename, size_t *size)
-{
- struct stat st;
- void *map = MAP_FAILED;
- int fd;
-
- fd = open(filename, O_RDONLY);
- if (fd < 0)
- return NULL;
- if (fstat(fd, &st))
- goto failed;
-
- *size = st.st_size;
- map = mmap(NULL, *size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
-
-failed:
- close(fd);
- if (map == MAP_FAILED)
- return NULL;
- return map;
-}
-
-static void release_file(void *file, size_t size)
-{
- munmap(file, size);
-}
-
-static int parse_elf(struct elf_info *info, const char *filename)
-{
- unsigned int i;
- Elf_Ehdr *hdr;
- Elf_Shdr *sechdrs;
- Elf_Sym *sym;
- const char *secstrings;
- unsigned int symtab_idx = ~0U, symtab_shndx_idx = ~0U;
-
- hdr = grab_file(filename, &info->size);
- if (!hdr) {
- if (ignore_missing_files) {
- fprintf(stderr, "%s: %s (ignored)\n", filename,
- strerror(errno));
- return 0;
- }
- perror(filename);
- exit(1);
- }
- info->hdr = hdr;
- if (info->size < sizeof(*hdr)) {
- /* file too small, assume this is an empty .o file */
- return 0;
- }
- /* Is this a valid ELF file? */
- if ((hdr->e_ident[EI_MAG0] != ELFMAG0) ||
- (hdr->e_ident[EI_MAG1] != ELFMAG1) ||
- (hdr->e_ident[EI_MAG2] != ELFMAG2) ||
- (hdr->e_ident[EI_MAG3] != ELFMAG3)) {
- /* Not an ELF file - silently ignore it */
- return 0;
- }
- /* Fix endianness in ELF header */
- hdr->e_type = TO_NATIVE(hdr->e_type);
- hdr->e_machine = TO_NATIVE(hdr->e_machine);
- hdr->e_version = TO_NATIVE(hdr->e_version);
- hdr->e_entry = TO_NATIVE(hdr->e_entry);
- hdr->e_phoff = TO_NATIVE(hdr->e_phoff);
- hdr->e_shoff = TO_NATIVE(hdr->e_shoff);
- hdr->e_flags = TO_NATIVE(hdr->e_flags);
- hdr->e_ehsize = TO_NATIVE(hdr->e_ehsize);
- hdr->e_phentsize = TO_NATIVE(hdr->e_phentsize);
- hdr->e_phnum = TO_NATIVE(hdr->e_phnum);
- hdr->e_shentsize = TO_NATIVE(hdr->e_shentsize);
- hdr->e_shnum = TO_NATIVE(hdr->e_shnum);
- hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx);
- sechdrs = (void *)hdr + hdr->e_shoff;
- info->sechdrs = sechdrs;
-
- /* modpost only works for relocatable objects */
- if (hdr->e_type != ET_REL)
- fatal("%s: not relocatable object.", filename);
-
- /* Check if file offset is correct */
- if (hdr->e_shoff > info->size) {
- fatal("section header offset=%lu in file '%s' is bigger than filesize=%zu\n",
- (unsigned long)hdr->e_shoff, filename, info->size);
- return 0;
- }
-
- if (hdr->e_shnum == SHN_UNDEF) {
- /*
- * There are more than 64k sections,
- * read count from .sh_size.
- */
- info->num_sections = TO_NATIVE(sechdrs[0].sh_size);
- }
- else {
- info->num_sections = hdr->e_shnum;
- }
- if (hdr->e_shstrndx == SHN_XINDEX) {
- info->secindex_strings = TO_NATIVE(sechdrs[0].sh_link);
- }
- else {
- info->secindex_strings = hdr->e_shstrndx;
- }
-
- /* Fix endianness in section headers */
- for (i = 0; i < info->num_sections; i++) {
- sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name);
- sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type);
- sechdrs[i].sh_flags = TO_NATIVE(sechdrs[i].sh_flags);
- sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr);
- sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset);
- sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size);
- sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link);
- sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info);
- sechdrs[i].sh_addralign = TO_NATIVE(sechdrs[i].sh_addralign);
- sechdrs[i].sh_entsize = TO_NATIVE(sechdrs[i].sh_entsize);
- }
- /* Find symbol table. */
- secstrings = (void *)hdr + sechdrs[info->secindex_strings].sh_offset;
- for (i = 1; i < info->num_sections; i++) {
- const char *secname;
- int nobits = sechdrs[i].sh_type == SHT_NOBITS;
-
- if (!nobits && sechdrs[i].sh_offset > info->size) {
- fatal("%s is truncated. sechdrs[i].sh_offset=%lu > "
- "sizeof(*hrd)=%zu\n", filename,
- (unsigned long)sechdrs[i].sh_offset,
- sizeof(*hdr));
- return 0;
- }
- secname = secstrings + sechdrs[i].sh_name;
- if (strcmp(secname, ".modinfo") == 0) {
- if (nobits)
- fatal("%s has NOBITS .modinfo\n", filename);
- info->modinfo = (void *)hdr + sechdrs[i].sh_offset;
- info->modinfo_len = sechdrs[i].sh_size;
- }
-
- if (sechdrs[i].sh_type == SHT_SYMTAB) {
- unsigned int sh_link_idx;
- symtab_idx = i;
- info->symtab_start = (void *)hdr +
- sechdrs[i].sh_offset;
- info->symtab_stop = (void *)hdr +
- sechdrs[i].sh_offset + sechdrs[i].sh_size;
- sh_link_idx = sechdrs[i].sh_link;
- info->strtab = (void *)hdr +
- sechdrs[sh_link_idx].sh_offset;
- }
-
- /* 32bit section no. table? ("more than 64k sections") */
- if (sechdrs[i].sh_type == SHT_SYMTAB_SHNDX) {
- symtab_shndx_idx = i;
- info->symtab_shndx_start = (void *)hdr +
- sechdrs[i].sh_offset;
- info->symtab_shndx_stop = (void *)hdr +
- sechdrs[i].sh_offset + sechdrs[i].sh_size;
- }
- }
- if (!info->symtab_start)
- fatal("%s has no symtab?\n", filename);
-
- /* Fix endianness in symbols */
- for (sym = info->symtab_start; sym < info->symtab_stop; sym++) {
- sym->st_shndx = TO_NATIVE(sym->st_shndx);
- sym->st_name = TO_NATIVE(sym->st_name);
- sym->st_value = TO_NATIVE(sym->st_value);
- sym->st_size = TO_NATIVE(sym->st_size);
- }
-
- if (symtab_shndx_idx != ~0U) {
- Elf32_Word *p;
- if (symtab_idx != sechdrs[symtab_shndx_idx].sh_link)
- fatal("%s: SYMTAB_SHNDX has bad sh_link: %u!=%u\n",
- filename, sechdrs[symtab_shndx_idx].sh_link,
- symtab_idx);
- /* Fix endianness */
- for (p = info->symtab_shndx_start; p < info->symtab_shndx_stop;
- p++)
- *p = TO_NATIVE(*p);
- }
-
- return 1;
-}
-
-static void parse_elf_finish(struct elf_info *info)
-{
- release_file(info->hdr, info->size);
-}
-
-static int ignore_undef_symbol(struct elf_info *info, const char *symname)
-{
- /* ignore __this_module, it will be resolved shortly */
- if (strcmp(symname, "__this_module") == 0)
- return 1;
- /* ignore global offset table */
- if (strcmp(symname, "_GLOBAL_OFFSET_TABLE_") == 0)
- return 1;
- if (info->hdr->e_machine == EM_PPC)
- /* Special register function linked on all modules during final link of .ko */
- if (strstarts(symname, "_restgpr_") ||
- strstarts(symname, "_savegpr_") ||
- strstarts(symname, "_rest32gpr_") ||
- strstarts(symname, "_save32gpr_") ||
- strstarts(symname, "_restvr_") ||
- strstarts(symname, "_savevr_"))
- return 1;
- if (info->hdr->e_machine == EM_PPC64)
- /* Special register function linked on all modules during final link of .ko */
- if (strstarts(symname, "_restgpr0_") ||
- strstarts(symname, "_savegpr0_") ||
- strstarts(symname, "_restvr_") ||
- strstarts(symname, "_savevr_") ||
- strcmp(symname, ".TOC.") == 0)
- return 1;
-
- if (info->hdr->e_machine == EM_S390)
- /* Expoline thunks are linked on all kernel modules during final link of .ko */
- if (strstarts(symname, "__s390_indirect_jump_r"))
- return 1;
- /* Do not ignore this symbol */
- return 0;
-}
-
-static void handle_symbol(struct module *mod, struct elf_info *info,
- const Elf_Sym *sym, const char *symname)
-{
- switch (sym->st_shndx) {
- case SHN_COMMON:
- if (strstarts(symname, "__gnu_lto_")) {
- /* Should warn here, but modpost runs before the linker */
- } else
- warn("\"%s\" [%s] is COMMON symbol\n", symname, mod->name);
- break;
- case SHN_UNDEF:
- /* undefined symbol */
- if (ELF_ST_BIND(sym->st_info) != STB_GLOBAL &&
- ELF_ST_BIND(sym->st_info) != STB_WEAK)
- break;
- if (ignore_undef_symbol(info, symname))
- break;
- if (info->hdr->e_machine == EM_SPARC ||
- info->hdr->e_machine == EM_SPARCV9) {
- /* Ignore register directives. */
- if (ELF_ST_TYPE(sym->st_info) == STT_SPARC_REGISTER)
- break;
- if (symname[0] == '.') {
- char *munged = NOFAIL(strdup(symname));
- munged[0] = '_';
- munged[1] = toupper(munged[1]);
- symname = munged;
- }
- }
-
- sym_add_unresolved(symname, mod,
- ELF_ST_BIND(sym->st_info) == STB_WEAK);
- break;
- default:
- /* All exported symbols */
- if (strstarts(symname, "__ksymtab_")) {
- const char *name, *secname;
-
- name = symname + strlen("__ksymtab_");
- secname = sec_name(info, get_secindex(info, sym));
-
- if (strstarts(secname, "___ksymtab_gpl+"))
- sym_add_exported(name, mod, true);
- else if (strstarts(secname, "___ksymtab+"))
- sym_add_exported(name, mod, false);
- }
- if (strcmp(symname, "init_module") == 0)
- mod->has_init = true;
- if (strcmp(symname, "cleanup_module") == 0)
- mod->has_cleanup = true;
- break;
- }
-}
-
-/**
- * Parse tag=value strings from .modinfo section
- **/
-static char *next_string(char *string, unsigned long *secsize)
-{
- /* Skip non-zero chars */
- while (string[0]) {
- string++;
- if ((*secsize)-- <= 1)
- return NULL;
- }
-
- /* Skip any zero padding. */
- while (!string[0]) {
- string++;
- if ((*secsize)-- <= 1)
- return NULL;
- }
- return string;
-}
-
-static char *get_next_modinfo(struct elf_info *info, const char *tag,
- char *prev)
-{
- char *p;
- unsigned int taglen = strlen(tag);
- char *modinfo = info->modinfo;
- unsigned long size = info->modinfo_len;
-
- if (prev) {
- size -= prev - modinfo;
- modinfo = next_string(prev, &size);
- }
-
- for (p = modinfo; p; p = next_string(p, &size)) {
- if (strncmp(p, tag, taglen) == 0 && p[taglen] == '=')
- return p + taglen + 1;
- }
- return NULL;
-}
-
-static char *get_modinfo(struct elf_info *info, const char *tag)
-
-{
- return get_next_modinfo(info, tag, NULL);
-}
-
-static const char *sym_name(struct elf_info *elf, Elf_Sym *sym)
-{
- if (sym)
- return elf->strtab + sym->st_name;
- else
- return "(unknown)";
-}
-
-/*
- * Check whether the 'string' argument matches one of the 'patterns',
- * an array of shell wildcard patterns (glob).
- *
- * Return true is there is a match.
- */
-static bool match(const char *string, const char *const patterns[])
-{
- const char *pattern;
-
- while ((pattern = *patterns++)) {
- if (!fnmatch(pattern, string, 0))
- return true;
- }
-
- return false;
-}
-
-/* useful to pass patterns to match() directly */
-#define PATTERNS(...) \
- ({ \
- static const char *const patterns[] = {__VA_ARGS__, NULL}; \
- patterns; \
- })
-
-/* sections that we do not want to do full section mismatch check on */
-static const char *const section_white_list[] =
-{
- ".comment*",
- ".debug*",
- ".zdebug*", /* Compressed debug sections. */
- ".GCC.command.line", /* record-gcc-switches */
- ".mdebug*", /* alpha, score, mips etc. */
- ".pdr", /* alpha, score, mips etc. */
- ".stab*",
- ".note*",
- ".got*",
- ".toc*",
- ".xt.prop", /* xtensa */
- ".xt.lit", /* xtensa */
- ".arcextmap*", /* arc */
- ".gnu.linkonce.arcext*", /* arc : modules */
- ".cmem*", /* EZchip */
- ".fmt_slot*", /* EZchip */
- ".gnu.lto*",
- ".discard.*",
- NULL
-};
-
-/*
- * This is used to find sections missing the SHF_ALLOC flag.
- * The cause of this is often a section specified in assembler
- * without "ax" / "aw".
- */
-static void check_section(const char *modname, struct elf_info *elf,
- Elf_Shdr *sechdr)
-{
- const char *sec = sech_name(elf, sechdr);
-
- if (sechdr->sh_type == SHT_PROGBITS &&
- !(sechdr->sh_flags & SHF_ALLOC) &&
- !match(sec, section_white_list)) {
- warn("%s (%s): unexpected non-allocatable section.\n"
- "Did you forget to use \"ax\"/\"aw\" in a .S file?\n"
- "Note that for example <linux/init.h> contains\n"
- "section definitions for use in .S files.\n\n",
- modname, sec);
- }
-}
-
-
-
-#define ALL_INIT_DATA_SECTIONS \
- ".init.setup", ".init.rodata", ".meminit.rodata", \
- ".init.data", ".meminit.data"
-#define ALL_EXIT_DATA_SECTIONS \
- ".exit.data", ".memexit.data"
-
-#define ALL_INIT_TEXT_SECTIONS \
- ".init.text", ".meminit.text"
-#define ALL_EXIT_TEXT_SECTIONS \
- ".exit.text", ".memexit.text"
-
-#define ALL_PCI_INIT_SECTIONS \
- ".pci_fixup_early", ".pci_fixup_header", ".pci_fixup_final", \
- ".pci_fixup_enable", ".pci_fixup_resume", \
- ".pci_fixup_resume_early", ".pci_fixup_suspend"
-
-#define ALL_XXXINIT_SECTIONS MEM_INIT_SECTIONS
-#define ALL_XXXEXIT_SECTIONS MEM_EXIT_SECTIONS
-
-#define ALL_INIT_SECTIONS INIT_SECTIONS, ALL_XXXINIT_SECTIONS
-#define ALL_EXIT_SECTIONS EXIT_SECTIONS, ALL_XXXEXIT_SECTIONS
-
-#define DATA_SECTIONS ".data", ".data.rel"
-#define TEXT_SECTIONS ".text", ".text.unlikely", ".sched.text", \
- ".kprobes.text", ".cpuidle.text", ".noinstr.text"
-#define OTHER_TEXT_SECTIONS ".ref.text", ".head.text", ".spinlock.text", \
- ".fixup", ".entry.text", ".exception.text", ".text.*", \
- ".coldtext", ".softirqentry.text"
-
-#define INIT_SECTIONS ".init.*"
-#define MEM_INIT_SECTIONS ".meminit.*"
-
-#define EXIT_SECTIONS ".exit.*"
-#define MEM_EXIT_SECTIONS ".memexit.*"
-
-#define ALL_TEXT_SECTIONS ALL_INIT_TEXT_SECTIONS, ALL_EXIT_TEXT_SECTIONS, \
- TEXT_SECTIONS, OTHER_TEXT_SECTIONS
-
-/* init data sections */
-static const char *const init_data_sections[] =
- { ALL_INIT_DATA_SECTIONS, NULL };
-
-/* all init sections */
-static const char *const init_sections[] = { ALL_INIT_SECTIONS, NULL };
-
-/* all text sections */
-static const char *const text_sections[] = { ALL_TEXT_SECTIONS, NULL };
-
-/* data section */
-static const char *const data_sections[] = { DATA_SECTIONS, NULL };
-
-static const char *const head_sections[] = { ".head.text*", NULL };
-static const char *const linker_symbols[] =
- { "__init_begin", "_sinittext", "_einittext", NULL };
-static const char *const optim_symbols[] = { "*.constprop.*", NULL };
-
-enum mismatch {
- TEXT_TO_ANY_INIT,
- DATA_TO_ANY_INIT,
- TEXT_TO_ANY_EXIT,
- DATA_TO_ANY_EXIT,
- XXXINIT_TO_SOME_INIT,
- XXXEXIT_TO_SOME_EXIT,
- ANY_INIT_TO_ANY_EXIT,
- ANY_EXIT_TO_ANY_INIT,
- EXPORT_TO_INIT_EXIT,
- EXTABLE_TO_NON_TEXT,
-};
-
-/**
- * Describe how to match sections on different criteria:
- *
- * @fromsec: Array of sections to be matched.
- *
- * @bad_tosec: Relocations applied to a section in @fromsec to a section in
- * this array is forbidden (black-list). Can be empty.
- *
- * @good_tosec: Relocations applied to a section in @fromsec must be
- * targeting sections in this array (white-list). Can be empty.
- *
- * @mismatch: Type of mismatch.
- *
- * @handler: Specific handler to call when a match is found. If NULL,
- * default_mismatch_handler() will be called.
- *
- */
-struct sectioncheck {
- const char *fromsec[20];
- const char *bad_tosec[20];
- const char *good_tosec[20];
- enum mismatch mismatch;
- void (*handler)(const char *modname, struct elf_info *elf,
- const struct sectioncheck* const mismatch,
- Elf_Rela *r, Elf_Sym *sym, const char *fromsec);
-
-};
-
-static void extable_mismatch_handler(const char *modname, struct elf_info *elf,
- const struct sectioncheck* const mismatch,
- Elf_Rela *r, Elf_Sym *sym,
- const char *fromsec);
-
-static const struct sectioncheck sectioncheck[] = {
-/* Do not reference init/exit code/data from
- * normal code and data
- */
-{
- .fromsec = { TEXT_SECTIONS, NULL },
- .bad_tosec = { ALL_INIT_SECTIONS, NULL },
- .mismatch = TEXT_TO_ANY_INIT,
-},
-{
- .fromsec = { DATA_SECTIONS, NULL },
- .bad_tosec = { ALL_XXXINIT_SECTIONS, NULL },
- .mismatch = DATA_TO_ANY_INIT,
-},
-{
- .fromsec = { DATA_SECTIONS, NULL },
- .bad_tosec = { INIT_SECTIONS, NULL },
- .mismatch = DATA_TO_ANY_INIT,
-},
-{
- .fromsec = { TEXT_SECTIONS, NULL },
- .bad_tosec = { ALL_EXIT_SECTIONS, NULL },
- .mismatch = TEXT_TO_ANY_EXIT,
-},
-{
- .fromsec = { DATA_SECTIONS, NULL },
- .bad_tosec = { ALL_EXIT_SECTIONS, NULL },
- .mismatch = DATA_TO_ANY_EXIT,
-},
-/* Do not reference init code/data from meminit code/data */
-{
- .fromsec = { ALL_XXXINIT_SECTIONS, NULL },
- .bad_tosec = { INIT_SECTIONS, NULL },
- .mismatch = XXXINIT_TO_SOME_INIT,
-},
-/* Do not reference exit code/data from memexit code/data */
-{
- .fromsec = { ALL_XXXEXIT_SECTIONS, NULL },
- .bad_tosec = { EXIT_SECTIONS, NULL },
- .mismatch = XXXEXIT_TO_SOME_EXIT,
-},
-/* Do not use exit code/data from init code */
-{
- .fromsec = { ALL_INIT_SECTIONS, NULL },
- .bad_tosec = { ALL_EXIT_SECTIONS, NULL },
- .mismatch = ANY_INIT_TO_ANY_EXIT,
-},
-/* Do not use init code/data from exit code */
-{
- .fromsec = { ALL_EXIT_SECTIONS, NULL },
- .bad_tosec = { ALL_INIT_SECTIONS, NULL },
- .mismatch = ANY_EXIT_TO_ANY_INIT,
-},
-{
- .fromsec = { ALL_PCI_INIT_SECTIONS, NULL },
- .bad_tosec = { INIT_SECTIONS, NULL },
- .mismatch = ANY_INIT_TO_ANY_EXIT,
-},
-/* Do not export init/exit functions or data */
-{
- .fromsec = { "___ksymtab*", NULL },
- .bad_tosec = { INIT_SECTIONS, EXIT_SECTIONS, NULL },
- .mismatch = EXPORT_TO_INIT_EXIT,
-},
-{
- .fromsec = { "__ex_table", NULL },
- /* If you're adding any new black-listed sections in here, consider
- * adding a special 'printer' for them in scripts/check_extable.
- */
- .bad_tosec = { ".altinstr_replacement", NULL },
- .good_tosec = {ALL_TEXT_SECTIONS , NULL},
- .mismatch = EXTABLE_TO_NON_TEXT,
- .handler = extable_mismatch_handler,
-}
-};
-
-static const struct sectioncheck *section_mismatch(
- const char *fromsec, const char *tosec)
-{
- int i;
-
- /*
- * The target section could be the SHT_NUL section when we're
- * handling relocations to un-resolved symbols, trying to match it
- * doesn't make much sense and causes build failures on parisc
- * architectures.
- */
- if (*tosec == '\0')
- return NULL;
-
- for (i = 0; i < ARRAY_SIZE(sectioncheck); i++) {
- const struct sectioncheck *check = §ioncheck[i];
-
- if (match(fromsec, check->fromsec)) {
- if (check->bad_tosec[0] && match(tosec, check->bad_tosec))
- return check;
- if (check->good_tosec[0] && !match(tosec, check->good_tosec))
- return check;
- }
- }
- return NULL;
-}
-
-/**
- * Whitelist to allow certain references to pass with no warning.
- *
- * Pattern 1:
- * If a module parameter is declared __initdata and permissions=0
- * then this is legal despite the warning generated.
- * We cannot see value of permissions here, so just ignore
- * this pattern.
- * The pattern is identified by:
- * tosec = .init.data
- * fromsec = .data*
- * atsym =__param*
- *
- * Pattern 1a:
- * module_param_call() ops can refer to __init set function if permissions=0
- * The pattern is identified by:
- * tosec = .init.text
- * fromsec = .data*
- * atsym = __param_ops_*
- *
- * Pattern 3:
- * Whitelist all references from .head.text to any init section
- *
- * Pattern 4:
- * Some symbols belong to init section but still it is ok to reference
- * these from non-init sections as these symbols don't have any memory
- * allocated for them and symbol address and value are same. So even
- * if init section is freed, its ok to reference those symbols.
- * For ex. symbols marking the init section boundaries.
- * This pattern is identified by
- * refsymname = __init_begin, _sinittext, _einittext
- *
- * Pattern 5:
- * GCC may optimize static inlines when fed constant arg(s) resulting
- * in functions like cpumask_empty() -- generating an associated symbol
- * cpumask_empty.constprop.3 that appears in the audit. If the const that
- * is passed in comes from __init, like say nmi_ipi_mask, we get a
- * meaningless section warning. May need to add isra symbols too...
- * This pattern is identified by
- * tosec = init section
- * fromsec = text section
- * refsymname = *.constprop.*
- *
- * Pattern 6:
- * Hide section mismatch warnings for ELF local symbols. The goal
- * is to eliminate false positive modpost warnings caused by
- * compiler-generated ELF local symbol names such as ".LANCHOR1".
- * Autogenerated symbol names bypass modpost's "Pattern 2"
- * whitelisting, which relies on pattern-matching against symbol
- * names to work. (One situation where gcc can autogenerate ELF
- * local symbols is when "-fsection-anchors" is used.)
- **/
-static int secref_whitelist(const struct sectioncheck *mismatch,
- const char *fromsec, const char *fromsym,
- const char *tosec, const char *tosym)
-{
- /* Check for pattern 1 */
- if (match(tosec, init_data_sections) &&
- match(fromsec, data_sections) &&
- strstarts(fromsym, "__param"))
- return 0;
-
- /* Check for pattern 1a */
- if (strcmp(tosec, ".init.text") == 0 &&
- match(fromsec, data_sections) &&
- strstarts(fromsym, "__param_ops_"))
- return 0;
-
- /* symbols in data sections that may refer to any init/exit sections */
- if (match(fromsec, PATTERNS(DATA_SECTIONS)) &&
- match(tosec, PATTERNS(ALL_INIT_SECTIONS, ALL_EXIT_SECTIONS)) &&
- match(fromsym, PATTERNS("*_template", // scsi uses *_template a lot
- "*_timer", // arm uses ops structures named _timer a lot
- "*_sht", // scsi also used *_sht to some extent
- "*_ops",
- "*_probe",
- "*_probe_one",
- "*_console")))
- return 0;
-
- /* symbols in data sections that may refer to meminit/exit sections */
- if (match(fromsec, PATTERNS(DATA_SECTIONS)) &&
- match(tosec, PATTERNS(ALL_XXXINIT_SECTIONS, ALL_EXIT_SECTIONS)) &&
- match(fromsym, PATTERNS("*driver")))
- return 0;
-
- /* Check for pattern 3 */
- if (match(fromsec, head_sections) &&
- match(tosec, init_sections))
- return 0;
-
- /* Check for pattern 4 */
- if (match(tosym, linker_symbols))
- return 0;
-
- /* Check for pattern 5 */
- if (match(fromsec, text_sections) &&
- match(tosec, init_sections) &&
- match(fromsym, optim_symbols))
- return 0;
-
- /* Check for pattern 6 */
- if (strstarts(fromsym, ".L"))
- return 0;
-
- return 1;
-}
-
-static inline int is_arm_mapping_symbol(const char *str)
-{
- return str[0] == '$' &&
- (str[1] == 'a' || str[1] == 'd' || str[1] == 't' || str[1] == 'x')
- && (str[2] == '\0' || str[2] == '.');
-}
-
-/*
- * If there's no name there, ignore it; likewise, ignore it if it's
- * one of the magic symbols emitted used by current ARM tools.
- *
- * Otherwise if find_symbols_between() returns those symbols, they'll
- * fail the whitelist tests and cause lots of false alarms ... fixable
- * only by merging __exit and __init sections into __text, bloating
- * the kernel (which is especially evil on embedded platforms).
- */
-static inline int is_valid_name(struct elf_info *elf, Elf_Sym *sym)
-{
- const char *name = elf->strtab + sym->st_name;
-
- if (!name || !strlen(name))
- return 0;
- return !is_arm_mapping_symbol(name);
-}
-
-/**
- * Find symbol based on relocation record info.
- * In some cases the symbol supplied is a valid symbol so
- * return refsym. If st_name != 0 we assume this is a valid symbol.
- * In other cases the symbol needs to be looked up in the symbol table
- * based on section and address.
- * **/
-static Elf_Sym *find_elf_symbol(struct elf_info *elf, Elf64_Sword addr,
- Elf_Sym *relsym)
-{
- Elf_Sym *sym;
- Elf_Sym *near = NULL;
- Elf64_Sword distance = 20;
- Elf64_Sword d;
- unsigned int relsym_secindex;
-
- if (relsym->st_name != 0)
- return relsym;
-
- relsym_secindex = get_secindex(elf, relsym);
- for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) {
- if (get_secindex(elf, sym) != relsym_secindex)
- continue;
- if (ELF_ST_TYPE(sym->st_info) == STT_SECTION)
- continue;
- if (!is_valid_name(elf, sym))
- continue;
- if (sym->st_value == addr)
- return sym;
- /* Find a symbol nearby - addr are maybe negative */
- d = sym->st_value - addr;
- if (d < 0)
- d = addr - sym->st_value;
- if (d < distance) {
- distance = d;
- near = sym;
- }
- }
- /* We need a close match */
- if (distance < 20)
- return near;
- else
- return NULL;
-}
-
-/*
- * Find symbols before or equal addr and after addr - in the section sec.
- * If we find two symbols with equal offset prefer one with a valid name.
- * The ELF format may have a better way to detect what type of symbol
- * it is, but this works for now.
- **/
-static Elf_Sym *find_elf_symbol2(struct elf_info *elf, Elf_Addr addr,
- const char *sec)
-{
- Elf_Sym *sym;
- Elf_Sym *near = NULL;
- Elf_Addr distance = ~0;
-
- for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) {
- const char *symsec;
-
- if (is_shndx_special(sym->st_shndx))
- continue;
- symsec = sec_name(elf, get_secindex(elf, sym));
- if (strcmp(symsec, sec) != 0)
- continue;
- if (!is_valid_name(elf, sym))
- continue;
- if (sym->st_value <= addr && addr - sym->st_value <= distance) {
- distance = addr - sym->st_value;
- near = sym;
- }
- }
- return near;
-}
-
-static int is_function(Elf_Sym *sym)
-{
- if (sym)
- return ELF_ST_TYPE(sym->st_info) == STT_FUNC;
- else
- return -1;
-}
-
-static inline void get_pretty_name(int is_func, const char** name, const char** name_p)
-{
- switch (is_func) {
- case 0: *name = "variable"; *name_p = ""; break;
- case 1: *name = "function"; *name_p = "()"; break;
- default: *name = "(unknown reference)"; *name_p = ""; break;
- }
-}
-
-/*
- * Print a warning about a section mismatch.
- * Try to find symbols near it so user can find it.
- * Check whitelist before warning - it may be a false positive.
- */
-static void report_sec_mismatch(const char *modname,
- const struct sectioncheck *mismatch,
- const char *fromsec,
- const char *fromsym,
- const char *tosec, const char *tosym)
-{
- sec_mismatch_count++;
-
- switch (mismatch->mismatch) {
- case TEXT_TO_ANY_INIT:
- case DATA_TO_ANY_INIT:
- case TEXT_TO_ANY_EXIT:
- case DATA_TO_ANY_EXIT:
- case XXXINIT_TO_SOME_INIT:
- case XXXEXIT_TO_SOME_EXIT:
- case ANY_INIT_TO_ANY_EXIT:
- case ANY_EXIT_TO_ANY_INIT:
- warn("%s: section mismatch in reference: %s (section: %s) -> %s (section: %s)\n",
- modname, fromsym, fromsec, tosym, tosec);
- break;
- case EXPORT_TO_INIT_EXIT:
- warn("%s: EXPORT_SYMBOL used for init/exit symbol: %s (section: %s)\n",
- modname, tosym, tosec);
- break;
- case EXTABLE_TO_NON_TEXT:
- fatal("There's a special handler for this mismatch type, we should never get here.\n");
- break;
- }
-}
-
-static void default_mismatch_handler(const char *modname, struct elf_info *elf,
- const struct sectioncheck* const mismatch,
- Elf_Rela *r, Elf_Sym *sym, const char *fromsec)
-{
- const char *tosec;
- Elf_Sym *to;
- Elf_Sym *from;
- const char *tosym;
- const char *fromsym;
-
- from = find_elf_symbol2(elf, r->r_offset, fromsec);
- fromsym = sym_name(elf, from);
-
- tosec = sec_name(elf, get_secindex(elf, sym));
- to = find_elf_symbol(elf, r->r_addend, sym);
- tosym = sym_name(elf, to);
-
- /* check whitelist - we may ignore it */
- if (secref_whitelist(mismatch,
- fromsec, fromsym, tosec, tosym)) {
- report_sec_mismatch(modname, mismatch,
- fromsec, fromsym, tosec, tosym);
- }
-}
-
-static int is_executable_section(struct elf_info* elf, unsigned int section_index)
-{
- if (section_index > elf->num_sections)
- fatal("section_index is outside elf->num_sections!\n");
-
- return ((elf->sechdrs[section_index].sh_flags & SHF_EXECINSTR) == SHF_EXECINSTR);
-}
-
-/*
- * We rely on a gross hack in section_rel[a]() calling find_extable_entry_size()
- * to know the sizeof(struct exception_table_entry) for the target architecture.
- */
-static unsigned int extable_entry_size = 0;
-static void find_extable_entry_size(const char* const sec, const Elf_Rela* r)
-{
- /*
- * If we're currently checking the second relocation within __ex_table,
- * that relocation offset tells us the offsetof(struct
- * exception_table_entry, fixup) which is equal to sizeof(struct
- * exception_table_entry) divided by two. We use that to our advantage
- * since there's no portable way to get that size as every architecture
- * seems to go with different sized types. Not pretty but better than
- * hard-coding the size for every architecture..
- */
- if (!extable_entry_size)
- extable_entry_size = r->r_offset * 2;
-}
-
-static inline bool is_extable_fault_address(Elf_Rela *r)
-{
- /*
- * extable_entry_size is only discovered after we've handled the
- * _second_ relocation in __ex_table, so only abort when we're not
- * handling the first reloc and extable_entry_size is zero.
- */
- if (r->r_offset && extable_entry_size == 0)
- fatal("extable_entry size hasn't been discovered!\n");
-
- return ((r->r_offset == 0) ||
- (r->r_offset % extable_entry_size == 0));
-}
-
-#define is_second_extable_reloc(Start, Cur, Sec) \
- (((Cur) == (Start) + 1) && (strcmp("__ex_table", (Sec)) == 0))
-
-static void report_extable_warnings(const char* modname, struct elf_info* elf,
- const struct sectioncheck* const mismatch,
- Elf_Rela* r, Elf_Sym* sym,
- const char* fromsec, const char* tosec)
-{
- Elf_Sym* fromsym = find_elf_symbol2(elf, r->r_offset, fromsec);
- const char* fromsym_name = sym_name(elf, fromsym);
- Elf_Sym* tosym = find_elf_symbol(elf, r->r_addend, sym);
- const char* tosym_name = sym_name(elf, tosym);
- const char* from_pretty_name;
- const char* from_pretty_name_p;
- const char* to_pretty_name;
- const char* to_pretty_name_p;
-
- get_pretty_name(is_function(fromsym),
- &from_pretty_name, &from_pretty_name_p);
- get_pretty_name(is_function(tosym),
- &to_pretty_name, &to_pretty_name_p);
-
- warn("%s(%s+0x%lx): Section mismatch in reference"
- " from the %s %s%s to the %s %s:%s%s\n",
- modname, fromsec, (long)r->r_offset, from_pretty_name,
- fromsym_name, from_pretty_name_p,
- to_pretty_name, tosec, tosym_name, to_pretty_name_p);
-
- if (!match(tosec, mismatch->bad_tosec) &&
- is_executable_section(elf, get_secindex(elf, sym)))
- fprintf(stderr,
- "The relocation at %s+0x%lx references\n"
- "section \"%s\" which is not in the list of\n"
- "authorized sections. If you're adding a new section\n"
- "and/or if this reference is valid, add \"%s\" to the\n"
- "list of authorized sections to jump to on fault.\n"
- "This can be achieved by adding \"%s\" to \n"
- "OTHER_TEXT_SECTIONS in scripts/mod/modpost.c.\n",
- fromsec, (long)r->r_offset, tosec, tosec, tosec);
-}
-
-static void extable_mismatch_handler(const char* modname, struct elf_info *elf,
- const struct sectioncheck* const mismatch,
- Elf_Rela* r, Elf_Sym* sym,
- const char *fromsec)
-{
- const char* tosec = sec_name(elf, get_secindex(elf, sym));
-
- sec_mismatch_count++;
-
- report_extable_warnings(modname, elf, mismatch, r, sym, fromsec, tosec);
-
- if (match(tosec, mismatch->bad_tosec))
- fatal("The relocation at %s+0x%lx references\n"
- "section \"%s\" which is black-listed.\n"
- "Something is seriously wrong and should be fixed.\n"
- "You might get more information about where this is\n"
- "coming from by using scripts/check_extable.sh %s\n",
- fromsec, (long)r->r_offset, tosec, modname);
- else if (!is_executable_section(elf, get_secindex(elf, sym))) {
- if (is_extable_fault_address(r))
- fatal("The relocation at %s+0x%lx references\n"
- "section \"%s\" which is not executable, IOW\n"
- "it is not possible for the kernel to fault\n"
- "at that address. Something is seriously wrong\n"
- "and should be fixed.\n",
- fromsec, (long)r->r_offset, tosec);
- else
- fatal("The relocation at %s+0x%lx references\n"
- "section \"%s\" which is not executable, IOW\n"
- "the kernel will fault if it ever tries to\n"
- "jump to it. Something is seriously wrong\n"
- "and should be fixed.\n",
- fromsec, (long)r->r_offset, tosec);
- }
-}
-
-static void check_section_mismatch(const char *modname, struct elf_info *elf,
- Elf_Rela *r, Elf_Sym *sym, const char *fromsec)
-{
- const char *tosec = sec_name(elf, get_secindex(elf, sym));
- const struct sectioncheck *mismatch = section_mismatch(fromsec, tosec);
-
- if (mismatch) {
- if (mismatch->handler)
- mismatch->handler(modname, elf, mismatch,
- r, sym, fromsec);
- else
- default_mismatch_handler(modname, elf, mismatch,
- r, sym, fromsec);
- }
-}
-
-static unsigned int *reloc_location(struct elf_info *elf,
- Elf_Shdr *sechdr, Elf_Rela *r)
-{
- return sym_get_data_by_offset(elf, sechdr->sh_info, r->r_offset);
-}
-
-static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
-{
- unsigned int r_typ = ELF_R_TYPE(r->r_info);
- unsigned int *location = reloc_location(elf, sechdr, r);
-
- switch (r_typ) {
- case R_386_32:
- r->r_addend = TO_NATIVE(*location);
- break;
- case R_386_PC32:
- r->r_addend = TO_NATIVE(*location) + 4;
- break;
- }
- return 0;
-}
-
-#ifndef R_ARM_CALL
-#define R_ARM_CALL 28
-#endif
-#ifndef R_ARM_JUMP24
-#define R_ARM_JUMP24 29
-#endif
-
-#ifndef R_ARM_THM_CALL
-#define R_ARM_THM_CALL 10
-#endif
-#ifndef R_ARM_THM_JUMP24
-#define R_ARM_THM_JUMP24 30
-#endif
-#ifndef R_ARM_THM_JUMP19
-#define R_ARM_THM_JUMP19 51
-#endif
-
-static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
-{
- unsigned int r_typ = ELF_R_TYPE(r->r_info);
-
- switch (r_typ) {
- case R_ARM_ABS32:
- /* From ARM ABI: (S + A) | T */
- r->r_addend = (int)(long)
- (elf->symtab_start + ELF_R_SYM(r->r_info));
- break;
- case R_ARM_PC24:
- case R_ARM_CALL:
- case R_ARM_JUMP24:
- case R_ARM_THM_CALL:
- case R_ARM_THM_JUMP24:
- case R_ARM_THM_JUMP19:
- /* From ARM ABI: ((S + A) | T) - P */
- r->r_addend = (int)(long)(elf->hdr +
- sechdr->sh_offset +
- (r->r_offset - sechdr->sh_addr));
- break;
- default:
- return 1;
- }
- return 0;
-}
-
-static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
-{
- unsigned int r_typ = ELF_R_TYPE(r->r_info);
- unsigned int *location = reloc_location(elf, sechdr, r);
- unsigned int inst;
-
- if (r_typ == R_MIPS_HI16)
- return 1; /* skip this */
- inst = TO_NATIVE(*location);
- switch (r_typ) {
- case R_MIPS_LO16:
- r->r_addend = inst & 0xffff;
- break;
- case R_MIPS_26:
- r->r_addend = (inst & 0x03ffffff) << 2;
- break;
- case R_MIPS_32:
- r->r_addend = inst;
- break;
- }
- return 0;
-}
-
-#ifndef EM_RISCV
-#define EM_RISCV 243
-#endif
-
-#ifndef R_RISCV_SUB32
-#define R_RISCV_SUB32 39
-#endif
-
-static void section_rela(const char *modname, struct elf_info *elf,
- Elf_Shdr *sechdr)
-{
- Elf_Sym *sym;
- Elf_Rela *rela;
- Elf_Rela r;
- unsigned int r_sym;
- const char *fromsec;
-
- Elf_Rela *start = (void *)elf->hdr + sechdr->sh_offset;
- Elf_Rela *stop = (void *)start + sechdr->sh_size;
-
- fromsec = sec_name(elf, sechdr->sh_info);
- /* if from section (name) is know good then skip it */
- if (match(fromsec, section_white_list))
- return;
-
- for (rela = start; rela < stop; rela++) {
- r.r_offset = TO_NATIVE(rela->r_offset);
-#if KERNEL_ELFCLASS == ELFCLASS64
- if (elf->hdr->e_machine == EM_MIPS) {
- unsigned int r_typ;
- r_sym = ELF64_MIPS_R_SYM(rela->r_info);
- r_sym = TO_NATIVE(r_sym);
- r_typ = ELF64_MIPS_R_TYPE(rela->r_info);
- r.r_info = ELF64_R_INFO(r_sym, r_typ);
- } else {
- r.r_info = TO_NATIVE(rela->r_info);
- r_sym = ELF_R_SYM(r.r_info);
- }
-#else
- r.r_info = TO_NATIVE(rela->r_info);
- r_sym = ELF_R_SYM(r.r_info);
-#endif
- r.r_addend = TO_NATIVE(rela->r_addend);
- switch (elf->hdr->e_machine) {
- case EM_RISCV:
- if (!strcmp("__ex_table", fromsec) &&
- ELF_R_TYPE(r.r_info) == R_RISCV_SUB32)
- continue;
- break;
- }
- sym = elf->symtab_start + r_sym;
- /* Skip special sections */
- if (is_shndx_special(sym->st_shndx))
- continue;
- if (is_second_extable_reloc(start, rela, fromsec))
- find_extable_entry_size(fromsec, &r);
- check_section_mismatch(modname, elf, &r, sym, fromsec);
- }
-}
-
-static void section_rel(const char *modname, struct elf_info *elf,
- Elf_Shdr *sechdr)
-{
- Elf_Sym *sym;
- Elf_Rel *rel;
- Elf_Rela r;
- unsigned int r_sym;
- const char *fromsec;
-
- Elf_Rel *start = (void *)elf->hdr + sechdr->sh_offset;
- Elf_Rel *stop = (void *)start + sechdr->sh_size;
-
- fromsec = sec_name(elf, sechdr->sh_info);
- /* if from section (name) is know good then skip it */
- if (match(fromsec, section_white_list))
- return;
-
- for (rel = start; rel < stop; rel++) {
- r.r_offset = TO_NATIVE(rel->r_offset);
-#if KERNEL_ELFCLASS == ELFCLASS64
- if (elf->hdr->e_machine == EM_MIPS) {
- unsigned int r_typ;
- r_sym = ELF64_MIPS_R_SYM(rel->r_info);
- r_sym = TO_NATIVE(r_sym);
- r_typ = ELF64_MIPS_R_TYPE(rel->r_info);
- r.r_info = ELF64_R_INFO(r_sym, r_typ);
- } else {
- r.r_info = TO_NATIVE(rel->r_info);
- r_sym = ELF_R_SYM(r.r_info);
- }
-#else
- r.r_info = TO_NATIVE(rel->r_info);
- r_sym = ELF_R_SYM(r.r_info);
-#endif
- r.r_addend = 0;
- switch (elf->hdr->e_machine) {
- case EM_386:
- if (addend_386_rel(elf, sechdr, &r))
- continue;
- break;
- case EM_ARM:
- if (addend_arm_rel(elf, sechdr, &r))
- continue;
- break;
- case EM_MIPS:
- if (addend_mips_rel(elf, sechdr, &r))
- continue;
- break;
- }
- sym = elf->symtab_start + r_sym;
- /* Skip special sections */
- if (is_shndx_special(sym->st_shndx))
- continue;
- if (is_second_extable_reloc(start, rel, fromsec))
- find_extable_entry_size(fromsec, &r);
- check_section_mismatch(modname, elf, &r, sym, fromsec);
- }
-}
-
-/**
- * A module includes a number of sections that are discarded
- * either when loaded or when used as built-in.
- * For loaded modules all functions marked __init and all data
- * marked __initdata will be discarded when the module has been initialized.
- * Likewise for modules used built-in the sections marked __exit
- * are discarded because __exit marked function are supposed to be called
- * only when a module is unloaded which never happens for built-in modules.
- * The check_sec_ref() function traverses all relocation records
- * to find all references to a section that reference a section that will
- * be discarded and warns about it.
- **/
-static void check_sec_ref(const char *modname, struct elf_info *elf)
-{
- int i;
- Elf_Shdr *sechdrs = elf->sechdrs;
-
- /* Walk through all sections */
- for (i = 0; i < elf->num_sections; i++) {
- check_section(modname, elf, &elf->sechdrs[i]);
- /* We want to process only relocation sections and not .init */
- if (sechdrs[i].sh_type == SHT_RELA)
- section_rela(modname, elf, &elf->sechdrs[i]);
- else if (sechdrs[i].sh_type == SHT_REL)
- section_rel(modname, elf, &elf->sechdrs[i]);
- }
-}
-
-static char *remove_dot(char *s)
-{
- size_t n = strcspn(s, ".");
-
- if (n && s[n]) {
- size_t m = strspn(s + n + 1, "0123456789");
- if (m && (s[n + m + 1] == '.' || s[n + m + 1] == 0))
- s[n] = 0;
- }
- return s;
-}
-
-/*
- * The CRCs are recorded in .*.cmd files in the form of:
- * #SYMVER <name> <crc>
- */
-static void extract_crcs_for_object(const char *object, struct module *mod)
-{
- char cmd_file[PATH_MAX];
- char *buf, *p;
- const char *base;
- int dirlen, ret;
-
- base = strrchr(object, '/');
- if (base) {
- base++;
- dirlen = base - object;
- } else {
- dirlen = 0;
- base = object;
- }
-
- ret = snprintf(cmd_file, sizeof(cmd_file), "%.*s.%s.cmd",
- dirlen, object, base);
- if (ret >= sizeof(cmd_file)) {
- error("%s: too long path was truncated\n", cmd_file);
- return;
- }
-
- buf = read_text_file(cmd_file);
- p = buf;
-
- while ((p = strstr(p, "\n#SYMVER "))) {
- char *name;
- size_t namelen;
- unsigned int crc;
- struct symbol *sym;
-
- name = p + strlen("\n#SYMVER ");
-
- p = strchr(name, ' ');
- if (!p)
- break;
-
- namelen = p - name;
- p++;
-
- if (!isdigit(*p))
- continue; /* skip this line */
-
- crc = strtoul(p, &p, 0);
- if (*p != '\n')
- continue; /* skip this line */
-
- name[namelen] = '\0';
-
- /*
- * sym_find_with_module() may return NULL here.
- * It typically occurs when CONFIG_TRIM_UNUSED_KSYMS=y.
- * Since commit e1327a127703, genksyms calculates CRCs of all
- * symbols, including trimmed ones. Ignore orphan CRCs.
- */
- sym = sym_find_with_module(name, mod);
- if (sym)
- sym_set_crc(sym, crc);
- }
-
- free(buf);
-}
-
-/*
- * The symbol versions (CRC) are recorded in the .*.cmd files.
- * Parse them to retrieve CRCs for the current module.
- */
-static void mod_set_crcs(struct module *mod)
-{
- char objlist[PATH_MAX];
- char *buf, *p, *obj;
- int ret;
-
- if (mod->is_vmlinux) {
- strcpy(objlist, ".vmlinux.objs");
- } else {
- /* objects for a module are listed in the *.mod file. */
- ret = snprintf(objlist, sizeof(objlist), "%s.mod", mod->name);
- if (ret >= sizeof(objlist)) {
- error("%s: too long path was truncated\n", objlist);
- return;
- }
- }
-
- buf = read_text_file(objlist);
- p = buf;
-
- while ((obj = strsep(&p, "\n")) && obj[0])
- extract_crcs_for_object(obj, mod);
-
- free(buf);
-}
-
-static void read_symbols(const char *modname)
-{
- const char *symname;
- char *version;
- char *license;
- char *namespace;
- struct module *mod;
- struct elf_info info = { };
- Elf_Sym *sym;
-
- if (!parse_elf(&info, modname))
- return;
-
- if (!strends(modname, ".o")) {
- error("%s: filename must be suffixed with .o\n", modname);
- return;
- }
-
- /* strip trailing .o */
- mod = new_module(modname, strlen(modname) - strlen(".o"));
-
- if (!mod->is_vmlinux) {
- license = get_modinfo(&info, "license");
- if (!license)
- error("missing MODULE_LICENSE() in %s\n", modname);
- while (license) {
- if (!license_is_gpl_compatible(license)) {
- mod->is_gpl_compatible = false;
- break;
- }
- license = get_next_modinfo(&info, "license", license);
- }
-
- namespace = get_modinfo(&info, "import_ns");
- while (namespace) {
- add_namespace(&mod->imported_namespaces, namespace);
- namespace = get_next_modinfo(&info, "import_ns",
- namespace);
- }
- }
-
- for (sym = info.symtab_start; sym < info.symtab_stop; sym++) {
- symname = remove_dot(info.strtab + sym->st_name);
-
- handle_symbol(mod, &info, sym, symname);
- handle_moddevtable(mod, &info, sym, symname);
- }
-
- for (sym = info.symtab_start; sym < info.symtab_stop; sym++) {
- symname = remove_dot(info.strtab + sym->st_name);
-
- /* Apply symbol namespaces from __kstrtabns_<symbol> entries. */
- if (strstarts(symname, "__kstrtabns_"))
- sym_update_namespace(symname + strlen("__kstrtabns_"),
- sym_get_data(&info, sym));
- }
-
- check_sec_ref(modname, &info);
-
- if (!mod->is_vmlinux) {
- version = get_modinfo(&info, "version");
- if (version || all_versions)
- get_src_version(mod->name, mod->srcversion,
- sizeof(mod->srcversion) - 1);
- }
-
- parse_elf_finish(&info);
-
- if (modversions) {
- /*
- * Our trick to get versioning for module struct etc. - it's
- * never passed as an argument to an exported function, so
- * the automatic versioning doesn't pick it up, but it's really
- * important anyhow.
- */
- sym_add_unresolved("module_layout", mod, false);
-
- mod_set_crcs(mod);
- }
-}
-
-static void read_symbols_from_files(const char *filename)
-{
- FILE *in = stdin;
- char fname[PATH_MAX];
-
- if (strcmp(filename, "-") != 0) {
- in = fopen(filename, "r");
- if (!in)
- fatal("Can't open filenames file %s: %m", filename);
- }
-
- while (fgets(fname, PATH_MAX, in) != NULL) {
- if (strends(fname, "\n"))
- fname[strlen(fname)-1] = '\0';
- read_symbols(fname);
- }
-
- if (in != stdin)
- fclose(in);
-}
-
-#define SZ 500
-
-/* We first write the generated file into memory using the
- * following helper, then compare to the file on disk and
- * only update the later if anything changed */
-
-void __attribute__((format(printf, 2, 3))) buf_printf(struct buffer *buf,
- const char *fmt, ...)
-{
- char tmp[SZ];
- int len;
- va_list ap;
-
- va_start(ap, fmt);
- len = vsnprintf(tmp, SZ, fmt, ap);
- buf_write(buf, tmp, len);
- va_end(ap);
-}
-
-void buf_write(struct buffer *buf, const char *s, int len)
-{
- if (buf->size - buf->pos < len) {
- buf->size += len + SZ;
- buf->p = NOFAIL(realloc(buf->p, buf->size));
- }
- strncpy(buf->p + buf->pos, s, len);
- buf->pos += len;
-}
-
-static void check_exports(struct module *mod)
-{
- struct symbol *s, *exp;
-
- list_for_each_entry(s, &mod->unresolved_symbols, list) {
- const char *basename;
- exp = find_symbol(s->name);
- if (!exp) {
- if (!s->weak && nr_unresolved++ < MAX_UNRESOLVED_REPORTS)
- modpost_log(warn_unresolved ? LOG_WARN : LOG_ERROR,
- "\"%s\" [%s.ko] undefined!\n",
- s->name, mod->name);
- continue;
- }
- if (exp->module == mod) {
- error("\"%s\" [%s.ko] was exported without definition\n",
- s->name, mod->name);
- continue;
- }
-
- s->module = exp->module;
- s->crc_valid = exp->crc_valid;
- s->crc = exp->crc;
-
- basename = strrchr(mod->name, '/');
- if (basename)
- basename++;
- else
- basename = mod->name;
-
- if (exp->namespace &&
- !contains_namespace(&mod->imported_namespaces, exp->namespace)) {
- modpost_log(allow_missing_ns_imports ? LOG_WARN : LOG_ERROR,
- "module %s uses symbol %s from namespace %s, but does not import it.\n",
- basename, exp->name, exp->namespace);
- add_namespace(&mod->missing_namespaces, exp->namespace);
- }
-
- if (!mod->is_gpl_compatible && exp->is_gpl_only)
- error("GPL-incompatible module %s.ko uses GPL-only symbol '%s'\n",
- basename, exp->name);
- }
-}
-
-static void check_modname_len(struct module *mod)
-{
- const char *mod_name;
-
- mod_name = strrchr(mod->name, '/');
- if (mod_name == NULL)
- mod_name = mod->name;
- else
- mod_name++;
- if (strlen(mod_name) >= MODULE_NAME_LEN)
- error("module name is too long [%s.ko]\n", mod->name);
-}
-
-/**
- * Header for the generated file
- **/
-static void add_header(struct buffer *b, struct module *mod)
-{
- buf_printf(b, "#include <linux/module.h>\n");
- /*
- * Include build-salt.h after module.h in order to
- * inherit the definitions.
- */
- buf_printf(b, "#define INCLUDE_VERMAGIC\n");
- buf_printf(b, "#include <linux/build-salt.h>\n");
- buf_printf(b, "#include <linux/elfnote-lto.h>\n");
- buf_printf(b, "#include <linux/export-internal.h>\n");
- buf_printf(b, "#include <linux/vermagic.h>\n");
- buf_printf(b, "#include <linux/compiler.h>\n");
- buf_printf(b, "\n");
- buf_printf(b, "BUILD_SALT;\n");
- buf_printf(b, "BUILD_LTO_INFO;\n");
- buf_printf(b, "\n");
- buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n");
- buf_printf(b, "MODULE_INFO(name, KBUILD_MODNAME);\n");
- buf_printf(b, "\n");
- buf_printf(b, "__visible struct module __this_module\n");
- buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n");
- buf_printf(b, "\t.name = KBUILD_MODNAME,\n");
- if (mod->has_init)
- buf_printf(b, "\t.init = init_module,\n");
- if (mod->has_cleanup)
- buf_printf(b, "#ifdef CONFIG_MODULE_UNLOAD\n"
- "\t.exit = cleanup_module,\n"
- "#endif\n");
- buf_printf(b, "\t.arch = MODULE_ARCH_INIT,\n");
- buf_printf(b, "};\n");
-
- if (!external_module)
- buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n");
-
- buf_printf(b,
- "\n"
- "#ifdef CONFIG_RETPOLINE\n"
- "MODULE_INFO(retpoline, \"Y\");\n"
- "#endif\n");
-
- if (strstarts(mod->name, "drivers/staging"))
- buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n");
-
- if (strstarts(mod->name, "tools/testing"))
- buf_printf(b, "\nMODULE_INFO(test, \"Y\");\n");
-}
-
-static void add_exported_symbols(struct buffer *buf, struct module *mod)
-{
- struct symbol *sym;
-
- if (!modversions)
- return;
-
- /* record CRCs for exported symbols */
- buf_printf(buf, "\n");
- list_for_each_entry(sym, &mod->exported_symbols, list) {
- if (!sym->crc_valid)
- warn("EXPORT symbol \"%s\" [%s%s] version generation failed, symbol will not be versioned.\n"
- "Is \"%s\" prototyped in <asm/asm-prototypes.h>?\n",
- sym->name, mod->name, mod->is_vmlinux ? "" : ".ko",
- sym->name);
-
- buf_printf(buf, "SYMBOL_CRC(%s, 0x%08x, \"%s\");\n",
- sym->name, sym->crc, sym->is_gpl_only ? "_gpl" : "");
- }
-}
-
-/**
- * Record CRCs for unresolved symbols
- **/
-static void add_versions(struct buffer *b, struct module *mod)
-{
- struct symbol *s;
-
- if (!modversions)
- return;
-
- buf_printf(b, "\n");
- buf_printf(b, "static const struct modversion_info ____versions[]\n");
- buf_printf(b, "__used __section(\"__versions\") = {\n");
-
- list_for_each_entry(s, &mod->unresolved_symbols, list) {
- if (!s->module)
- continue;
- if (!s->crc_valid) {
- warn("\"%s\" [%s.ko] has no CRC!\n",
- s->name, mod->name);
- continue;
- }
- if (strlen(s->name) >= MODULE_NAME_LEN) {
- error("too long symbol \"%s\" [%s.ko]\n",
- s->name, mod->name);
- break;
- }
- buf_printf(b, "\t{ %#8x, \"%s\" },\n",
- s->crc, s->name);
- }
-
- buf_printf(b, "};\n");
-}
-
-static void add_depends(struct buffer *b, struct module *mod)
-{
- struct symbol *s;
- int first = 1;
-
- /* Clear ->seen flag of modules that own symbols needed by this. */
- list_for_each_entry(s, &mod->unresolved_symbols, list) {
- if (s->module)
- s->module->seen = s->module->is_vmlinux;
- }
-
- buf_printf(b, "\n");
- buf_printf(b, "MODULE_INFO(depends, \"");
- list_for_each_entry(s, &mod->unresolved_symbols, list) {
- const char *p;
- if (!s->module)
- continue;
-
- if (s->module->seen)
- continue;
-
- s->module->seen = true;
- p = strrchr(s->module->name, '/');
- if (p)
- p++;
- else
- p = s->module->name;
- buf_printf(b, "%s%s", first ? "" : ",", p);
- first = 0;
- }
- buf_printf(b, "\");\n");
-}
-
-static void add_srcversion(struct buffer *b, struct module *mod)
-{
- if (mod->srcversion[0]) {
- buf_printf(b, "\n");
- buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n",
- mod->srcversion);
- }
-}
-
-static void write_buf(struct buffer *b, const char *fname)
-{
- FILE *file;
-
- if (error_occurred)
- return;
-
- file = fopen(fname, "w");
- if (!file) {
- perror(fname);
- exit(1);
- }
- if (fwrite(b->p, 1, b->pos, file) != b->pos) {
- perror(fname);
- exit(1);
- }
- if (fclose(file) != 0) {
- perror(fname);
- exit(1);
- }
-}
-
-static void write_if_changed(struct buffer *b, const char *fname)
-{
- char *tmp;
- FILE *file;
- struct stat st;
-
- file = fopen(fname, "r");
- if (!file)
- goto write;
-
- if (fstat(fileno(file), &st) < 0)
- goto close_write;
-
- if (st.st_size != b->pos)
- goto close_write;
-
- tmp = NOFAIL(malloc(b->pos));
- if (fread(tmp, 1, b->pos, file) != b->pos)
- goto free_write;
-
- if (memcmp(tmp, b->p, b->pos) != 0)
- goto free_write;
-
- free(tmp);
- fclose(file);
- return;
-
- free_write:
- free(tmp);
- close_write:
- fclose(file);
- write:
- write_buf(b, fname);
-}
-
-static void write_vmlinux_export_c_file(struct module *mod)
-{
- struct buffer buf = { };
-
- buf_printf(&buf,
- "#include <linux/export-internal.h>\n");
-
- add_exported_symbols(&buf, mod);
- write_if_changed(&buf, ".vmlinux.export.c");
- free(buf.p);
-}
-
-/* do sanity checks, and generate *.mod.c file */
-static void write_mod_c_file(struct module *mod)
-{
- struct buffer buf = { };
- char fname[PATH_MAX];
- int ret;
-
- check_modname_len(mod);
- check_exports(mod);
-
- add_header(&buf, mod);
- add_exported_symbols(&buf, mod);
- add_versions(&buf, mod);
- add_depends(&buf, mod);
- add_moddevtable(&buf, mod);
- add_srcversion(&buf, mod);
-
- ret = snprintf(fname, sizeof(fname), "%s.mod.c", mod->name);
- if (ret >= sizeof(fname)) {
- error("%s: too long path was truncated\n", fname);
- goto free;
- }
-
- write_if_changed(&buf, fname);
-
-free:
- free(buf.p);
-}
-
-/* parse Module.symvers file. line format:
- * 0x12345678<tab>symbol<tab>module<tab>export<tab>namespace
- **/
-static void read_dump(const char *fname)
-{
- char *buf, *pos, *line;
-
- buf = read_text_file(fname);
- if (!buf)
- /* No symbol versions, silently ignore */
- return;
-
- pos = buf;
-
- while ((line = get_line(&pos))) {
- char *symname, *namespace, *modname, *d, *export;
- unsigned int crc;
- struct module *mod;
- struct symbol *s;
- bool gpl_only;
-
- if (!(symname = strchr(line, '\t')))
- goto fail;
- *symname++ = '\0';
- if (!(modname = strchr(symname, '\t')))
- goto fail;
- *modname++ = '\0';
- if (!(export = strchr(modname, '\t')))
- goto fail;
- *export++ = '\0';
- if (!(namespace = strchr(export, '\t')))
- goto fail;
- *namespace++ = '\0';
-
- crc = strtoul(line, &d, 16);
- if (*symname == '\0' || *modname == '\0' || *d != '\0')
- goto fail;
-
- if (!strcmp(export, "EXPORT_SYMBOL_GPL")) {
- gpl_only = true;
- } else if (!strcmp(export, "EXPORT_SYMBOL")) {
- gpl_only = false;
- } else {
- error("%s: unknown license %s. skip", symname, export);
- continue;
- }
-
- mod = find_module(modname);
- if (!mod) {
- mod = new_module(modname, strlen(modname));
- mod->from_dump = true;
- }
- s = sym_add_exported(symname, mod, gpl_only);
- sym_set_crc(s, crc);
- sym_update_namespace(symname, namespace);
- }
- free(buf);
- return;
-fail:
- free(buf);
- fatal("parse error in symbol dump file\n");
-}
-
-static void write_dump(const char *fname)
-{
- struct buffer buf = { };
- struct module *mod;
- struct symbol *sym;
-
- list_for_each_entry(mod, &modules, list) {
- if (mod->from_dump)
- continue;
- list_for_each_entry(sym, &mod->exported_symbols, list) {
- buf_printf(&buf, "0x%08x\t%s\t%s\tEXPORT_SYMBOL%s\t%s\n",
- sym->crc, sym->name, mod->name,
- sym->is_gpl_only ? "_GPL" : "",
- sym->namespace ?: "");
- }
- }
- write_buf(&buf, fname);
- free(buf.p);
-}
-
-static void write_namespace_deps_files(const char *fname)
-{
- struct module *mod;
- struct namespace_list *ns;
- struct buffer ns_deps_buf = {};
-
- list_for_each_entry(mod, &modules, list) {
-
- if (mod->from_dump || list_empty(&mod->missing_namespaces))
- continue;
-
- buf_printf(&ns_deps_buf, "%s.ko:", mod->name);
-
- list_for_each_entry(ns, &mod->missing_namespaces, list)
- buf_printf(&ns_deps_buf, " %s", ns->namespace);
-
- buf_printf(&ns_deps_buf, "\n");
- }
-
- write_if_changed(&ns_deps_buf, fname);
- free(ns_deps_buf.p);
-}
-
-struct dump_list {
- struct list_head list;
- const char *file;
-};
-
-int main(int argc, char **argv)
-{
- struct module *mod;
- char *missing_namespace_deps = NULL;
- char *dump_write = NULL, *files_source = NULL;
- int opt;
- LIST_HEAD(dump_lists);
- struct dump_list *dl, *dl2;
-
- while ((opt = getopt(argc, argv, "ei:mnT:o:awENd:")) != -1) {
- switch (opt) {
- case 'e':
- external_module = true;
- break;
- case 'i':
- dl = NOFAIL(malloc(sizeof(*dl)));
- dl->file = optarg;
- list_add_tail(&dl->list, &dump_lists);
- break;
- case 'm':
- modversions = true;
- break;
- case 'n':
- ignore_missing_files = true;
- break;
- case 'o':
- dump_write = optarg;
- break;
- case 'a':
- all_versions = true;
- break;
- case 'T':
- files_source = optarg;
- break;
- case 'w':
- warn_unresolved = true;
- break;
- case 'E':
- sec_mismatch_warn_only = false;
- break;
- case 'N':
- allow_missing_ns_imports = true;
- break;
- case 'd':
- missing_namespace_deps = optarg;
- break;
- default:
- exit(1);
- }
- }
-
- list_for_each_entry_safe(dl, dl2, &dump_lists, list) {
- read_dump(dl->file);
- list_del(&dl->list);
- free(dl);
- }
-
- while (optind < argc)
- read_symbols(argv[optind++]);
-
- if (files_source)
- read_symbols_from_files(files_source);
-
- list_for_each_entry(mod, &modules, list) {
- if (mod->from_dump)
- continue;
-
- if (mod->is_vmlinux)
- write_vmlinux_export_c_file(mod);
- else
- write_mod_c_file(mod);
- }
-
- if (missing_namespace_deps)
- write_namespace_deps_files(missing_namespace_deps);
-
- if (dump_write)
- write_dump(dump_write);
- if (sec_mismatch_count && !sec_mismatch_warn_only)
- error("Section mismatches detected.\n"
- "Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them.\n");
-
- if (nr_unresolved > MAX_UNRESOLVED_REPORTS)
- warn("suppressed %u unresolved symbol warnings because there were too many)\n",
- nr_unresolved - MAX_UNRESOLVED_REPORTS);
-
- return error_occurred ? 1 : 0;
-}
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/mod/sumversion.c
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/mod/sumversion.c (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/mod/sumversion.c (nonexistent)
@@ -1,410 +0,0 @@
-#include <netinet/in.h>
-#ifdef __sun__
-#include <inttypes.h>
-#else
-#include <stdint.h>
-#endif
-#include <ctype.h>
-#include <errno.h>
-#include <string.h>
-#include <linux/limits.h>
-#include "modpost.h"
-
-/*
- * Stolen form Cryptographic API.
- *
- * MD4 Message Digest Algorithm (RFC1320).
- *
- * Implementation derived from Andrew Tridgell and Steve French's
- * CIFS MD4 implementation, and the cryptoapi implementation
- * originally based on the public domain implementation written
- * by Colin Plumb in 1993.
- *
- * Copyright (c) Andrew Tridgell 1997-1998.
- * Modified by Steve French (sfrench@us.ibm.com) 2002
- * Copyright (c) Cryptoapi developers.
- * Copyright (c) 2002 David S. Miller (davem@redhat.com)
- * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#define MD4_DIGEST_SIZE 16
-#define MD4_HMAC_BLOCK_SIZE 64
-#define MD4_BLOCK_WORDS 16
-#define MD4_HASH_WORDS 4
-
-struct md4_ctx {
- uint32_t hash[MD4_HASH_WORDS];
- uint32_t block[MD4_BLOCK_WORDS];
- uint64_t byte_count;
-};
-
-static inline uint32_t lshift(uint32_t x, unsigned int s)
-{
- x &= 0xFFFFFFFF;
- return ((x << s) & 0xFFFFFFFF) | (x >> (32 - s));
-}
-
-static inline uint32_t F(uint32_t x, uint32_t y, uint32_t z)
-{
- return (x & y) | ((~x) & z);
-}
-
-static inline uint32_t G(uint32_t x, uint32_t y, uint32_t z)
-{
- return (x & y) | (x & z) | (y & z);
-}
-
-static inline uint32_t H(uint32_t x, uint32_t y, uint32_t z)
-{
- return x ^ y ^ z;
-}
-
-#define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s))
-#define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (uint32_t)0x5A827999,s))
-#define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (uint32_t)0x6ED9EBA1,s))
-
-/* XXX: this stuff can be optimized */
-static inline void le32_to_cpu_array(uint32_t *buf, unsigned int words)
-{
- while (words--) {
- *buf = ntohl(*buf);
- buf++;
- }
-}
-
-static inline void cpu_to_le32_array(uint32_t *buf, unsigned int words)
-{
- while (words--) {
- *buf = htonl(*buf);
- buf++;
- }
-}
-
-static void md4_transform(uint32_t *hash, uint32_t const *in)
-{
- uint32_t a, b, c, d;
-
- a = hash[0];
- b = hash[1];
- c = hash[2];
- d = hash[3];
-
- ROUND1(a, b, c, d, in[0], 3);
- ROUND1(d, a, b, c, in[1], 7);
- ROUND1(c, d, a, b, in[2], 11);
- ROUND1(b, c, d, a, in[3], 19);
- ROUND1(a, b, c, d, in[4], 3);
- ROUND1(d, a, b, c, in[5], 7);
- ROUND1(c, d, a, b, in[6], 11);
- ROUND1(b, c, d, a, in[7], 19);
- ROUND1(a, b, c, d, in[8], 3);
- ROUND1(d, a, b, c, in[9], 7);
- ROUND1(c, d, a, b, in[10], 11);
- ROUND1(b, c, d, a, in[11], 19);
- ROUND1(a, b, c, d, in[12], 3);
- ROUND1(d, a, b, c, in[13], 7);
- ROUND1(c, d, a, b, in[14], 11);
- ROUND1(b, c, d, a, in[15], 19);
-
- ROUND2(a, b, c, d,in[ 0], 3);
- ROUND2(d, a, b, c, in[4], 5);
- ROUND2(c, d, a, b, in[8], 9);
- ROUND2(b, c, d, a, in[12], 13);
- ROUND2(a, b, c, d, in[1], 3);
- ROUND2(d, a, b, c, in[5], 5);
- ROUND2(c, d, a, b, in[9], 9);
- ROUND2(b, c, d, a, in[13], 13);
- ROUND2(a, b, c, d, in[2], 3);
- ROUND2(d, a, b, c, in[6], 5);
- ROUND2(c, d, a, b, in[10], 9);
- ROUND2(b, c, d, a, in[14], 13);
- ROUND2(a, b, c, d, in[3], 3);
- ROUND2(d, a, b, c, in[7], 5);
- ROUND2(c, d, a, b, in[11], 9);
- ROUND2(b, c, d, a, in[15], 13);
-
- ROUND3(a, b, c, d,in[ 0], 3);
- ROUND3(d, a, b, c, in[8], 9);
- ROUND3(c, d, a, b, in[4], 11);
- ROUND3(b, c, d, a, in[12], 15);
- ROUND3(a, b, c, d, in[2], 3);
- ROUND3(d, a, b, c, in[10], 9);
- ROUND3(c, d, a, b, in[6], 11);
- ROUND3(b, c, d, a, in[14], 15);
- ROUND3(a, b, c, d, in[1], 3);
- ROUND3(d, a, b, c, in[9], 9);
- ROUND3(c, d, a, b, in[5], 11);
- ROUND3(b, c, d, a, in[13], 15);
- ROUND3(a, b, c, d, in[3], 3);
- ROUND3(d, a, b, c, in[11], 9);
- ROUND3(c, d, a, b, in[7], 11);
- ROUND3(b, c, d, a, in[15], 15);
-
- hash[0] += a;
- hash[1] += b;
- hash[2] += c;
- hash[3] += d;
-}
-
-static inline void md4_transform_helper(struct md4_ctx *ctx)
-{
- le32_to_cpu_array(ctx->block, sizeof(ctx->block) / sizeof(uint32_t));
- md4_transform(ctx->hash, ctx->block);
-}
-
-static void md4_init(struct md4_ctx *mctx)
-{
- mctx->hash[0] = 0x67452301;
- mctx->hash[1] = 0xefcdab89;
- mctx->hash[2] = 0x98badcfe;
- mctx->hash[3] = 0x10325476;
- mctx->byte_count = 0;
-}
-
-static void md4_update(struct md4_ctx *mctx,
- const unsigned char *data, unsigned int len)
-{
- const uint32_t avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
-
- mctx->byte_count += len;
-
- if (avail > len) {
- memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
- data, len);
- return;
- }
-
- memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
- data, avail);
-
- md4_transform_helper(mctx);
- data += avail;
- len -= avail;
-
- while (len >= sizeof(mctx->block)) {
- memcpy(mctx->block, data, sizeof(mctx->block));
- md4_transform_helper(mctx);
- data += sizeof(mctx->block);
- len -= sizeof(mctx->block);
- }
-
- memcpy(mctx->block, data, len);
-}
-
-static void md4_final_ascii(struct md4_ctx *mctx, char *out, unsigned int len)
-{
- const unsigned int offset = mctx->byte_count & 0x3f;
- char *p = (char *)mctx->block + offset;
- int padding = 56 - (offset + 1);
-
- *p++ = 0x80;
- if (padding < 0) {
- memset(p, 0x00, padding + sizeof (uint64_t));
- md4_transform_helper(mctx);
- p = (char *)mctx->block;
- padding = 56;
- }
-
- memset(p, 0, padding);
- mctx->block[14] = mctx->byte_count << 3;
- mctx->block[15] = mctx->byte_count >> 29;
- le32_to_cpu_array(mctx->block, (sizeof(mctx->block) -
- sizeof(uint64_t)) / sizeof(uint32_t));
- md4_transform(mctx->hash, mctx->block);
- cpu_to_le32_array(mctx->hash, sizeof(mctx->hash) / sizeof(uint32_t));
-
- snprintf(out, len, "%08X%08X%08X%08X",
- mctx->hash[0], mctx->hash[1], mctx->hash[2], mctx->hash[3]);
-}
-
-static inline void add_char(unsigned char c, struct md4_ctx *md)
-{
- md4_update(md, &c, 1);
-}
-
-static int parse_string(const char *file, unsigned long len,
- struct md4_ctx *md)
-{
- unsigned long i;
-
- add_char(file[0], md);
- for (i = 1; i < len; i++) {
- add_char(file[i], md);
- if (file[i] == '"' && file[i-1] != '\\')
- break;
- }
- return i;
-}
-
-static int parse_comment(const char *file, unsigned long len)
-{
- unsigned long i;
-
- for (i = 2; i < len; i++) {
- if (file[i-1] == '*' && file[i] == '/')
- break;
- }
- return i;
-}
-
-/* FIXME: Handle .s files differently (eg. # starts comments) --RR */
-static int parse_file(const char *fname, struct md4_ctx *md)
-{
- char *file;
- unsigned long i, len;
-
- file = read_text_file(fname);
- len = strlen(file);
-
- for (i = 0; i < len; i++) {
- /* Collapse and ignore \ and CR. */
- if (file[i] == '\\' && (i+1 < len) && file[i+1] == '\n') {
- i++;
- continue;
- }
-
- /* Ignore whitespace */
- if (isspace(file[i]))
- continue;
-
- /* Handle strings as whole units */
- if (file[i] == '"') {
- i += parse_string(file+i, len - i, md);
- continue;
- }
-
- /* Comments: ignore */
- if (file[i] == '/' && file[i+1] == '*') {
- i += parse_comment(file+i, len - i);
- continue;
- }
-
- add_char(file[i], md);
- }
- free(file);
- return 1;
-}
-/* Check whether the file is a static library or not */
-static bool is_static_library(const char *objfile)
-{
- int len = strlen(objfile);
-
- return objfile[len - 2] == '.' && objfile[len - 1] == 'a';
-}
-
-/* We have dir/file.o. Open dir/.file.o.cmd, look for source_ and deps_ line
- * to figure out source files. */
-static int parse_source_files(const char *objfile, struct md4_ctx *md)
-{
- char *cmd, *file, *line, *dir, *pos;
- const char *base;
- int dirlen, ret = 0, check_files = 0;
-
- cmd = NOFAIL(malloc(strlen(objfile) + sizeof("..cmd")));
-
- base = strrchr(objfile, '/');
- if (base) {
- base++;
- dirlen = base - objfile;
- sprintf(cmd, "%.*s.%s.cmd", dirlen, objfile, base);
- } else {
- dirlen = 0;
- sprintf(cmd, ".%s.cmd", objfile);
- }
- dir = NOFAIL(malloc(dirlen + 1));
- strncpy(dir, objfile, dirlen);
- dir[dirlen] = '\0';
-
- file = read_text_file(cmd);
-
- pos = file;
-
- /* Sum all files in the same dir or subdirs. */
- while ((line = get_line(&pos))) {
- char* p = line;
-
- if (strncmp(line, "source_", sizeof("source_")-1) == 0) {
- p = strrchr(line, ' ');
- if (!p) {
- warn("malformed line: %s\n", line);
- goto out_file;
- }
- p++;
- if (!parse_file(p, md)) {
- warn("could not open %s: %s\n",
- p, strerror(errno));
- goto out_file;
- }
- continue;
- }
- if (strncmp(line, "deps_", sizeof("deps_")-1) == 0) {
- check_files = 1;
- continue;
- }
- if (!check_files)
- continue;
-
- /* Continue until line does not end with '\' */
- if ( *(p + strlen(p)-1) != '\\')
- break;
- /* Terminate line at first space, to get rid of final ' \' */
- while (*p) {
- if (isspace(*p)) {
- *p = '\0';
- break;
- }
- p++;
- }
-
- /* Check if this file is in same dir as objfile */
- if ((strstr(line, dir)+strlen(dir)-1) == strrchr(line, '/')) {
- if (!parse_file(line, md)) {
- warn("could not open %s: %s\n",
- line, strerror(errno));
- goto out_file;
- }
-
- }
-
- }
-
- /* Everyone parsed OK */
- ret = 1;
-out_file:
- free(file);
- free(dir);
- free(cmd);
- return ret;
-}
-
-/* Calc and record src checksum. */
-void get_src_version(const char *modname, char sum[], unsigned sumlen)
-{
- char *buf;
- struct md4_ctx md;
- char *fname;
- char filelist[PATH_MAX + 1];
-
- /* objects for a module are listed in the first line of *.mod file. */
- snprintf(filelist, sizeof(filelist), "%s.mod", modname);
-
- buf = read_text_file(filelist);
-
- md4_init(&md);
- while ((fname = strsep(&buf, "\n"))) {
- if (!*fname)
- continue;
- if (!(is_static_library(fname)) &&
- !parse_source_files(fname, &md))
- goto free;
- }
-
- md4_final_ascii(&md, sum, sumlen);
-free:
- free(buf);
-}
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/lexer.l
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/lexer.l (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/lexer.l (nonexistent)
@@ -1,468 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-%option nostdinit noyywrap never-interactive full ecs
-%option 8bit nodefault yylineno
-%x ASSIGN_VAL HELP STRING
-%{
-
-#include <assert.h>
-#include <linux/limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "lkc.h"
-#include "parser.tab.h"
-
-#define YY_DECL static int yylex1(void)
-
-#define START_STRSIZE 16
-
-static struct {
- struct file *file;
- int lineno;
-} current_pos;
-
-static int prev_prev_token = T_EOL;
-static int prev_token = T_EOL;
-static char *text;
-static int text_size, text_asize;
-
-struct buffer {
- struct buffer *parent;
- YY_BUFFER_STATE state;
-};
-
-static struct buffer *current_buf;
-
-static int last_ts, first_ts;
-
-static char *expand_token(const char *in, size_t n);
-static void append_expanded_string(const char *in);
-static void zconf_endhelp(void);
-static void zconf_endfile(void);
-
-static void new_string(void)
-{
- text = xmalloc(START_STRSIZE);
- text_asize = START_STRSIZE;
- text_size = 0;
- *text = 0;
-}
-
-static void append_string(const char *str, int size)
-{
- int new_size = text_size + size + 1;
- if (new_size > text_asize) {
- new_size += START_STRSIZE - 1;
- new_size &= -START_STRSIZE;
- text = xrealloc(text, new_size);
- text_asize = new_size;
- }
- memcpy(text + text_size, str, size);
- text_size += size;
- text[text_size] = 0;
-}
-
-static void alloc_string(const char *str, int size)
-{
- text = xmalloc(size + 1);
- memcpy(text, str, size);
- text[size] = 0;
-}
-
-static void warn_ignored_character(char chr)
-{
- fprintf(stderr,
- "%s:%d:warning: ignoring unsupported character '%c'\n",
- current_file->name, yylineno, chr);
-}
-%}
-
-n [A-Za-z0-9_-]
-
-%%
- char open_quote = 0;
-
-#.* /* ignore comment */
-[ \t]* /* whitespaces */
-\\\n /* escaped new line */
-\n return T_EOL;
-"bool" return T_BOOL;
-"choice" return T_CHOICE;
-"comment" return T_COMMENT;
-"config" return T_CONFIG;
-"def_bool" return T_DEF_BOOL;
-"def_tristate" return T_DEF_TRISTATE;
-"default" return T_DEFAULT;
-"depends" return T_DEPENDS;
-"endchoice" return T_ENDCHOICE;
-"endif" return T_ENDIF;
-"endmenu" return T_ENDMENU;
-"help" return T_HELP;
-"hex" return T_HEX;
-"if" return T_IF;
-"imply" return T_IMPLY;
-"int" return T_INT;
-"mainmenu" return T_MAINMENU;
-"menu" return T_MENU;
-"menuconfig" return T_MENUCONFIG;
-"modules" return T_MODULES;
-"on" return T_ON;
-"optional" return T_OPTIONAL;
-"prompt" return T_PROMPT;
-"range" return T_RANGE;
-"select" return T_SELECT;
-"source" return T_SOURCE;
-"string" return T_STRING;
-"tristate" return T_TRISTATE;
-"visible" return T_VISIBLE;
-"||" return T_OR;
-"&&" return T_AND;
-"=" return T_EQUAL;
-"!=" return T_UNEQUAL;
-"<" return T_LESS;
-"<=" return T_LESS_EQUAL;
-">" return T_GREATER;
-">=" return T_GREATER_EQUAL;
-"!" return T_NOT;
-"(" return T_OPEN_PAREN;
-")" return T_CLOSE_PAREN;
-":=" return T_COLON_EQUAL;
-"+=" return T_PLUS_EQUAL;
-\"|\' {
- open_quote = yytext[0];
- new_string();
- BEGIN(STRING);
- }
-{n}+ {
- alloc_string(yytext, yyleng);
- yylval.string = text;
- return T_WORD;
- }
-({n}|$)+ {
- /* this token includes at least one '$' */
- yylval.string = expand_token(yytext, yyleng);
- if (strlen(yylval.string))
- return T_WORD;
- free(yylval.string);
- }
-. warn_ignored_character(*yytext);
-
-<ASSIGN_VAL>{
- [^[:blank:]\n]+.* {
- alloc_string(yytext, yyleng);
- yylval.string = text;
- return T_ASSIGN_VAL;
- }
- \n { BEGIN(INITIAL); return T_EOL; }
- .
-}
-
-<STRING>{
- "$".* append_expanded_string(yytext);
- [^$'"\\\n]+ {
- append_string(yytext, yyleng);
- }
- \\.? {
- append_string(yytext + 1, yyleng - 1);
- }
- \'|\" {
- if (open_quote == yytext[0]) {
- BEGIN(INITIAL);
- yylval.string = text;
- return T_WORD_QUOTE;
- } else
- append_string(yytext, 1);
- }
- \n {
- fprintf(stderr,
- "%s:%d:warning: multi-line strings not supported\n",
- zconf_curname(), zconf_lineno());
- unput('\n');
- BEGIN(INITIAL);
- yylval.string = text;
- return T_WORD_QUOTE;
- }
- <<EOF>> {
- BEGIN(INITIAL);
- yylval.string = text;
- return T_WORD_QUOTE;
- }
-}
-
-<HELP>{
- [ \t]+ {
- int ts, i;
-
- ts = 0;
- for (i = 0; i < yyleng; i++) {
- if (yytext[i] == '\t')
- ts = (ts & ~7) + 8;
- else
- ts++;
- }
- last_ts = ts;
- if (first_ts) {
- if (ts < first_ts) {
- zconf_endhelp();
- return T_HELPTEXT;
- }
- ts -= first_ts;
- while (ts > 8) {
- append_string(" ", 8);
- ts -= 8;
- }
- append_string(" ", ts);
- }
- }
- [ \t]*\n/[^ \t\n] {
- zconf_endhelp();
- return T_HELPTEXT;
- }
- [ \t]*\n {
- append_string("\n", 1);
- }
- [^ \t\n].* {
- while (yyleng) {
- if ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\t'))
- break;
- yyleng--;
- }
- append_string(yytext, yyleng);
- if (!first_ts)
- first_ts = last_ts;
- }
- <<EOF>> {
- zconf_endhelp();
- return T_HELPTEXT;
- }
-}
-
-<<EOF>> {
- BEGIN(INITIAL);
-
- if (prev_token != T_EOL && prev_token != T_HELPTEXT)
- fprintf(stderr, "%s:%d:warning: no new line at end of file\n",
- current_file->name, yylineno);
-
- if (current_file) {
- zconf_endfile();
- return T_EOL;
- }
- fclose(yyin);
- yyterminate();
-}
-
-%%
-
-/* second stage lexer */
-int yylex(void)
-{
- int token;
-
-repeat:
- token = yylex1();
-
- if (prev_token == T_EOL || prev_token == T_HELPTEXT) {
- if (token == T_EOL) {
- /* Do not pass unneeded T_EOL to the parser. */
- goto repeat;
- } else {
- /*
- * For the parser, update file/lineno at the first token
- * of each statement. Generally, \n is a statement
- * terminator in Kconfig, but it is not always true
- * because \n could be escaped by a backslash.
- */
- current_pos.file = current_file;
- current_pos.lineno = yylineno;
- }
- }
-
- if (prev_prev_token == T_EOL && prev_token == T_WORD &&
- (token == T_EQUAL || token == T_COLON_EQUAL || token == T_PLUS_EQUAL))
- BEGIN(ASSIGN_VAL);
-
- prev_prev_token = prev_token;
- prev_token = token;
-
- return token;
-}
-
-static char *expand_token(const char *in, size_t n)
-{
- char *out;
- int c;
- char c2;
- const char *rest, *end;
-
- new_string();
- append_string(in, n);
-
- /* get the whole line because we do not know the end of token. */
- while ((c = input()) != EOF) {
- if (c == '\n') {
- unput(c);
- break;
- }
- c2 = c;
- append_string(&c2, 1);
- }
-
- rest = text;
- out = expand_one_token(&rest);
-
- /* push back unused characters to the input stream */
- end = rest + strlen(rest);
- while (end > rest)
- unput(*--end);
-
- free(text);
-
- return out;
-}
-
-static void append_expanded_string(const char *str)
-{
- const char *end;
- char *res;
-
- str++;
-
- res = expand_dollar(&str);
-
- /* push back unused characters to the input stream */
- end = str + strlen(str);
- while (end > str)
- unput(*--end);
-
- append_string(res, strlen(res));
-
- free(res);
-}
-
-void zconf_starthelp(void)
-{
- new_string();
- last_ts = first_ts = 0;
- BEGIN(HELP);
-}
-
-static void zconf_endhelp(void)
-{
- yylval.string = text;
- BEGIN(INITIAL);
-}
-
-
-/*
- * Try to open specified file with following names:
- * ./name
- * $(srctree)/name
- * The latter is used when srctree is separate from objtree
- * when compiling the kernel.
- * Return NULL if file is not found.
- */
-FILE *zconf_fopen(const char *name)
-{
- char *env, fullname[PATH_MAX+1];
- FILE *f;
-
- f = fopen(name, "r");
- if (!f && name != NULL && name[0] != '/') {
- env = getenv(SRCTREE);
- if (env) {
- snprintf(fullname, sizeof(fullname),
- "%s/%s", env, name);
- f = fopen(fullname, "r");
- }
- }
- return f;
-}
-
-void zconf_initscan(const char *name)
-{
- yyin = zconf_fopen(name);
- if (!yyin) {
- fprintf(stderr, "can't find file %s\n", name);
- exit(1);
- }
-
- current_buf = xmalloc(sizeof(*current_buf));
- memset(current_buf, 0, sizeof(*current_buf));
-
- current_file = file_lookup(name);
- yylineno = 1;
-}
-
-void zconf_nextfile(const char *name)
-{
- struct file *iter;
- struct file *file = file_lookup(name);
- struct buffer *buf = xmalloc(sizeof(*buf));
- memset(buf, 0, sizeof(*buf));
-
- current_buf->state = YY_CURRENT_BUFFER;
- yyin = zconf_fopen(file->name);
- if (!yyin) {
- fprintf(stderr, "%s:%d: can't open file \"%s\"\n",
- zconf_curname(), zconf_lineno(), file->name);
- exit(1);
- }
- yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));
- buf->parent = current_buf;
- current_buf = buf;
-
- current_file->lineno = yylineno;
- file->parent = current_file;
-
- for (iter = current_file; iter; iter = iter->parent) {
- if (!strcmp(iter->name, file->name)) {
- fprintf(stderr,
- "Recursive inclusion detected.\n"
- "Inclusion path:\n"
- " current file : %s\n", file->name);
- iter = file;
- do {
- iter = iter->parent;
- fprintf(stderr, " included from: %s:%d\n",
- iter->name, iter->lineno - 1);
- } while (strcmp(iter->name, file->name));
- exit(1);
- }
- }
-
- yylineno = 1;
- current_file = file;
-}
-
-static void zconf_endfile(void)
-{
- struct buffer *parent;
-
- current_file = current_file->parent;
- if (current_file)
- yylineno = current_file->lineno;
-
- parent = current_buf->parent;
- if (parent) {
- fclose(yyin);
- yy_delete_buffer(YY_CURRENT_BUFFER);
- yy_switch_to_buffer(parent->state);
- }
- free(current_buf);
- current_buf = parent;
-}
-
-int zconf_lineno(void)
-{
- return current_pos.lineno;
-}
-
-const char *zconf_curname(void)
-{
- return current_pos.file ? current_pos.file->name : "<none>";
-}
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/confdata.c
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/confdata.c (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/confdata.c (nonexistent)
@@ -1,1265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <sys/mman.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <ctype.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <linux/limits.h>
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "lkc.h"
-
-/* return true if 'path' exists, false otherwise */
-static bool is_present(const char *path)
-{
- struct stat st;
-
- return !stat(path, &st);
-}
-
-/* return true if 'path' exists and it is a directory, false otherwise */
-static bool is_dir(const char *path)
-{
- struct stat st;
-
- if (stat(path, &st))
- return false;
-
- return S_ISDIR(st.st_mode);
-}
-
-/* return true if the given two files are the same, false otherwise */
-static bool is_same(const char *file1, const char *file2)
-{
- int fd1, fd2;
- struct stat st1, st2;
- void *map1, *map2;
- bool ret = false;
-
- fd1 = open(file1, O_RDONLY);
- if (fd1 < 0)
- return ret;
-
- fd2 = open(file2, O_RDONLY);
- if (fd2 < 0)
- goto close1;
-
- ret = fstat(fd1, &st1);
- if (ret)
- goto close2;
- ret = fstat(fd2, &st2);
- if (ret)
- goto close2;
-
- if (st1.st_size != st2.st_size)
- goto close2;
-
- map1 = mmap(NULL, st1.st_size, PROT_READ, MAP_PRIVATE, fd1, 0);
- if (map1 == MAP_FAILED)
- goto close2;
-
- map2 = mmap(NULL, st2.st_size, PROT_READ, MAP_PRIVATE, fd2, 0);
- if (map2 == MAP_FAILED)
- goto close2;
-
- if (bcmp(map1, map2, st1.st_size))
- goto close2;
-
- ret = true;
-close2:
- close(fd2);
-close1:
- close(fd1);
-
- return ret;
-}
-
-/*
- * Create the parent directory of the given path.
- *
- * For example, if 'include/config/auto.conf' is given, create 'include/config'.
- */
-static int make_parent_dir(const char *path)
-{
- char tmp[PATH_MAX + 1];
- char *p;
-
- strncpy(tmp, path, sizeof(tmp));
- tmp[sizeof(tmp) - 1] = 0;
-
- /* Remove the base name. Just return if nothing is left */
- p = strrchr(tmp, '/');
- if (!p)
- return 0;
- *(p + 1) = 0;
-
- /* Just in case it is an absolute path */
- p = tmp;
- while (*p == '/')
- p++;
-
- while ((p = strchr(p, '/'))) {
- *p = 0;
-
- /* skip if the directory exists */
- if (!is_dir(tmp) && mkdir(tmp, 0755))
- return -1;
-
- *p = '/';
- while (*p == '/')
- p++;
- }
-
- return 0;
-}
-
-static char depfile_path[PATH_MAX];
-static size_t depfile_prefix_len;
-
-/* touch depfile for symbol 'name' */
-static int conf_touch_dep(const char *name)
-{
- int fd;
-
- /* check overflow: prefix + name + '\0' must fit in buffer. */
- if (depfile_prefix_len + strlen(name) + 1 > sizeof(depfile_path))
- return -1;
-
- strcpy(depfile_path + depfile_prefix_len, name);
-
- fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if (fd == -1)
- return -1;
- close(fd);
-
- return 0;
-}
-
-static void conf_warning(const char *fmt, ...)
- __attribute__ ((format (printf, 1, 2)));
-
-static void conf_message(const char *fmt, ...)
- __attribute__ ((format (printf, 1, 2)));
-
-static const char *conf_filename;
-static int conf_lineno, conf_warnings;
-
-static void conf_warning(const char *fmt, ...)
-{
- va_list ap;
- va_start(ap, fmt);
- fprintf(stderr, "%s:%d:warning: ", conf_filename, conf_lineno);
- vfprintf(stderr, fmt, ap);
- fprintf(stderr, "\n");
- va_end(ap);
- conf_warnings++;
-}
-
-static void conf_default_message_callback(const char *s)
-{
- printf("#\n# ");
- printf("%s", s);
- printf("\n#\n");
-}
-
-static void (*conf_message_callback)(const char *s) =
- conf_default_message_callback;
-void conf_set_message_callback(void (*fn)(const char *s))
-{
- conf_message_callback = fn;
-}
-
-static void conf_message(const char *fmt, ...)
-{
- va_list ap;
- char buf[4096];
-
- if (!conf_message_callback)
- return;
-
- va_start(ap, fmt);
-
- vsnprintf(buf, sizeof(buf), fmt, ap);
- conf_message_callback(buf);
- va_end(ap);
-}
-
-const char *conf_get_configname(void)
-{
- char *name = getenv("KCONFIG_CONFIG");
-
- return name ? name : ".config";
-}
-
-static const char *conf_get_autoconfig_name(void)
-{
- char *name = getenv("KCONFIG_AUTOCONFIG");
-
- return name ? name : "include/config/auto.conf";
-}
-
-static const char *conf_get_autoheader_name(void)
-{
- char *name = getenv("KCONFIG_AUTOHEADER");
-
- return name ? name : "include/generated/autoconf.h";
-}
-
-static const char *conf_get_rustccfg_name(void)
-{
- char *name = getenv("KCONFIG_RUSTCCFG");
-
- return name ? name : "include/generated/rustc_cfg";
-}
-
-static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
-{
- char *p2;
-
- switch (sym->type) {
- case S_TRISTATE:
- if (p[0] == 'm') {
- sym->def[def].tri = mod;
- sym->flags |= def_flags;
- break;
- }
- /* fall through */
- case S_BOOLEAN:
- if (p[0] == 'y') {
- sym->def[def].tri = yes;
- sym->flags |= def_flags;
- break;
- }
- if (p[0] == 'n') {
- sym->def[def].tri = no;
- sym->flags |= def_flags;
- break;
- }
- if (def != S_DEF_AUTO)
- conf_warning("symbol value '%s' invalid for %s",
- p, sym->name);
- return 1;
- case S_STRING:
- /* No escaping for S_DEF_AUTO (include/config/auto.conf) */
- if (def != S_DEF_AUTO) {
- if (*p++ != '"')
- break;
- for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) {
- if (*p2 == '"') {
- *p2 = 0;
- break;
- }
- memmove(p2, p2 + 1, strlen(p2));
- }
- if (!p2) {
- conf_warning("invalid string found");
- return 1;
- }
- }
- /* fall through */
- case S_INT:
- case S_HEX:
- if (sym_string_valid(sym, p)) {
- sym->def[def].val = xstrdup(p);
- sym->flags |= def_flags;
- } else {
- if (def != S_DEF_AUTO)
- conf_warning("symbol value '%s' invalid for %s",
- p, sym->name);
- return 1;
- }
- break;
- default:
- ;
- }
- return 0;
-}
-
-#define LINE_GROWTH 16
-static int add_byte(int c, char **lineptr, size_t slen, size_t *n)
-{
- char *nline;
- size_t new_size = slen + 1;
- if (new_size > *n) {
- new_size += LINE_GROWTH - 1;
- new_size *= 2;
- nline = xrealloc(*lineptr, new_size);
- if (!nline)
- return -1;
-
- *lineptr = nline;
- *n = new_size;
- }
-
- (*lineptr)[slen] = c;
-
- return 0;
-}
-
-static ssize_t compat_getline(char **lineptr, size_t *n, FILE *stream)
-{
- char *line = *lineptr;
- size_t slen = 0;
-
- for (;;) {
- int c = getc(stream);
-
- switch (c) {
- case '\n':
- if (add_byte(c, &line, slen, n) < 0)
- goto e_out;
- slen++;
- /* fall through */
- case EOF:
- if (add_byte('\0', &line, slen, n) < 0)
- goto e_out;
- *lineptr = line;
- if (slen == 0)
- return -1;
- return slen;
- default:
- if (add_byte(c, &line, slen, n) < 0)
- goto e_out;
- slen++;
- }
- }
-
-e_out:
- line[slen-1] = '\0';
- *lineptr = line;
- return -1;
-}
-
-int conf_read_simple(const char *name, int def)
-{
- FILE *in = NULL;
- char *line = NULL;
- size_t line_asize = 0;
- char *p, *p2;
- struct symbol *sym;
- int i, def_flags;
-
- if (name) {
- in = zconf_fopen(name);
- } else {
- char *env;
-
- name = conf_get_configname();
- in = zconf_fopen(name);
- if (in)
- goto load;
- conf_set_changed(true);
-
- env = getenv("KCONFIG_DEFCONFIG_LIST");
- if (!env)
- return 1;
-
- while (1) {
- bool is_last;
-
- while (isspace(*env))
- env++;
-
- if (!*env)
- break;
-
- p = env;
- while (*p && !isspace(*p))
- p++;
-
- is_last = (*p == '\0');
-
- *p = '\0';
-
- in = zconf_fopen(env);
- if (in) {
- conf_message("using defaults found in %s",
- env);
- goto load;
- }
-
- if (is_last)
- break;
-
- env = p + 1;
- }
- }
- if (!in)
- return 1;
-
-load:
- conf_filename = name;
- conf_lineno = 0;
- conf_warnings = 0;
-
- def_flags = SYMBOL_DEF << def;
- for_all_symbols(i, sym) {
- sym->flags |= SYMBOL_CHANGED;
- sym->flags &= ~(def_flags|SYMBOL_VALID);
- if (sym_is_choice(sym))
- sym->flags |= def_flags;
- switch (sym->type) {
- case S_INT:
- case S_HEX:
- case S_STRING:
- if (sym->def[def].val)
- free(sym->def[def].val);
- /* fall through */
- default:
- sym->def[def].val = NULL;
- sym->def[def].tri = no;
- }
- }
-
- while (compat_getline(&line, &line_asize, in) != -1) {
- conf_lineno++;
- sym = NULL;
- if (line[0] == '#') {
- if (memcmp(line + 2, CONFIG_, strlen(CONFIG_)))
- continue;
- p = strchr(line + 2 + strlen(CONFIG_), ' ');
- if (!p)
- continue;
- *p++ = 0;
- if (strncmp(p, "is not set", 10))
- continue;
- if (def == S_DEF_USER) {
- sym = sym_find(line + 2 + strlen(CONFIG_));
- if (!sym) {
- conf_set_changed(true);
- continue;
- }
- } else {
- sym = sym_lookup(line + 2 + strlen(CONFIG_), 0);
- if (sym->type == S_UNKNOWN)
- sym->type = S_BOOLEAN;
- }
- if (sym->flags & def_flags) {
- conf_warning("override: reassigning to symbol %s", sym->name);
- }
- switch (sym->type) {
- case S_BOOLEAN:
- case S_TRISTATE:
- sym->def[def].tri = no;
- sym->flags |= def_flags;
- break;
- default:
- ;
- }
- } else if (memcmp(line, CONFIG_, strlen(CONFIG_)) == 0) {
- p = strchr(line + strlen(CONFIG_), '=');
- if (!p)
- continue;
- *p++ = 0;
- p2 = strchr(p, '\n');
- if (p2) {
- *p2-- = 0;
- if (*p2 == '\r')
- *p2 = 0;
- }
-
- sym = sym_find(line + strlen(CONFIG_));
- if (!sym) {
- if (def == S_DEF_AUTO)
- /*
- * Reading from include/config/auto.conf
- * If CONFIG_FOO previously existed in
- * auto.conf but it is missing now,
- * include/config/FOO must be touched.
- */
- conf_touch_dep(line + strlen(CONFIG_));
- else
- conf_set_changed(true);
- continue;
- }
-
- if (sym->flags & def_flags) {
- conf_warning("override: reassigning to symbol %s", sym->name);
- }
- if (conf_set_sym_val(sym, def, def_flags, p))
- continue;
- } else {
- if (line[0] != '\r' && line[0] != '\n')
- conf_warning("unexpected data: %.*s",
- (int)strcspn(line, "\r\n"), line);
-
- continue;
- }
-
- if (sym && sym_is_choice_value(sym)) {
- struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));
- switch (sym->def[def].tri) {
- case no:
- break;
- case mod:
- if (cs->def[def].tri == yes) {
- conf_warning("%s creates inconsistent choice state", sym->name);
- cs->flags &= ~def_flags;
- }
- break;
- case yes:
- if (cs->def[def].tri != no)
- conf_warning("override: %s changes choice state", sym->name);
- cs->def[def].val = sym;
- break;
- }
- cs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri);
- }
- }
- free(line);
- fclose(in);
- return 0;
-}
-
-int conf_read(const char *name)
-{
- struct symbol *sym;
- int conf_unsaved = 0;
- int i;
-
- conf_set_changed(false);
-
- if (conf_read_simple(name, S_DEF_USER)) {
- sym_calc_value(modules_sym);
- return 1;
- }
-
- sym_calc_value(modules_sym);
-
- for_all_symbols(i, sym) {
- sym_calc_value(sym);
- if (sym_is_choice(sym) || (sym->flags & SYMBOL_NO_WRITE))
- continue;
- if (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) {
- /* check that calculated value agrees with saved value */
- switch (sym->type) {
- case S_BOOLEAN:
- case S_TRISTATE:
- if (sym->def[S_DEF_USER].tri == sym_get_tristate_value(sym))
- continue;
- break;
- default:
- if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val))
- continue;
- break;
- }
- } else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE))
- /* no previous value and not saved */
- continue;
- conf_unsaved++;
- /* maybe print value in verbose mode... */
- }
-
- for_all_symbols(i, sym) {
- if (sym_has_value(sym) && !sym_is_choice_value(sym)) {
- /* Reset values of generates values, so they'll appear
- * as new, if they should become visible, but that
- * doesn't quite work if the Kconfig and the saved
- * configuration disagree.
- */
- if (sym->visible == no && !conf_unsaved)
- sym->flags &= ~SYMBOL_DEF_USER;
- switch (sym->type) {
- case S_STRING:
- case S_INT:
- case S_HEX:
- /* Reset a string value if it's out of range */
- if (sym_string_within_range(sym, sym->def[S_DEF_USER].val))
- break;
- sym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER);
- conf_unsaved++;
- break;
- default:
- break;
- }
- }
- }
-
- if (conf_warnings || conf_unsaved)
- conf_set_changed(true);
-
- return 0;
-}
-
-struct comment_style {
- const char *decoration;
- const char *prefix;
- const char *postfix;
-};
-
-static const struct comment_style comment_style_pound = {
- .decoration = "#",
- .prefix = "#",
- .postfix = "#",
-};
-
-static const struct comment_style comment_style_c = {
- .decoration = " *",
- .prefix = "/*",
- .postfix = " */",
-};
-
-static void conf_write_heading(FILE *fp, const struct comment_style *cs)
-{
- if (!cs)
- return;
-
- fprintf(fp, "%s\n", cs->prefix);
-
- fprintf(fp, "%s Automatically generated file; DO NOT EDIT.\n",
- cs->decoration);
-
- fprintf(fp, "%s %s\n", cs->decoration, rootmenu.prompt->text);
-
- fprintf(fp, "%s\n", cs->postfix);
-}
-
-/* The returned pointer must be freed on the caller side */
-static char *escape_string_value(const char *in)
-{
- const char *p;
- char *out;
- size_t len;
-
- len = strlen(in) + strlen("\"\"") + 1;
-
- p = in;
- while (1) {
- p += strcspn(p, "\"\\");
-
- if (p[0] == '\0')
- break;
-
- len++;
- p++;
- }
-
- out = xmalloc(len);
- out[0] = '\0';
-
- strcat(out, "\"");
-
- p = in;
- while (1) {
- len = strcspn(p, "\"\\");
- strncat(out, p, len);
- p += len;
-
- if (p[0] == '\0')
- break;
-
- strcat(out, "\\");
- strncat(out, p++, 1);
- }
-
- strcat(out, "\"");
-
- return out;
-}
-
-enum output_n { OUTPUT_N, OUTPUT_N_AS_UNSET, OUTPUT_N_NONE };
-
-static void __print_symbol(FILE *fp, struct symbol *sym, enum output_n output_n,
- bool escape_string)
-{
- const char *val;
- char *escaped = NULL;
-
- if (sym->type == S_UNKNOWN)
- return;
-
- val = sym_get_string_value(sym);
-
- if ((sym->type == S_BOOLEAN || sym->type == S_TRISTATE) &&
- output_n != OUTPUT_N && *val == 'n') {
- if (output_n == OUTPUT_N_AS_UNSET)
- fprintf(fp, "# %s%s is not set\n", CONFIG_, sym->name);
- return;
- }
-
- if (sym->type == S_STRING && escape_string) {
- escaped = escape_string_value(val);
- val = escaped;
- }
-
- fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, val);
-
- free(escaped);
-}
-
-static void print_symbol_for_dotconfig(FILE *fp, struct symbol *sym)
-{
- __print_symbol(fp, sym, OUTPUT_N_AS_UNSET, true);
-}
-
-static void print_symbol_for_autoconf(FILE *fp, struct symbol *sym)
-{
- __print_symbol(fp, sym, OUTPUT_N_NONE, false);
-}
-
-void print_symbol_for_listconfig(struct symbol *sym)
-{
- __print_symbol(stdout, sym, OUTPUT_N, true);
-}
-
-static void print_symbol_for_c(FILE *fp, struct symbol *sym)
-{
- const char *val;
- const char *sym_suffix = "";
- const char *val_prefix = "";
- char *escaped = NULL;
-
- if (sym->type == S_UNKNOWN)
- return;
-
- val = sym_get_string_value(sym);
-
- switch (sym->type) {
- case S_BOOLEAN:
- case S_TRISTATE:
- switch (*val) {
- case 'n':
- return;
- case 'm':
- sym_suffix = "_MODULE";
- /* fall through */
- default:
- val = "1";
- }
- break;
- case S_HEX:
- if (val[0] != '0' || (val[1] != 'x' && val[1] != 'X'))
- val_prefix = "0x";
- break;
- case S_STRING:
- escaped = escape_string_value(val);
- val = escaped;
- default:
- break;
- }
-
- fprintf(fp, "#define %s%s%s %s%s\n", CONFIG_, sym->name, sym_suffix,
- val_prefix, val);
-
- free(escaped);
-}
-
-static void print_symbol_for_rustccfg(FILE *fp, struct symbol *sym)
-{
- const char *val;
- const char *val_prefix = "";
- char *val_prefixed = NULL;
- size_t val_prefixed_len;
- char *escaped = NULL;
-
- if (sym->type == S_UNKNOWN)
- return;
-
- val = sym_get_string_value(sym);
-
- switch (sym->type) {
- case S_BOOLEAN:
- case S_TRISTATE:
- /*
- * We do not care about disabled ones, i.e. no need for
- * what otherwise are "comments" in other printers.
- */
- if (*val == 'n')
- return;
-
- /*
- * To have similar functionality to the C macro `IS_ENABLED()`
- * we provide an empty `--cfg CONFIG_X` here in both `y`
- * and `m` cases.
- *
- * Then, the common `fprintf()` below will also give us
- * a `--cfg CONFIG_X="y"` or `--cfg CONFIG_X="m"`, which can
- * be used as the equivalent of `IS_BUILTIN()`/`IS_MODULE()`.
- */
- fprintf(fp, "--cfg=%s%s\n", CONFIG_, sym->name);
- break;
- case S_HEX:
- if (val[0] != '0' || (val[1] != 'x' && val[1] != 'X'))
- val_prefix = "0x";
- break;
- default:
- break;
- }
-
- if (strlen(val_prefix) > 0) {
- val_prefixed_len = strlen(val) + strlen(val_prefix) + 1;
- val_prefixed = xmalloc(val_prefixed_len);
- snprintf(val_prefixed, val_prefixed_len, "%s%s", val_prefix, val);
- val = val_prefixed;
- }
-
- /* All values get escaped: the `--cfg` option only takes strings */
- escaped = escape_string_value(val);
- val = escaped;
-
- fprintf(fp, "--cfg=%s%s=%s\n", CONFIG_, sym->name, val);
-
- free(escaped);
- free(val_prefixed);
-}
-
-/*
- * Write out a minimal config.
- * All values that has default values are skipped as this is redundant.
- */
-int conf_write_defconfig(const char *filename)
-{
- struct symbol *sym;
- struct menu *menu;
- FILE *out;
-
- out = fopen(filename, "w");
- if (!out)
- return 1;
-
- sym_clear_all_valid();
-
- /* Traverse all menus to find all relevant symbols */
- menu = rootmenu.list;
-
- while (menu != NULL)
- {
- sym = menu->sym;
- if (sym == NULL) {
- if (!menu_is_visible(menu))
- goto next_menu;
- } else if (!sym_is_choice(sym)) {
- sym_calc_value(sym);
- if (!(sym->flags & SYMBOL_WRITE))
- goto next_menu;
- sym->flags &= ~SYMBOL_WRITE;
- /* If we cannot change the symbol - skip */
- if (!sym_is_changeable(sym))
- goto next_menu;
- /* If symbol equals to default value - skip */
- if (strcmp(sym_get_string_value(sym), sym_get_string_default(sym)) == 0)
- goto next_menu;
-
- /*
- * If symbol is a choice value and equals to the
- * default for a choice - skip.
- * But only if value is bool and equal to "y" and
- * choice is not "optional".
- * (If choice is "optional" then all values can be "n")
- */
- if (sym_is_choice_value(sym)) {
- struct symbol *cs;
- struct symbol *ds;
-
- cs = prop_get_symbol(sym_get_choice_prop(sym));
- ds = sym_choice_default(cs);
- if (!sym_is_optional(cs) && sym == ds) {
- if ((sym->type == S_BOOLEAN) &&
- sym_get_tristate_value(sym) == yes)
- goto next_menu;
- }
- }
- print_symbol_for_dotconfig(out, sym);
- }
-next_menu:
- if (menu->list != NULL) {
- menu = menu->list;
- }
- else if (menu->next != NULL) {
- menu = menu->next;
- } else {
- while ((menu = menu->parent)) {
- if (menu->next != NULL) {
- menu = menu->next;
- break;
- }
- }
- }
- }
- fclose(out);
- return 0;
-}
-
-int conf_write(const char *name)
-{
- FILE *out;
- struct symbol *sym;
- struct menu *menu;
- const char *str;
- char tmpname[PATH_MAX + 1], oldname[PATH_MAX + 1];
- char *env;
- int i;
- bool need_newline = false;
-
- if (!name)
- name = conf_get_configname();
-
- if (!*name) {
- fprintf(stderr, "config name is empty\n");
- return -1;
- }
-
- if (is_dir(name)) {
- fprintf(stderr, "%s: Is a directory\n", name);
- return -1;
- }
-
- if (make_parent_dir(name))
- return -1;
-
- env = getenv("KCONFIG_OVERWRITECONFIG");
- if (env && *env) {
- *tmpname = 0;
- out = fopen(name, "w");
- } else {
- snprintf(tmpname, sizeof(tmpname), "%s.%d.tmp",
- name, (int)getpid());
- out = fopen(tmpname, "w");
- }
- if (!out)
- return 1;
-
- conf_write_heading(out, &comment_style_pound);
-
- if (!conf_get_changed())
- sym_clear_all_valid();
-
- menu = rootmenu.list;
- while (menu) {
- sym = menu->sym;
- if (!sym) {
- if (!menu_is_visible(menu))
- goto next;
- str = menu_get_prompt(menu);
- fprintf(out, "\n"
- "#\n"
- "# %s\n"
- "#\n", str);
- need_newline = false;
- } else if (!(sym->flags & SYMBOL_CHOICE) &&
- !(sym->flags & SYMBOL_WRITTEN)) {
- sym_calc_value(sym);
- if (!(sym->flags & SYMBOL_WRITE))
- goto next;
- if (need_newline) {
- fprintf(out, "\n");
- need_newline = false;
- }
- sym->flags |= SYMBOL_WRITTEN;
- print_symbol_for_dotconfig(out, sym);
- }
-
-next:
- if (menu->list) {
- menu = menu->list;
- continue;
- }
-
-end_check:
- if (!menu->sym && menu_is_visible(menu) && menu != &rootmenu &&
- menu->prompt->type == P_MENU) {
- fprintf(out, "# end of %s\n", menu_get_prompt(menu));
- need_newline = true;
- }
-
- if (menu->next) {
- menu = menu->next;
- } else {
- menu = menu->parent;
- if (menu)
- goto end_check;
- }
- }
- fclose(out);
-
- for_all_symbols(i, sym)
- sym->flags &= ~SYMBOL_WRITTEN;
-
- if (*tmpname) {
- if (is_same(name, tmpname)) {
- conf_message("No change to %s", name);
- unlink(tmpname);
- conf_set_changed(false);
- return 0;
- }
-
- snprintf(oldname, sizeof(oldname), "%s.old", name);
- rename(name, oldname);
- if (rename(tmpname, name))
- return 1;
- }
-
- conf_message("configuration written to %s", name);
-
- conf_set_changed(false);
-
- return 0;
-}
-
-/* write a dependency file as used by kbuild to track dependencies */
-static int conf_write_autoconf_cmd(const char *autoconf_name)
-{
- char name[PATH_MAX], tmp[PATH_MAX];
- struct file *file;
- FILE *out;
- int ret;
-
- ret = snprintf(name, sizeof(name), "%s.cmd", autoconf_name);
- if (ret >= sizeof(name)) /* check truncation */
- return -1;
-
- if (make_parent_dir(name))
- return -1;
-
- ret = snprintf(tmp, sizeof(tmp), "%s.cmd.tmp", autoconf_name);
- if (ret >= sizeof(tmp)) /* check truncation */
- return -1;
-
- out = fopen(tmp, "w");
- if (!out) {
- perror("fopen");
- return -1;
- }
-
- fprintf(out, "deps_config := \\\n");
- for (file = file_list; file; file = file->next)
- fprintf(out, "\t%s \\\n", file->name);
-
- fprintf(out, "\n%s: $(deps_config)\n\n", autoconf_name);
-
- env_write_dep(out, autoconf_name);
-
- fprintf(out, "\n$(deps_config): ;\n");
-
- fflush(out);
- ret = ferror(out); /* error check for all fprintf() calls */
- fclose(out);
- if (ret)
- return -1;
-
- if (rename(tmp, name)) {
- perror("rename");
- return -1;
- }
-
- return 0;
-}
-
-static int conf_touch_deps(void)
-{
- const char *name, *tmp;
- struct symbol *sym;
- int res, i;
-
- name = conf_get_autoconfig_name();
- tmp = strrchr(name, '/');
- depfile_prefix_len = tmp ? tmp - name + 1 : 0;
- if (depfile_prefix_len + 1 > sizeof(depfile_path))
- return -1;
-
- strncpy(depfile_path, name, depfile_prefix_len);
- depfile_path[depfile_prefix_len] = 0;
-
- conf_read_simple(name, S_DEF_AUTO);
- sym_calc_value(modules_sym);
-
- for_all_symbols(i, sym) {
- sym_calc_value(sym);
- if ((sym->flags & SYMBOL_NO_WRITE) || !sym->name)
- continue;
- if (sym->flags & SYMBOL_WRITE) {
- if (sym->flags & SYMBOL_DEF_AUTO) {
- /*
- * symbol has old and new value,
- * so compare them...
- */
- switch (sym->type) {
- case S_BOOLEAN:
- case S_TRISTATE:
- if (sym_get_tristate_value(sym) ==
- sym->def[S_DEF_AUTO].tri)
- continue;
- break;
- case S_STRING:
- case S_HEX:
- case S_INT:
- if (!strcmp(sym_get_string_value(sym),
- sym->def[S_DEF_AUTO].val))
- continue;
- break;
- default:
- break;
- }
- } else {
- /*
- * If there is no old value, only 'no' (unset)
- * is allowed as new value.
- */
- switch (sym->type) {
- case S_BOOLEAN:
- case S_TRISTATE:
- if (sym_get_tristate_value(sym) == no)
- continue;
- break;
- default:
- break;
- }
- }
- } else if (!(sym->flags & SYMBOL_DEF_AUTO))
- /* There is neither an old nor a new value. */
- continue;
- /* else
- * There is an old value, but no new value ('no' (unset)
- * isn't saved in auto.conf, so the old value is always
- * different from 'no').
- */
-
- res = conf_touch_dep(sym->name);
- if (res)
- return res;
- }
-
- return 0;
-}
-
-static int __conf_write_autoconf(const char *filename,
- void (*print_symbol)(FILE *, struct symbol *),
- const struct comment_style *comment_style)
-{
- char tmp[PATH_MAX];
- FILE *file;
- struct symbol *sym;
- int ret, i;
-
- if (make_parent_dir(filename))
- return -1;
-
- ret = snprintf(tmp, sizeof(tmp), "%s.tmp", filename);
- if (ret >= sizeof(tmp)) /* check truncation */
- return -1;
-
- file = fopen(tmp, "w");
- if (!file) {
- perror("fopen");
- return -1;
- }
-
- conf_write_heading(file, comment_style);
-
- for_all_symbols(i, sym)
- if ((sym->flags & SYMBOL_WRITE) && sym->name)
- print_symbol(file, sym);
-
- fflush(file);
- /* check possible errors in conf_write_heading() and print_symbol() */
- ret = ferror(file);
- fclose(file);
- if (ret)
- return -1;
-
- if (rename(tmp, filename)) {
- perror("rename");
- return -1;
- }
-
- return 0;
-}
-
-int conf_write_autoconf(int overwrite)
-{
- struct symbol *sym;
- const char *autoconf_name = conf_get_autoconfig_name();
- int ret, i;
-
- if (!overwrite && is_present(autoconf_name))
- return 0;
-
- ret = conf_write_autoconf_cmd(autoconf_name);
- if (ret)
- return -1;
-
- if (conf_touch_deps())
- return 1;
-
- for_all_symbols(i, sym)
- sym_calc_value(sym);
-
- ret = __conf_write_autoconf(conf_get_autoheader_name(),
- print_symbol_for_c,
- &comment_style_c);
- if (ret)
- return ret;
-
- ret = __conf_write_autoconf(conf_get_rustccfg_name(),
- print_symbol_for_rustccfg,
- NULL);
- if (ret)
- return ret;
-
- /*
- * Create include/config/auto.conf. This must be the last step because
- * Kbuild has a dependency on auto.conf and this marks the successful
- * completion of the previous steps.
- */
- ret = __conf_write_autoconf(conf_get_autoconfig_name(),
- print_symbol_for_autoconf,
- &comment_style_pound);
- if (ret)
- return ret;
-
- return 0;
-}
-
-static bool conf_changed;
-static void (*conf_changed_callback)(void);
-
-void conf_set_changed(bool val)
-{
- bool changed = conf_changed != val;
-
- conf_changed = val;
-
- if (conf_changed_callback && changed)
- conf_changed_callback();
-}
-
-bool conf_get_changed(void)
-{
- return conf_changed;
-}
-
-void conf_set_changed_callback(void (*fn)(void))
-{
- conf_changed_callback = fn;
-}
-
-void set_all_choice_values(struct symbol *csym)
-{
- struct property *prop;
- struct symbol *sym;
- struct expr *e;
-
- prop = sym_get_choice_prop(csym);
-
- /*
- * Set all non-assinged choice values to no
- */
- expr_list_for_each_sym(prop->expr, e, sym) {
- if (!sym_has_value(sym))
- sym->def[S_DEF_USER].tri = no;
- }
- csym->flags |= SYMBOL_DEF_USER;
- /* clear VALID to get value calculated */
- csym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES);
-}
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/conf.c
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/conf.c (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/scripts/kconfig/conf.c (nonexistent)
@@ -1,921 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
- */
-
-#include <ctype.h>
-#include <linux/limits.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-#include <getopt.h>
-#include <sys/time.h>
-#include <errno.h>
-
-#include "lkc.h"
-
-static void conf(struct menu *menu);
-static void check_conf(struct menu *menu);
-
-enum input_mode {
- oldaskconfig,
- syncconfig,
- oldconfig,
- allnoconfig,
- allyesconfig,
- allmodconfig,
- alldefconfig,
- randconfig,
- defconfig,
- savedefconfig,
- listnewconfig,
- helpnewconfig,
- olddefconfig,
- yes2modconfig,
- mod2yesconfig,
- mod2noconfig,
-};
-static enum input_mode input_mode = oldaskconfig;
-static int input_mode_opt;
-static int indent = 1;
-static int tty_stdio;
-static int sync_kconfig;
-static int conf_cnt;
-static char line[PATH_MAX];
-static struct menu *rootEntry;
-
-static void print_help(struct menu *menu)
-{
- struct gstr help = str_new();
-
- menu_get_ext_help(menu, &help);
-
- printf("\n%s\n", str_get(&help));
- str_free(&help);
-}
-
-static void strip(char *str)
-{
- char *p = str;
- int l;
-
- while ((isspace(*p)))
- p++;
- l = strlen(p);
- if (p != str)
- memmove(str, p, l + 1);
- if (!l)
- return;
- p = str + l - 1;
- while ((isspace(*p)))
- *p-- = 0;
-}
-
-/* Helper function to facilitate fgets() by Jean Sacren. */
-static void xfgets(char *str, int size, FILE *in)
-{
- if (!fgets(str, size, in))
- fprintf(stderr, "\nError in reading or end of file.\n");
-
- if (!tty_stdio)
- printf("%s", str);
-}
-
-static void set_randconfig_seed(void)
-{
- unsigned int seed;
- char *env;
- bool seed_set = false;
-
- env = getenv("KCONFIG_SEED");
- if (env && *env) {
- char *endp;
-
- seed = strtol(env, &endp, 0);
- if (*endp == '\0')
- seed_set = true;
- }
-
- if (!seed_set) {
- struct timeval now;
-
- /*
- * Use microseconds derived seed, compensate for systems where it may
- * be zero.
- */
- gettimeofday(&now, NULL);
- seed = (now.tv_sec + 1) * (now.tv_usec + 1);
- }
-
- printf("KCONFIG_SEED=0x%X\n", seed);
- srand(seed);
-}
-
-static bool randomize_choice_values(struct symbol *csym)
-{
- struct property *prop;
- struct symbol *sym;
- struct expr *e;
- int cnt, def;
-
- /*
- * If choice is mod then we may have more items selected
- * and if no then no-one.
- * In both cases stop.
- */
- if (csym->curr.tri != yes)
- return false;
-
- prop = sym_get_choice_prop(csym);
-
- /* count entries in choice block */
- cnt = 0;
- expr_list_for_each_sym(prop->expr, e, sym)
- cnt++;
-
- /*
- * find a random value and set it to yes,
- * set the rest to no so we have only one set
- */
- def = rand() % cnt;
-
- cnt = 0;
- expr_list_for_each_sym(prop->expr, e, sym) {
- if (def == cnt++) {
- sym->def[S_DEF_USER].tri = yes;
- csym->def[S_DEF_USER].val = sym;
- } else {
- sym->def[S_DEF_USER].tri = no;
- }
- sym->flags |= SYMBOL_DEF_USER;
- /* clear VALID to get value calculated */
- sym->flags &= ~SYMBOL_VALID;
- }
- csym->flags |= SYMBOL_DEF_USER;
- /* clear VALID to get value calculated */
- csym->flags &= ~SYMBOL_VALID;
-
- return true;
-}
-
-enum conf_def_mode {
- def_default,
- def_yes,
- def_mod,
- def_no,
- def_random
-};
-
-static bool conf_set_all_new_symbols(enum conf_def_mode mode)
-{
- struct symbol *sym, *csym;
- int i, cnt;
- /*
- * can't go as the default in switch-case below, otherwise gcc whines
- * about -Wmaybe-uninitialized
- */
- int pby = 50; /* probability of bool = y */
- int pty = 33; /* probability of tristate = y */
- int ptm = 33; /* probability of tristate = m */
- bool has_changed = false;
-
- if (mode == def_random) {
- int n, p[3];
- char *env = getenv("KCONFIG_PROBABILITY");
-
- n = 0;
- while (env && *env) {
- char *endp;
- int tmp = strtol(env, &endp, 10);
-
- if (tmp >= 0 && tmp <= 100) {
- p[n++] = tmp;
- } else {
- errno = ERANGE;
- perror("KCONFIG_PROBABILITY");
- exit(1);
- }
- env = (*endp == ':') ? endp + 1 : endp;
- if (n >= 3)
- break;
- }
- switch (n) {
- case 1:
- pby = p[0];
- ptm = pby / 2;
- pty = pby - ptm;
- break;
- case 2:
- pty = p[0];
- ptm = p[1];
- pby = pty + ptm;
- break;
- case 3:
- pby = p[0];
- pty = p[1];
- ptm = p[2];
- break;
- }
-
- if (pty + ptm > 100) {
- errno = ERANGE;
- perror("KCONFIG_PROBABILITY");
- exit(1);
- }
- }
-
- for_all_symbols(i, sym) {
- if (sym_has_value(sym) || sym->flags & SYMBOL_VALID)
- continue;
- switch (sym_get_type(sym)) {
- case S_BOOLEAN:
- case S_TRISTATE:
- has_changed = true;
- switch (mode) {
- case def_yes:
- sym->def[S_DEF_USER].tri = yes;
- break;
- case def_mod:
- sym->def[S_DEF_USER].tri = mod;
- break;
- case def_no:
- sym->def[S_DEF_USER].tri = no;
- break;
- case def_random:
- sym->def[S_DEF_USER].tri = no;
- cnt = rand() % 100;
- if (sym->type == S_TRISTATE) {
- if (cnt < pty)
- sym->def[S_DEF_USER].tri = yes;
- else if (cnt < pty + ptm)
- sym->def[S_DEF_USER].tri = mod;
- } else if (cnt < pby)
- sym->def[S_DEF_USER].tri = yes;
- break;
- default:
- continue;
- }
- if (!(sym_is_choice(sym) && mode == def_random))
- sym->flags |= SYMBOL_DEF_USER;
- break;
- default:
- break;
- }
-
- }
-
- sym_clear_all_valid();
-
- /*
- * We have different type of choice blocks.
- * If curr.tri equals to mod then we can select several
- * choice symbols in one block.
- * In this case we do nothing.
- * If curr.tri equals yes then only one symbol can be
- * selected in a choice block and we set it to yes,
- * and the rest to no.
- */
- if (mode != def_random) {
- for_all_symbols(i, csym) {
- if ((sym_is_choice(csym) && !sym_has_value(csym)) ||
- sym_is_choice_value(csym))
- csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES;
- }
- }
-
- for_all_symbols(i, csym) {
- if (sym_has_value(csym) || !sym_is_choice(csym))
- continue;
-
- sym_calc_value(csym);
- if (mode == def_random)
- has_changed |= randomize_choice_values(csym);
- else {
- set_all_choice_values(csym);
- has_changed = true;
- }
- }
-
- return has_changed;
-}
-
-static void conf_rewrite_tristates(tristate old_val, tristate new_val)
-{
- struct symbol *sym;
- int i;
-
- for_all_symbols(i, sym) {
- if (sym_get_type(sym) == S_TRISTATE &&
- sym->def[S_DEF_USER].tri == old_val)
- sym->def[S_DEF_USER].tri = new_val;
- }
- sym_clear_all_valid();
-}
-
-static int conf_askvalue(struct symbol *sym, const char *def)
-{
- if (!sym_has_value(sym))
- printf("(NEW) ");
-
- line[0] = '\n';
- line[1] = 0;
-
- if (!sym_is_changeable(sym)) {
- printf("%s\n", def);
- line[0] = '\n';
- line[1] = 0;
- return 0;
- }
-
- switch (input_mode) {
- case oldconfig:
- case syncconfig:
- if (sym_has_value(sym)) {
- printf("%s\n", def);
- return 0;
- }
- /* fall through */
- default:
- fflush(stdout);
- xfgets(line, sizeof(line), stdin);
- break;
- }
-
- return 1;
-}
-
-static int conf_string(struct menu *menu)
-{
- struct symbol *sym = menu->sym;
- const char *def;
-
- while (1) {
- printf("%*s%s ", indent - 1, "", menu->prompt->text);
- printf("(%s) ", sym->name);
- def = sym_get_string_value(sym);
- if (def)
- printf("[%s] ", def);
- if (!conf_askvalue(sym, def))
- return 0;
- switch (line[0]) {
- case '\n':
- break;
- case '?':
- /* print help */
- if (line[1] == '\n') {
- print_help(menu);
- def = NULL;
- break;
- }
- /* fall through */
- default:
- line[strlen(line)-1] = 0;
- def = line;
- }
- if (def && sym_set_string_value(sym, def))
- return 0;
- }
-}
-
-static int conf_sym(struct menu *menu)
-{
- struct symbol *sym = menu->sym;
- tristate oldval, newval;
-
- while (1) {
- printf("%*s%s ", indent - 1, "", menu->prompt->text);
- if (sym->name)
- printf("(%s) ", sym->name);
- putchar('[');
- oldval = sym_get_tristate_value(sym);
- switch (oldval) {
- case no:
- putchar('N');
- break;
- case mod:
- putchar('M');
- break;
- case yes:
- putchar('Y');
- break;
- }
- if (oldval != no && sym_tristate_within_range(sym, no))
- printf("/n");
- if (oldval != mod && sym_tristate_within_range(sym, mod))
- printf("/m");
- if (oldval != yes && sym_tristate_within_range(sym, yes))
- printf("/y");
- printf("/?] ");
- if (!conf_askvalue(sym, sym_get_string_value(sym)))
- return 0;
- strip(line);
-
- switch (line[0]) {
- case 'n':
- case 'N':
- newval = no;
- if (!line[1] || !strcmp(&line[1], "o"))
- break;
- continue;
- case 'm':
- case 'M':
- newval = mod;
- if (!line[1])
- break;
- continue;
- case 'y':
- case 'Y':
- newval = yes;
- if (!line[1] || !strcmp(&line[1], "es"))
- break;
- continue;
- case 0:
- newval = oldval;
- break;
- case '?':
- goto help;
- default:
- continue;
- }
- if (sym_set_tristate_value(sym, newval))
- return 0;
-help:
- print_help(menu);
- }
-}
-
-static int conf_choice(struct menu *menu)
-{
- struct symbol *sym, *def_sym;
- struct menu *child;
- bool is_new;
-
- sym = menu->sym;
- is_new = !sym_has_value(sym);
- if (sym_is_changeable(sym)) {
- conf_sym(menu);
- sym_calc_value(sym);
- switch (sym_get_tristate_value(sym)) {
- case no:
- return 1;
- case mod:
- return 0;
- case yes:
- break;
- }
- } else {
- switch (sym_get_tristate_value(sym)) {
- case no:
- return 1;
- case mod:
- printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu));
- return 0;
- case yes:
- break;
- }
- }
-
- while (1) {
- int cnt, def;
-
- printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu));
- def_sym = sym_get_choice_value(sym);
- cnt = def = 0;
- line[0] = 0;
- for (child = menu->list; child; child = child->next) {
- if (!menu_is_visible(child))
- continue;
- if (!child->sym) {
- printf("%*c %s\n", indent, '*', menu_get_prompt(child));
- continue;
- }
- cnt++;
- if (child->sym == def_sym) {
- def = cnt;
- printf("%*c", indent, '>');
- } else
- printf("%*c", indent, ' ');
- printf(" %d. %s", cnt, menu_get_prompt(child));
- if (child->sym->name)
- printf(" (%s)", child->sym->name);
- if (!sym_has_value(child->sym))
- printf(" (NEW)");
- printf("\n");
- }
- printf("%*schoice", indent - 1, "");
- if (cnt == 1) {
- printf("[1]: 1\n");
- goto conf_childs;
- }
- printf("[1-%d?]: ", cnt);
- switch (input_mode) {
- case oldconfig:
- case syncconfig:
- if (!is_new) {
- cnt = def;
- printf("%d\n", cnt);
- break;
- }
- /* fall through */
- case oldaskconfig:
- fflush(stdout);
- xfgets(line, sizeof(line), stdin);
- strip(line);
- if (line[0] == '?') {
- print_help(menu);
- continue;
- }
- if (!line[0])
- cnt = def;
- else if (isdigit(line[0]))
- cnt = atoi(line);
- else
- continue;
- break;
- default:
- break;
- }
-
- conf_childs:
- for (child = menu->list; child; child = child->next) {
- if (!child->sym || !menu_is_visible(child))
- continue;
- if (!--cnt)
- break;
- }
- if (!child)
- continue;
- if (line[0] && line[strlen(line) - 1] == '?') {
- print_help(child);
- continue;
- }
- sym_set_tristate_value(child->sym, yes);
- for (child = child->list; child; child = child->next) {
- indent += 2;
- conf(child);
- indent -= 2;
- }
- return 1;
- }
-}
-
-static void conf(struct menu *menu)
-{
- struct symbol *sym;
- struct property *prop;
- struct menu *child;
-
- if (!menu_is_visible(menu))
- return;
-
- sym = menu->sym;
- prop = menu->prompt;
- if (prop) {
- const char *prompt;
-
- switch (prop->type) {
- case P_MENU:
- /*
- * Except in oldaskconfig mode, we show only menus that
- * contain new symbols.
- */
- if (input_mode != oldaskconfig && rootEntry != menu) {
- check_conf(menu);
- return;
- }
- /* fall through */
- case P_COMMENT:
- prompt = menu_get_prompt(menu);
- if (prompt)
- printf("%*c\n%*c %s\n%*c\n",
- indent, '*',
- indent, '*', prompt,
- indent, '*');
- default:
- ;
- }
- }
-
- if (!sym)
- goto conf_childs;
-
- if (sym_is_choice(sym)) {
- conf_choice(menu);
- if (sym->curr.tri != mod)
- return;
- goto conf_childs;
- }
-
- switch (sym->type) {
- case S_INT:
- case S_HEX:
- case S_STRING:
- conf_string(menu);
- break;
- default:
- conf_sym(menu);
- break;
- }
-
-conf_childs:
- if (sym)
- indent += 2;
- for (child = menu->list; child; child = child->next)
- conf(child);
- if (sym)
- indent -= 2;
-}
-
-static void check_conf(struct menu *menu)
-{
- struct symbol *sym;
- struct menu *child;
-
- if (!menu_is_visible(menu))
- return;
-
- sym = menu->sym;
- if (sym && !sym_has_value(sym) &&
- (sym_is_changeable(sym) ||
- (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes))) {
-
- switch (input_mode) {
- case listnewconfig:
- if (sym->name)
- print_symbol_for_listconfig(sym);
- break;
- case helpnewconfig:
- printf("-----\n");
- print_help(menu);
- printf("-----\n");
- break;
- default:
- if (!conf_cnt++)
- printf("*\n* Restart config...\n*\n");
- rootEntry = menu_get_parent_menu(menu);
- conf(rootEntry);
- break;
- }
- }
-
- for (child = menu->list; child; child = child->next)
- check_conf(child);
-}
-
-static const struct option long_opts[] = {
- {"help", no_argument, NULL, 'h'},
- {"silent", no_argument, NULL, 's'},
- {"oldaskconfig", no_argument, &input_mode_opt, oldaskconfig},
- {"oldconfig", no_argument, &input_mode_opt, oldconfig},
- {"syncconfig", no_argument, &input_mode_opt, syncconfig},
- {"defconfig", required_argument, &input_mode_opt, defconfig},
- {"savedefconfig", required_argument, &input_mode_opt, savedefconfig},
- {"allnoconfig", no_argument, &input_mode_opt, allnoconfig},
- {"allyesconfig", no_argument, &input_mode_opt, allyesconfig},
- {"allmodconfig", no_argument, &input_mode_opt, allmodconfig},
- {"alldefconfig", no_argument, &input_mode_opt, alldefconfig},
- {"randconfig", no_argument, &input_mode_opt, randconfig},
- {"listnewconfig", no_argument, &input_mode_opt, listnewconfig},
- {"helpnewconfig", no_argument, &input_mode_opt, helpnewconfig},
- {"olddefconfig", no_argument, &input_mode_opt, olddefconfig},
- {"yes2modconfig", no_argument, &input_mode_opt, yes2modconfig},
- {"mod2yesconfig", no_argument, &input_mode_opt, mod2yesconfig},
- {"mod2noconfig", no_argument, &input_mode_opt, mod2noconfig},
- {NULL, 0, NULL, 0}
-};
-
-static void conf_usage(const char *progname)
-{
- printf("Usage: %s [options] <kconfig-file>\n", progname);
- printf("\n");
- printf("Generic options:\n");
- printf(" -h, --help Print this message and exit.\n");
- printf(" -s, --silent Do not print log.\n");
- printf("\n");
- printf("Mode options:\n");
- printf(" --listnewconfig List new options\n");
- printf(" --helpnewconfig List new options and help text\n");
- printf(" --oldaskconfig Start a new configuration using a line-oriented program\n");
- printf(" --oldconfig Update a configuration using a provided .config as base\n");
- printf(" --syncconfig Similar to oldconfig but generates configuration in\n"
- " include/{generated/,config/}\n");
- printf(" --olddefconfig Same as oldconfig but sets new symbols to their default value\n");
- printf(" --defconfig <file> New config with default defined in <file>\n");
- printf(" --savedefconfig <file> Save the minimal current configuration to <file>\n");
- printf(" --allnoconfig New config where all options are answered with no\n");
- printf(" --allyesconfig New config where all options are answered with yes\n");
- printf(" --allmodconfig New config where all options are answered with mod\n");
- printf(" --alldefconfig New config with all symbols set to default\n");
- printf(" --randconfig New config with random answer to all options\n");
- printf(" --yes2modconfig Change answers from yes to mod if possible\n");
- printf(" --mod2yesconfig Change answers from mod to yes if possible\n");
- printf(" --mod2noconfig Change answers from mod to no if possible\n");
- printf(" (If none of the above is given, --oldaskconfig is the default)\n");
-}
-
-int main(int ac, char **av)
-{
- const char *progname = av[0];
- int opt;
- const char *name, *defconfig_file = NULL /* gcc uninit */;
- int no_conf_write = 0;
-
- tty_stdio = isatty(0) && isatty(1);
-
- while ((opt = getopt_long(ac, av, "hs", long_opts, NULL)) != -1) {
- switch (opt) {
- case 'h':
- conf_usage(progname);
- exit(1);
- break;
- case 's':
- conf_set_message_callback(NULL);
- break;
- case 0:
- input_mode = input_mode_opt;
- switch (input_mode) {
- case syncconfig:
- /*
- * syncconfig is invoked during the build stage.
- * Suppress distracting
- * "configuration written to ..."
- */
- conf_set_message_callback(NULL);
- sync_kconfig = 1;
- break;
- case defconfig:
- case savedefconfig:
- defconfig_file = optarg;
- break;
- case randconfig:
- set_randconfig_seed();
- break;
- default:
- break;
- }
- default:
- break;
- }
- }
- if (ac == optind) {
- fprintf(stderr, "%s: Kconfig file missing\n", av[0]);
- conf_usage(progname);
- exit(1);
- }
- conf_parse(av[optind]);
- //zconfdump(stdout);
-
- switch (input_mode) {
- case defconfig:
- if (conf_read(defconfig_file)) {
- fprintf(stderr,
- "***\n"
- "*** Can't find default configuration \"%s\"!\n"
- "***\n",
- defconfig_file);
- exit(1);
- }
- break;
- case savedefconfig:
- case syncconfig:
- case oldaskconfig:
- case oldconfig:
- case listnewconfig:
- case helpnewconfig:
- case olddefconfig:
- case yes2modconfig:
- case mod2yesconfig:
- case mod2noconfig:
- conf_read(NULL);
- break;
- case allnoconfig:
- case allyesconfig:
- case allmodconfig:
- case alldefconfig:
- case randconfig:
- name = getenv("KCONFIG_ALLCONFIG");
- if (!name)
- break;
- if ((strcmp(name, "") != 0) && (strcmp(name, "1") != 0)) {
- if (conf_read_simple(name, S_DEF_USER)) {
- fprintf(stderr,
- "*** Can't read seed configuration \"%s\"!\n",
- name);
- exit(1);
- }
- break;
- }
- switch (input_mode) {
- case allnoconfig: name = "allno.config"; break;
- case allyesconfig: name = "allyes.config"; break;
- case allmodconfig: name = "allmod.config"; break;
- case alldefconfig: name = "alldef.config"; break;
- case randconfig: name = "allrandom.config"; break;
- default: break;
- }
- if (conf_read_simple(name, S_DEF_USER) &&
- conf_read_simple("all.config", S_DEF_USER)) {
- fprintf(stderr,
- "*** KCONFIG_ALLCONFIG set, but no \"%s\" or \"all.config\" file found\n",
- name);
- exit(1);
- }
- break;
- default:
- break;
- }
-
- if (sync_kconfig) {
- name = getenv("KCONFIG_NOSILENTUPDATE");
- if (name && *name) {
- if (conf_get_changed()) {
- fprintf(stderr,
- "\n*** The configuration requires explicit update.\n\n");
- return 1;
- }
- no_conf_write = 1;
- }
- }
-
- switch (input_mode) {
- case allnoconfig:
- conf_set_all_new_symbols(def_no);
- break;
- case allyesconfig:
- conf_set_all_new_symbols(def_yes);
- break;
- case allmodconfig:
- conf_set_all_new_symbols(def_mod);
- break;
- case alldefconfig:
- conf_set_all_new_symbols(def_default);
- break;
- case randconfig:
- /* Really nothing to do in this loop */
- while (conf_set_all_new_symbols(def_random)) ;
- break;
- case defconfig:
- conf_set_all_new_symbols(def_default);
- break;
- case savedefconfig:
- break;
- case yes2modconfig:
- conf_rewrite_tristates(yes, mod);
- break;
- case mod2yesconfig:
- conf_rewrite_tristates(mod, yes);
- break;
- case mod2noconfig:
- conf_rewrite_tristates(mod, no);
- break;
- case oldaskconfig:
- rootEntry = &rootmenu;
- conf(&rootmenu);
- input_mode = oldconfig;
- /* fall through */
- case oldconfig:
- case listnewconfig:
- case helpnewconfig:
- case syncconfig:
- /* Update until a loop caused no more changes */
- do {
- conf_cnt = 0;
- check_conf(&rootmenu);
- } while (conf_cnt);
- break;
- case olddefconfig:
- default:
- break;
- }
-
- if (input_mode == savedefconfig) {
- if (conf_write_defconfig(defconfig_file)) {
- fprintf(stderr, "n*** Error while saving defconfig to: %s\n\n",
- defconfig_file);
- return 1;
- }
- } else if (input_mode != listnewconfig && input_mode != helpnewconfig) {
- if (!no_conf_write && conf_write(NULL)) {
- fprintf(stderr, "\n*** Error during writing of the configuration.\n\n");
- exit(1);
- }
-
- /*
- * Create auto.conf if it does not exist.
- * This prevents GNU Make 4.1 or older from emitting
- * "include/config/auto.conf: No such file or directory"
- * in the top-level Makefile
- *
- * syncconfig always creates or updates auto.conf because it is
- * used during the build.
- */
- if (conf_write_autoconf(sync_kconfig) && sync_kconfig) {
- fprintf(stderr,
- "\n*** Error during sync of the configuration.\n\n");
- return 1;
- }
- }
- return 0;
-}
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/usr/gen_init_cpio.c
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/usr/gen_init_cpio.c (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/usr/gen_init_cpio.c (nonexistent)
@@ -1,682 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <string.h>
-#include <unistd.h>
-#include <time.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <ctype.h>
-#include <linux/limits.h>
-
-/*
- * Original work by Jeff Garzik
- *
- * External file lists, symlink, pipe and fifo support by Thayne Harbaugh
- * Hard link support by Luciano Rocha
- */
-
-#define xstr(s) #s
-#define str(s) xstr(s)
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-
-static unsigned int offset;
-static unsigned int ino = 721;
-static time_t default_mtime;
-static bool do_csum = false;
-
-struct file_handler {
- const char *type;
- int (*handler)(const char *line);
-};
-
-static void push_string(const char *name)
-{
- unsigned int name_len = strlen(name) + 1;
-
- fputs(name, stdout);
- putchar(0);
- offset += name_len;
-}
-
-static void push_pad (void)
-{
- while (offset & 3) {
- putchar(0);
- offset++;
- }
-}
-
-static void push_rest(const char *name)
-{
- unsigned int name_len = strlen(name) + 1;
- unsigned int tmp_ofs;
-
- fputs(name, stdout);
- putchar(0);
- offset += name_len;
-
- tmp_ofs = name_len + 110;
- while (tmp_ofs & 3) {
- putchar(0);
- offset++;
- tmp_ofs++;
- }
-}
-
-static void push_hdr(const char *s)
-{
- fputs(s, stdout);
- offset += 110;
-}
-
-static void cpio_trailer(void)
-{
- char s[256];
- const char name[] = "TRAILER!!!";
-
- sprintf(s, "%s%08X%08X%08lX%08lX%08X%08lX"
- "%08X%08X%08X%08X%08X%08X%08X",
- do_csum ? "070702" : "070701", /* magic */
- 0, /* ino */
- 0, /* mode */
- (long) 0, /* uid */
- (long) 0, /* gid */
- 1, /* nlink */
- (long) 0, /* mtime */
- 0, /* filesize */
- 0, /* major */
- 0, /* minor */
- 0, /* rmajor */
- 0, /* rminor */
- (unsigned)strlen(name)+1, /* namesize */
- 0); /* chksum */
- push_hdr(s);
- push_rest(name);
-
- while (offset % 512) {
- putchar(0);
- offset++;
- }
-}
-
-static int cpio_mkslink(const char *name, const char *target,
- unsigned int mode, uid_t uid, gid_t gid)
-{
- char s[256];
-
- if (name[0] == '/')
- name++;
- sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
- "%08X%08X%08X%08X%08X%08X%08X",
- do_csum ? "070702" : "070701", /* magic */
- ino++, /* ino */
- S_IFLNK | mode, /* mode */
- (long) uid, /* uid */
- (long) gid, /* gid */
- 1, /* nlink */
- (long) default_mtime, /* mtime */
- (unsigned)strlen(target)+1, /* filesize */
- 3, /* major */
- 1, /* minor */
- 0, /* rmajor */
- 0, /* rminor */
- (unsigned)strlen(name) + 1,/* namesize */
- 0); /* chksum */
- push_hdr(s);
- push_string(name);
- push_pad();
- push_string(target);
- push_pad();
- return 0;
-}
-
-static int cpio_mkslink_line(const char *line)
-{
- char name[PATH_MAX + 1];
- char target[PATH_MAX + 1];
- unsigned int mode;
- int uid;
- int gid;
- int rc = -1;
-
- if (5 != sscanf(line, "%" str(PATH_MAX) "s %" str(PATH_MAX) "s %o %d %d", name, target, &mode, &uid, &gid)) {
- fprintf(stderr, "Unrecognized dir format '%s'", line);
- goto fail;
- }
- rc = cpio_mkslink(name, target, mode, uid, gid);
- fail:
- return rc;
-}
-
-static int cpio_mkgeneric(const char *name, unsigned int mode,
- uid_t uid, gid_t gid)
-{
- char s[256];
-
- if (name[0] == '/')
- name++;
- sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
- "%08X%08X%08X%08X%08X%08X%08X",
- do_csum ? "070702" : "070701", /* magic */
- ino++, /* ino */
- mode, /* mode */
- (long) uid, /* uid */
- (long) gid, /* gid */
- 2, /* nlink */
- (long) default_mtime, /* mtime */
- 0, /* filesize */
- 3, /* major */
- 1, /* minor */
- 0, /* rmajor */
- 0, /* rminor */
- (unsigned)strlen(name) + 1,/* namesize */
- 0); /* chksum */
- push_hdr(s);
- push_rest(name);
- return 0;
-}
-
-enum generic_types {
- GT_DIR,
- GT_PIPE,
- GT_SOCK
-};
-
-struct generic_type {
- const char *type;
- mode_t mode;
-};
-
-static const struct generic_type generic_type_table[] = {
- [GT_DIR] = {
- .type = "dir",
- .mode = S_IFDIR
- },
- [GT_PIPE] = {
- .type = "pipe",
- .mode = S_IFIFO
- },
- [GT_SOCK] = {
- .type = "sock",
- .mode = S_IFSOCK
- }
-};
-
-static int cpio_mkgeneric_line(const char *line, enum generic_types gt)
-{
- char name[PATH_MAX + 1];
- unsigned int mode;
- int uid;
- int gid;
- int rc = -1;
-
- if (4 != sscanf(line, "%" str(PATH_MAX) "s %o %d %d", name, &mode, &uid, &gid)) {
- fprintf(stderr, "Unrecognized %s format '%s'",
- line, generic_type_table[gt].type);
- goto fail;
- }
- mode |= generic_type_table[gt].mode;
- rc = cpio_mkgeneric(name, mode, uid, gid);
- fail:
- return rc;
-}
-
-static int cpio_mkdir_line(const char *line)
-{
- return cpio_mkgeneric_line(line, GT_DIR);
-}
-
-static int cpio_mkpipe_line(const char *line)
-{
- return cpio_mkgeneric_line(line, GT_PIPE);
-}
-
-static int cpio_mksock_line(const char *line)
-{
- return cpio_mkgeneric_line(line, GT_SOCK);
-}
-
-static int cpio_mknod(const char *name, unsigned int mode,
- uid_t uid, gid_t gid, char dev_type,
- unsigned int maj, unsigned int min)
-{
- char s[256];
-
- if (dev_type == 'b')
- mode |= S_IFBLK;
- else
- mode |= S_IFCHR;
-
- if (name[0] == '/')
- name++;
- sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
- "%08X%08X%08X%08X%08X%08X%08X",
- do_csum ? "070702" : "070701", /* magic */
- ino++, /* ino */
- mode, /* mode */
- (long) uid, /* uid */
- (long) gid, /* gid */
- 1, /* nlink */
- (long) default_mtime, /* mtime */
- 0, /* filesize */
- 3, /* major */
- 1, /* minor */
- maj, /* rmajor */
- min, /* rminor */
- (unsigned)strlen(name) + 1,/* namesize */
- 0); /* chksum */
- push_hdr(s);
- push_rest(name);
- return 0;
-}
-
-static int cpio_mknod_line(const char *line)
-{
- char name[PATH_MAX + 1];
- unsigned int mode;
- int uid;
- int gid;
- char dev_type;
- unsigned int maj;
- unsigned int min;
- int rc = -1;
-
- if (7 != sscanf(line, "%" str(PATH_MAX) "s %o %d %d %c %u %u",
- name, &mode, &uid, &gid, &dev_type, &maj, &min)) {
- fprintf(stderr, "Unrecognized nod format '%s'", line);
- goto fail;
- }
- rc = cpio_mknod(name, mode, uid, gid, dev_type, maj, min);
- fail:
- return rc;
-}
-
-static int cpio_mkfile_csum(int fd, unsigned long size, uint32_t *csum)
-{
- while (size) {
- unsigned char filebuf[65536];
- ssize_t this_read;
- size_t i, this_size = MIN(size, sizeof(filebuf));
-
- this_read = read(fd, filebuf, this_size);
- if (this_read <= 0 || this_read > this_size)
- return -1;
-
- for (i = 0; i < this_read; i++)
- *csum += filebuf[i];
-
- size -= this_read;
- }
- /* seek back to the start for data segment I/O */
- if (lseek(fd, 0, SEEK_SET) < 0)
- return -1;
-
- return 0;
-}
-
-static int cpio_mkfile(const char *name, const char *location,
- unsigned int mode, uid_t uid, gid_t gid,
- unsigned int nlinks)
-{
- char s[256];
- struct stat buf;
- unsigned long size;
- int file;
- int retval;
- int rc = -1;
- int namesize;
- unsigned int i;
- uint32_t csum = 0;
-
- mode |= S_IFREG;
-
- file = open (location, O_RDONLY);
- if (file < 0) {
- fprintf (stderr, "File %s could not be opened for reading\n", location);
- goto error;
- }
-
- retval = fstat(file, &buf);
- if (retval) {
- fprintf(stderr, "File %s could not be stat()'ed\n", location);
- goto error;
- }
-
- if (buf.st_mtime > 0xffffffff) {
- fprintf(stderr, "%s: Timestamp exceeds maximum cpio timestamp, clipping.\n",
- location);
- buf.st_mtime = 0xffffffff;
- }
-
- if (buf.st_size > 0xffffffff) {
- fprintf(stderr, "%s: Size exceeds maximum cpio file size\n",
- location);
- goto error;
- }
-
- if (do_csum && cpio_mkfile_csum(file, buf.st_size, &csum) < 0) {
- fprintf(stderr, "Failed to checksum file %s\n", location);
- goto error;
- }
-
- size = 0;
- for (i = 1; i <= nlinks; i++) {
- /* data goes on last link */
- if (i == nlinks)
- size = buf.st_size;
-
- if (name[0] == '/')
- name++;
- namesize = strlen(name) + 1;
- sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
- "%08lX%08X%08X%08X%08X%08X%08X",
- do_csum ? "070702" : "070701", /* magic */
- ino, /* ino */
- mode, /* mode */
- (long) uid, /* uid */
- (long) gid, /* gid */
- nlinks, /* nlink */
- (long) buf.st_mtime, /* mtime */
- size, /* filesize */
- 3, /* major */
- 1, /* minor */
- 0, /* rmajor */
- 0, /* rminor */
- namesize, /* namesize */
- size ? csum : 0); /* chksum */
- push_hdr(s);
- push_string(name);
- push_pad();
-
- while (size) {
- unsigned char filebuf[65536];
- ssize_t this_read;
- size_t this_size = MIN(size, sizeof(filebuf));
-
- this_read = read(file, filebuf, this_size);
- if (this_read <= 0 || this_read > this_size) {
- fprintf(stderr, "Can not read %s file\n", location);
- goto error;
- }
-
- if (fwrite(filebuf, this_read, 1, stdout) != 1) {
- fprintf(stderr, "writing filebuf failed\n");
- goto error;
- }
- offset += this_read;
- size -= this_read;
- }
- push_pad();
-
- name += namesize;
- }
- ino++;
- rc = 0;
-
-error:
- if (file >= 0)
- close(file);
- return rc;
-}
-
-static char *cpio_replace_env(char *new_location)
-{
- char expanded[PATH_MAX + 1];
- char *start, *end, *var;
-
- while ((start = strstr(new_location, "${")) &&
- (end = strchr(start + 2, '}'))) {
- *start = *end = 0;
- var = getenv(start + 2);
- snprintf(expanded, sizeof expanded, "%s%s%s",
- new_location, var ? var : "", end + 1);
- strcpy(new_location, expanded);
- }
-
- return new_location;
-}
-
-static int cpio_mkfile_line(const char *line)
-{
- char name[PATH_MAX + 1];
- char *dname = NULL; /* malloc'ed buffer for hard links */
- char location[PATH_MAX + 1];
- unsigned int mode;
- int uid;
- int gid;
- int nlinks = 1;
- int end = 0, dname_len = 0;
- int rc = -1;
-
- if (5 > sscanf(line, "%" str(PATH_MAX) "s %" str(PATH_MAX)
- "s %o %d %d %n",
- name, location, &mode, &uid, &gid, &end)) {
- fprintf(stderr, "Unrecognized file format '%s'", line);
- goto fail;
- }
- if (end && isgraph(line[end])) {
- int len;
- int nend;
-
- dname = malloc(strlen(line));
- if (!dname) {
- fprintf (stderr, "out of memory (%d)\n", dname_len);
- goto fail;
- }
-
- dname_len = strlen(name) + 1;
- memcpy(dname, name, dname_len);
-
- do {
- nend = 0;
- if (sscanf(line + end, "%" str(PATH_MAX) "s %n",
- name, &nend) < 1)
- break;
- len = strlen(name) + 1;
- memcpy(dname + dname_len, name, len);
- dname_len += len;
- nlinks++;
- end += nend;
- } while (isgraph(line[end]));
- } else {
- dname = name;
- }
- rc = cpio_mkfile(dname, cpio_replace_env(location),
- mode, uid, gid, nlinks);
- fail:
- if (dname_len) free(dname);
- return rc;
-}
-
-static void usage(const char *prog)
-{
- fprintf(stderr, "Usage:\n"
- "\t%s [-t <timestamp>] [-c] <cpio_list>\n"
- "\n"
- "<cpio_list> is a file containing newline separated entries that\n"
- "describe the files to be included in the initramfs archive:\n"
- "\n"
- "# a comment\n"
- "file <name> <location> <mode> <uid> <gid> [<hard links>]\n"
- "dir <name> <mode> <uid> <gid>\n"
- "nod <name> <mode> <uid> <gid> <dev_type> <maj> <min>\n"
- "slink <name> <target> <mode> <uid> <gid>\n"
- "pipe <name> <mode> <uid> <gid>\n"
- "sock <name> <mode> <uid> <gid>\n"
- "\n"
- "<name> name of the file/dir/nod/etc in the archive\n"
- "<location> location of the file in the current filesystem\n"
- " expands shell variables quoted with ${}\n"
- "<target> link target\n"
- "<mode> mode/permissions of the file\n"
- "<uid> user id (0=root)\n"
- "<gid> group id (0=root)\n"
- "<dev_type> device type (b=block, c=character)\n"
- "<maj> major number of nod\n"
- "<min> minor number of nod\n"
- "<hard links> space separated list of other links to file\n"
- "\n"
- "example:\n"
- "# A simple initramfs\n"
- "dir /dev 0755 0 0\n"
- "nod /dev/console 0600 0 0 c 5 1\n"
- "dir /root 0700 0 0\n"
- "dir /sbin 0755 0 0\n"
- "file /sbin/kinit /usr/src/klibc/kinit/kinit 0755 0 0\n"
- "\n"
- "<timestamp> is time in seconds since Epoch that will be used\n"
- "as mtime for symlinks, special files and directories. The default\n"
- "is to use the current time for these entries.\n"
- "-c: calculate and store 32-bit checksums for file data.\n",
- prog);
-}
-
-static const struct file_handler file_handler_table[] = {
- {
- .type = "file",
- .handler = cpio_mkfile_line,
- }, {
- .type = "nod",
- .handler = cpio_mknod_line,
- }, {
- .type = "dir",
- .handler = cpio_mkdir_line,
- }, {
- .type = "slink",
- .handler = cpio_mkslink_line,
- }, {
- .type = "pipe",
- .handler = cpio_mkpipe_line,
- }, {
- .type = "sock",
- .handler = cpio_mksock_line,
- }, {
- .type = NULL,
- .handler = NULL,
- }
-};
-
-#define LINE_SIZE (2 * PATH_MAX + 50)
-
-int main (int argc, char *argv[])
-{
- FILE *cpio_list;
- char line[LINE_SIZE];
- char *args, *type;
- int ec = 0;
- int line_nr = 0;
- const char *filename;
-
- default_mtime = time(NULL);
- while (1) {
- int opt = getopt(argc, argv, "t:ch");
- char *invalid;
-
- if (opt == -1)
- break;
- switch (opt) {
- case 't':
- default_mtime = strtol(optarg, &invalid, 10);
- if (!*optarg || *invalid) {
- fprintf(stderr, "Invalid timestamp: %s\n",
- optarg);
- usage(argv[0]);
- exit(1);
- }
- break;
- case 'c':
- do_csum = true;
- break;
- case 'h':
- case '?':
- usage(argv[0]);
- exit(opt == 'h' ? 0 : 1);
- }
- }
-
- /*
- * Timestamps after 2106-02-07 06:28:15 UTC have an ascii hex time_t
- * representation that exceeds 8 chars and breaks the cpio header
- * specification.
- */
- if (default_mtime > 0xffffffff) {
- fprintf(stderr, "ERROR: Timestamp too large for cpio format\n");
- exit(1);
- }
-
- if (argc - optind != 1) {
- usage(argv[0]);
- exit(1);
- }
- filename = argv[optind];
- if (!strcmp(filename, "-"))
- cpio_list = stdin;
- else if (!(cpio_list = fopen(filename, "r"))) {
- fprintf(stderr, "ERROR: unable to open '%s': %s\n\n",
- filename, strerror(errno));
- usage(argv[0]);
- exit(1);
- }
-
- while (fgets(line, LINE_SIZE, cpio_list)) {
- int type_idx;
- size_t slen = strlen(line);
-
- line_nr++;
-
- if ('#' == *line) {
- /* comment - skip to next line */
- continue;
- }
-
- if (! (type = strtok(line, " \t"))) {
- fprintf(stderr,
- "ERROR: incorrect format, could not locate file type line %d: '%s'\n",
- line_nr, line);
- ec = -1;
- break;
- }
-
- if ('\n' == *type) {
- /* a blank line */
- continue;
- }
-
- if (slen == strlen(type)) {
- /* must be an empty line */
- continue;
- }
-
- if (! (args = strtok(NULL, "\n"))) {
- fprintf(stderr,
- "ERROR: incorrect format, newline required line %d: '%s'\n",
- line_nr, line);
- ec = -1;
- }
-
- for (type_idx = 0; file_handler_table[type_idx].type; type_idx++) {
- int rc;
- if (! strcmp(line, file_handler_table[type_idx].type)) {
- if ((rc = file_handler_table[type_idx].handler(args))) {
- ec = rc;
- fprintf(stderr, " line %d\n", line_nr);
- }
- break;
- }
- }
-
- if (NULL == file_handler_table[type_idx].type) {
- fprintf(stderr, "unknown file type line %d: '%s'\n",
- line_nr, line);
- }
- }
- if (ec == 0)
- cpio_trailer();
-
- exit(ec);
-}
Index: v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/tools/build/fixdep.c
===================================================================
--- v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/tools/build/fixdep.c (revision 150)
+++ v6.x/create-6.1.26-host-limits-patch/linux-6.1.26-new/tools/build/fixdep.c (nonexistent)
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * "Optimize" a list of dependencies as spit out by gcc -MD
- * for the build framework.
- *
- * Original author:
- * Copyright 2002 by Kai Germaschewski <kai.germaschewski@gmx.de>
- *
- * This code has been borrowed from kbuild's fixdep (scripts/basic/fixdep.c),
- * Please check it for detailed explanation. This fixdep borow only the
- * base transformation of dependecies without the CONFIG mangle.
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <string.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <linux/limits.h>
-
-char *target;
-char *depfile;
-char *cmdline;
-
-static void usage(void)
-{
- fprintf(stderr, "Usage: fixdep <depfile> <target> <cmdline>\n");
- exit(1);
-}
-
-/*
- * Print out the commandline prefixed with cmd_<target filename> :=
- */
-static void print_cmdline(void)
-{
- printf("cmd_%s := %s\n\n", target, cmdline);
-}
-
-/*
- * Important: The below generated source_foo.o and deps_foo.o variable
- * assignments are parsed not only by make, but also by the rather simple
- * parser in scripts/mod/sumversion.c.
- */
-static void parse_dep_file(void *map, size_t len)
-{
- char *m = map;
- char *end = m + len;
- char *p;
- char s[PATH_MAX];
- int is_target, has_target = 0;
- int saw_any_target = 0;
- int is_first_dep = 0;
-
- while (m < end) {
- /* Skip any "white space" */
- while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
- m++;
- /* Find next "white space" */
- p = m;
- while (p < end && *p != ' ' && *p != '\\' && *p != '\n')
- p++;
- /* Is the token we found a target name? */
- is_target = (*(p-1) == ':');
- /* Don't write any target names into the dependency file */
- if (is_target) {
- /* The /next/ file is the first dependency */
- is_first_dep = 1;
- has_target = 1;
- } else if (has_target) {
- /* Save this token/filename */
- memcpy(s, m, p-m);
- s[p - m] = 0;
-
- /*
- * Do not list the source file as dependency,
- * so that kbuild is not confused if a .c file
- * is rewritten into .S or vice versa. Storing
- * it in source_* is needed for modpost to
- * compute srcversions.
- */
- if (is_first_dep) {
- /*
- * If processing the concatenation of
- * multiple dependency files, only
- * process the first target name, which
- * will be the original source name,
- * and ignore any other target names,
- * which will be intermediate temporary
- * files.
- */
- if (!saw_any_target) {
- saw_any_target = 1;
- printf("source_%s := %s\n\n",
- target, s);
- printf("deps_%s := \\\n",
- target);
- }
- is_first_dep = 0;
- } else
- printf(" %s \\\n", s);
- }
- /*
- * Start searching for next token immediately after the first
- * "whitespace" character that follows this token.
- */
- m = p + 1;
- }
-
- if (!saw_any_target) {
- fprintf(stderr, "fixdep: parse error; no targets found\n");
- exit(1);
- }
-
- printf("\n%s: $(deps_%s)\n\n", target, target);
- printf("$(deps_%s):\n", target);
-}
-
-static void print_deps(void)
-{
- struct stat st;
- int fd;
- void *map;
-
- fd = open(depfile, O_RDONLY);
- if (fd < 0) {
- fprintf(stderr, "fixdep: error opening depfile: ");
- perror(depfile);
- exit(2);
- }
- if (fstat(fd, &st) < 0) {
- fprintf(stderr, "fixdep: error fstat'ing depfile: ");
- perror(depfile);
- exit(2);
- }
- if (st.st_size == 0) {
- fprintf(stderr, "fixdep: %s is empty\n", depfile);
- close(fd);
- return;
- }
- map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
- if ((long) map == -1) {
- perror("fixdep: mmap");
- close(fd);
- return;
- }
-
- parse_dep_file(map, st.st_size);
-
- munmap(map, st.st_size);
-
- close(fd);
-}
-
-int main(int argc, char **argv)
-{
- if (argc != 4)
- usage();
-
- depfile = argv[1];
- target = argv[2];
- cmdline = argv[3];
-
- print_cmdline();
- print_deps();
-
- return 0;
-}
Index: v6.x/create-6.1.26-repka-pi3-patch/file.list
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/file.list (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/file.list (nonexistent)
@@ -1,3 +0,0 @@
-linux-6.1.26/arch/arm64/boot/dts/allwinner/Makefile
-linux-6.1.26/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
-linux-6.1.26/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
Index: v6.x/create-6.1.26-repka-pi3-patch/create.patch.sh
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/create.patch.sh (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/create.patch.sh (nonexistent)
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-VERSION=6.1.26
-
-tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
-mv linux-$VERSION linux-$VERSION-orig
-
-cp -rf ./linux-$VERSION-new ./linux-$VERSION
-
-diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-repka-pi3.patch
-
-mv linux-$VERSION-repka-pi3.patch ../patches
-
-rm -rf ./linux-$VERSION
-rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.1.26-repka-pi3-patch/create.patch.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi (nonexistent)
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
-
-/ {
- cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-288000000 {
- opp-hz = /bits/ 64 <288000000>;
- opp-microvolt = <1000000 1000000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-336000000 {
- opp-hz = /bits/ 64 <336000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000 1100000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000 1200000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1320000 1320000 1320000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1368000000 {
- opp-hz = /bits/ 64 <1368000000>;
- opp-microvolt = <1360000 1360000 1360000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
- };
-};
-
-&cpu0 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu1 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu2 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu3 {
- operating-points-v2 = <&cpu_opp_table>;
-};
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.2ghz.dtsi
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.2ghz.dtsi (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.2ghz.dtsi (nonexistent)
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
-
-/ {
- cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-288000000 {
- opp-hz = /bits/ 64 <288000000>;
- opp-microvolt = <1000000 1000000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-336000000 {
- opp-hz = /bits/ 64 <336000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000 1100000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1260000 1260000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-10560000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <1260000 1260000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1320000 1320000 1320000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
- };
-};
-
-&cpu0 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu1 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu2 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu3 {
- operating-points-v2 = <&cpu_opp_table>;
-};
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.4ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.4ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.4ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.4 GHz";
- repka-pinout = "3";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "okay";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.2ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.2ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.2ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.2 GHz";
- repka-pinout = "3";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "okay";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.0ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.0ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.0ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.0 GHz";
- repka-pinout = "3";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "okay";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.4ghz.dtsi
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.4ghz.dtsi (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.4ghz.dtsi (nonexistent)
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
-
-/ {
- cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-288000000 {
- opp-hz = /bits/ 64 <288000000>;
- opp-microvolt = <1000000 1000000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-336000000 {
- opp-hz = /bits/ 64 <336000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000 1100000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1260000 1260000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1320000 1320000 1320000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1368000000 {
- opp-hz = /bits/ 64 <1368000000>;
- opp-microvolt = <1360000 1360000 1360000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
- };
-};
-
-&cpu0 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu1 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu2 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu3 {
- operating-points-v2 = <&cpu_opp_table>;
-};
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt.dts (nonexistent)
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.0 GHz";
- repka-pinout = "4";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.2 GHz";
- repka-pinout = "4";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.4 GHz";
- repka-pinout = "4";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.0ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.0ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.0ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.0 GHz";
- repka-pinout = "2";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3.dts (nonexistent)
@@ -1,415 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "disabled"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-/*
- *
- *
- * ^__________^
-*
-*
-*/
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.2ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.2ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.2ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.2 GHz";
- repka-pinout = "2";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi (nonexistent)
@@ -1,339 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-#include <arm/sunxi-h3-h5.dtsi>
-
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <0>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <1>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <2>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <3>;
- enable-method = "psci";
- clocks = <&ccu CLK_CPUX>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- #cooling-cells = <2>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- arm,no-tick-in-suspend;
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc {
- syscon: system-control@1c00000 {
- compatible = "allwinner,sun50i-h5-system-control";
- reg = <0x01c00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram_c1: sram@18000 {
- compatible = "mmio-sram";
- reg = <0x00018000 0x1c000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00018000 0x1c000>;
-
- ve_sram: sram-section@0 {
- compatible = "allwinner,sun50i-h5-sram-c1",
- "allwinner,sun4i-a10-sram-c1";
- reg = <0x000000 0x1c000>;
- };
- };
- };
-
- video-codec@1c0e000 {
- compatible = "allwinner,sun50i-h5-video-engine";
- reg = <0x01c0e000 0x1000>;
- clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
- <&ccu CLK_DRAM_VE>;
- clock-names = "ahb", "mod", "ram";
- resets = <&ccu RST_BUS_VE>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- allwinner,sram = <&ve_sram 1>;
- };
-
- crypto: crypto@1c15000 {
- compatible = "allwinner,sun50i-h5-crypto";
- reg = <0x01c15000 0x1000>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
- clock-names = "bus", "mod";
- resets = <&ccu RST_BUS_CE>;
- };
-
- deinterlace: deinterlace@1e00000 {
- compatible = "allwinner,sun8i-h3-deinterlace";
- reg = <0x01e00000 0x20000>;
- clocks = <&ccu CLK_BUS_DEINTERLACE>,
- <&ccu CLK_DEINTERLACE>,
- <&ccu CLK_DRAM_DEINTERLACE>;
- clock-names = "bus", "mod", "ram";
- resets = <&ccu RST_BUS_DEINTERLACE>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- interconnects = <&mbus 9>;
- interconnect-names = "dma-mem";
- };
-
- mali: gpu@1e80000 {
- compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
- reg = <0x01e80000 0x30000>;
- /*
- * While the datasheet lists an interrupt for the
- * PMU, the actual silicon does not have the PMU
- * block. Reads all return zero, and writes are
- * ignored.
- */
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp",
- "gpmmu",
- "pp",
- "pp0",
- "ppmmu0",
- "pp1",
- "ppmmu1",
- "pp2",
- "ppmmu2",
- "pp3",
- "ppmmu3";
- clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
- clock-names = "bus", "core";
- resets = <&ccu RST_BUS_GPU>;
-
- assigned-clocks = <&ccu CLK_GPU>;
- assigned-clock-rates = <384000000>;
- };
-
- ths: thermal-sensor@1c25000 {
- compatible = "allwinner,sun50i-h5-ths";
- reg = <0x01c25000 0x400>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_BUS_THS>;
- clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
- clock-names = "bus", "mod";
- nvmem-cells = <&ths_calibration>;
- nvmem-cell-names = "calibration";
- #thermal-sensor-cells = <1>;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- /* milliseconds */
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&ths 0>;
-
- trips {
- cpu_warm: cpu_warm {
- temperature = <55000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_hot0: cpu_hot0 {
- temperature = <60000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_hot1: cpu_hot1 {
- temperature = <65000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_very_hot0: cpu_very_hot0 {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_very_hot1: cpu_very_hot1 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_very_hot2: cpu_very_hot2 {
- temperature = <80000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_very_hot3: cpu_very_hot3 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu_crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- cpu_warm_limit_cpu {
- trip = <&cpu_warm>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT 1>;
- };
-
- cpu_hot_limit_cpu0 {
- trip = <&cpu_hot0>;
- cooling-device = <&cpu0 1 2>;
- };
-
- cpu_hot_limit_cpu1 {
- trip = <&cpu_hot1>;
- cooling-device = <&cpu0 2 3>;
- };
-
- cpu_very_hot_limit_cpu0 {
- trip = <&cpu_very_hot0>;
- cooling-device = <&cpu0 3 4>;
- };
-
- cpu_very_hot_limit_cpu1 {
- trip = <&cpu_very_hot1>;
- cooling-device = <&cpu0 4 5>;
- };
-
- cpu_very_hot_limit_cpu2 {
- trip = <&cpu_very_hot2>;
- cooling-device = <&cpu0 5 6>;
- };
-
- cpu_very_hot_limit_cpu3 {
- trip = <&cpu_very_hot3>;
- cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
- };
-
- };
- };
-
- gpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&ths 1>;
- };
- };
-};
-
-&ccu {
- compatible = "allwinner,sun50i-h5-ccu";
-};
-
-&display_clocks {
- compatible = "allwinner,sun50i-h5-de2-clk";
-};
-
-&mbus {
- compatible = "allwinner,sun50i-h5-mbus";
-};
-
-&mmc0 {
- compatible = "allwinner,sun50i-h5-mmc",
- "allwinner,sun50i-a64-mmc";
- clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
- clock-names = "ahb", "mmc";
-};
-
-&mmc1 {
- compatible = "allwinner,sun50i-h5-mmc",
- "allwinner,sun50i-a64-mmc";
- clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
- clock-names = "ahb", "mmc";
-};
-
-&mmc2 {
- compatible = "allwinner,sun50i-h5-emmc",
- "allwinner,sun50i-a64-emmc";
- clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
- clock-names = "ahb", "mmc";
-};
-
-&pio {
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- compatible = "allwinner,sun50i-h5-pinctrl";
-};
-
-&rtc {
- compatible = "allwinner,sun50i-h5-rtc";
-};
-
-&sid {
- compatible = "allwinner,sun50i-h5-sid";
-};
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.4ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.4ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.4ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.4 GHz";
- repka-pinout = "2";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.0ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.0ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.0ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.0 GHz";
- repka-pinout = "1";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "disabled"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.0 GHz";
- repka-pinout = "5";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "okay";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.2ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.2ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.2ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.2 GHz";
- repka-pinout = "1";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "disabled"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.2 GHz";
- repka-pinout = "5";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "okay";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.4ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.4ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.4ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.4 GHz";
- repka-pinout = "1";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "disabled"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "disabled";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "disabled";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dts
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dts (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dts (nonexistent)
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2016 ARM Ltd.
-
-/dts-v1/;
-#include "sun50i-h5.dtsi"
-#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
- model = "Repka-Pi3-H5";
- repka-freq = "1.4 GHz";
- repka-pinout = "5";
- compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- aliases {
- mmc0 = &mmc0;
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ext_osc32k: ext_osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "ext_osc32k";
- };
-
- leds {
- compatible = "gpio-leds";
-
- status {
- label = "rbs:red:status";
- gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <200>;
- };
-
-};
-
-&codec {
- allwinner,audio-routing =
- "Line Out", "LINEOUT",
- "MIC1", "Mic",
- "Mic", "MBIAS";
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu1 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu2 {
- cpu-supply = <®_dcdc2>;
-};
-
-&cpu3 {
- cpu-supply = <®_dcdc2>;
-};
-
-&de {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&emac {
- phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
- allwinner,leds-active-low;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&ir {
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
-};
-
-&rtc {
- clocks = <&ext_osc32k>;
-};
-
-&mmc0 {
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
- status = "okay";
-};
-
-&mmc1 {
- vmmc-supply = <®_vcc3v3>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&r_pio>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
- interrupt-names = "host-wake";
- };
-
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_8bit_pins>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <8>;
- non-removable;
- cap-mmc-hw-reset;
- status = "disabled";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&i2c1 {
- status = "disabled"; /* PA19,PA18 */
-};
-
-&i2c0 {
- status = "okay"; /* PA11, PA12 */
-};
-
-&r_i2c {
- status = "okay";
-
- axp22x: pmic@34 {
- compatible = "x-powers,axp221";
- reg = <0x34>;
- interrupt-parent = <&r_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-#include "arm/axp22x.dtsi"
-
-&ac_power_supply {
- status = "okay";
-};
-
-®_aldo2 { /* VCC-PG 1.8 */
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-pg";
-};
-
-®_aldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-pll-avcc";
-};
-
-®_dc1sw {
- regulator-name = "vcc-phy";
-};
-
-®_dcdc1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-3v3";
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-a";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1360000>;
- regulator-name = "vdd-cpux-b";
-};
-
-/* DCDC3 is polyphased with DCDC2 */
-
-/*
- * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
- *
- */
-®_dcdc5 {
- regulator-always-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc-dram";
-};
-
-®_dldo1 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-1";
-};
-
-®_dldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-2";
-};
-
-®_dldo3 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-3";
-};
-
-®_dldo4 {
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi-4";
-};
- /* VCC-wifi-IO 1.8 */
-®_eldo1 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-1";
-};
-
-®_eldo2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-2";
-};
-
-®_eldo3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc-wifi-io-3";
-};
-
-
-
-®_rtc_ldo {
- regulator-name = "vcc-rtc";
-};
-
-&spi0 {
- pinctrl-names = "default", "default";
- pinctrl-1 = <&spi0_cs1>;
- cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
- spidev@1 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <1>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default", "default";
-
- status = "okay";
- spidev@0 {
- compatible = "rohm,dh2228fv";
- status = "okay";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
-
-&pio {
- spi0_cs1: spi0_cs1 {
- pins = "PA3";
- function = "gpio_out";
- output-high;
- };
-};
-
-
-&r_pwm {
- status = "okay";
-};
-
-/* to debag serial */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pa_pins>;
- status = "okay";
-};
-
-/* to bt-wifi module */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
- uart-has-rtscts;
- status = "okay";
-
-
-
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
- status = "disabled";
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins>;
- status = "disabled";
-};
-
-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/Makefile
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/Makefile (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/Makefile (nonexistent)
@@ -1,57 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-1.0ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-1.2ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-1.4ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-1.0ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-1.2ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-1.4ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-uart-1.0ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-uart-1.2ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-uart-1.4ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
Index: v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.0ghz.dtsi
===================================================================
--- v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.0ghz.dtsi (revision 150)
+++ v6.x/create-6.1.26-repka-pi3-patch/linux-6.1.26-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.0ghz.dtsi (nonexistent)
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
-
-/ {
- cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-288000000 {
- opp-hz = /bits/ 64 <288000000>;
- opp-microvolt = <1040000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-336000000 {
- opp-hz = /bits/ 64 <336000000>;
- opp-microvolt = <1040000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <1040000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-576000000 {
- opp-hz = /bits/ 64 <576000000>;
- opp-microvolt = <1040000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-912000000 {
- opp-hz = /bits/ 64 <912000000>;
- opp-microvolt = <1200000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1260000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- };
-};
-
-&cpu0 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu1 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu2 {
- operating-points-v2 = <&cpu_opp_table>;
-};
-
-&cpu3 {
- operating-points-v2 = <&cpu_opp_table>;
-};
Index: v6.x/Makefile
===================================================================
--- v6.x/Makefile (revision 150)
+++ v6.x/Makefile (revision 151)
@@ -7,16 +7,17 @@
url = $(DOWNLOAD_SERVER)/sources/Linux/v6.x
-versions = 6.1.26
+versions = 6.3.10
tarballs = $(addsuffix .tar.xz, $(addprefix linux-, $(versions)))
sha1s = $(addsuffix .sha1sum, $(tarballs))
-patches = $(CURDIR)/patches/linux-6.1.26-dwmac-rk.patch
-patches += $(CURDIR)/patches/linux-6.1.26-host-limits.patch
-patches += $(CURDIR)/patches/linux-6.1.26-sdhci-reset.patch
-patches += $(CURDIR)/patches/linux-6.1.26-leez-p710-spi.patch
-patches += $(CURDIR)/patches/linux-6.1.26-repka-pi3.patch
+patches = $(CURDIR)/patches/linux-6.3.10-dwmac-rk.patch
+patches += $(CURDIR)/patches/linux-6.3.10-host-limits.patch
+patches += $(CURDIR)/patches/linux-6.3.10-sdhci-reset.patch
+patches += $(CURDIR)/patches/linux-6.3.10-leez-p710-spi.patch
+patches += $(CURDIR)/patches/linux-6.3.10-orange-pi5.patch
+patches += $(CURDIR)/patches/linux-6.3.10-repka-pi3.patch
.NOTPARALLEL: $(patches)
@@ -51,11 +52,12 @@
$(patches): $(sha1s)
@echo -e "\n======= Create Patches =======\n" ; \
- ( cd create-6.1.26-dwmac-rk-patch ; ./create.patch.sh ) ; \
- ( cd create-6.1.26-host-limits-patch ; ./create.patch.sh ) ; \
- ( cd create-6.1.26-sdhci-reset-patch ; ./create.patch.sh ) ; \
- ( cd create-6.1.26-leez-p710-spi-patch ; ./create.patch.sh ) ; \
- ( cd create-6.1.26-repka-pi3-patch ; ./create.patch.sh ) ; \
+ ( cd create-6.3.10-dwmac-rk-patch ; ./create.patch.sh ) ; \
+ ( cd create-6.3.10-host-limits-patch ; ./create.patch.sh ) ; \
+ ( cd create-6.3.10-sdhci-reset-patch ; ./create.patch.sh ) ; \
+ ( cd create-6.3.10-leez-p710-spi-patch ; ./create.patch.sh ) ; \
+ ( cd create-6.3.10-orange-pi5-patch ; ./create.patch.sh ) ; \
+ ( cd create-6.3.10-repka-pi3-patch ; ./create.patch.sh ) ; \
echo -e "\n"
download_clean:
Index: v6.x/create-6.3.10-dwmac-rk-patch/create.patch.sh
===================================================================
--- v6.x/create-6.3.10-dwmac-rk-patch/create.patch.sh (nonexistent)
+++ v6.x/create-6.3.10-dwmac-rk-patch/create.patch.sh (revision 151)
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+VERSION=6.3.10
+
+tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
+mv linux-$VERSION linux-$VERSION-orig
+
+cp -rf ./linux-$VERSION-new ./linux-$VERSION
+
+diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-dwmac-rk.patch
+
+mv linux-$VERSION-dwmac-rk.patch ../patches
+
+rm -rf ./linux-$VERSION
+rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.3.10-dwmac-rk-patch/create.patch.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-dwmac-rk-patch/file.list
===================================================================
--- v6.x/create-6.3.10-dwmac-rk-patch/file.list (nonexistent)
+++ v6.x/create-6.3.10-dwmac-rk-patch/file.list (revision 151)
@@ -0,0 +1 @@
+linux-6.3.10/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
Index: v6.x/create-6.3.10-dwmac-rk-patch/linux-6.3.10-new/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
===================================================================
--- v6.x/create-6.3.10-dwmac-rk-patch/linux-6.3.10-new/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c (nonexistent)
+++ v6.x/create-6.3.10-dwmac-rk-patch/linux-6.3.10-new/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c (revision 151)
@@ -0,0 +1,1943 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/**
+ * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
+ *
+ * Copyright (C) 2014 Chen-Zhi (Roger Chen)
+ *
+ * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
+ */
+
+#include <linux/stmmac.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/phy.h>
+#include <linux/of_net.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/pm_runtime.h>
+
+#include "stmmac_platform.h"
+
+struct rk_priv_data;
+struct rk_gmac_ops {
+ void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay);
+ void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
+ void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
+ void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
+ void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
+ bool enable);
+ void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
+ bool regs_valid;
+ u32 regs[];
+};
+
+static const char * const rk_clocks[] = {
+ "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
+};
+
+static const char * const rk_rmii_clocks[] = {
+ "mac_clk_rx", "clk_mac_ref", "clk_mac_refout",
+};
+
+enum rk_clocks_index {
+ RK_ACLK_MAC = 0,
+ RK_PCLK_MAC,
+ RK_MAC_CLK_TX,
+ RK_CLK_MAC_SPEED,
+ RK_MAC_CLK_RX,
+ RK_CLK_MAC_REF,
+ RK_CLK_MAC_REFOUT,
+};
+
+struct rk_priv_data {
+ struct platform_device *pdev;
+ phy_interface_t phy_iface;
+ int id;
+ struct regulator *regulator;
+ bool suspended;
+ const struct rk_gmac_ops *ops;
+
+ bool clk_enabled;
+ bool clock_input;
+ bool integrated_phy;
+
+ struct clk_bulk_data *clks;
+ int num_clks;
+ struct clk *clk_mac;
+ struct clk *clk_phy;
+
+ struct reset_control *phy_reset;
+
+ int tx_delay;
+ int rx_delay;
+
+ struct regmap *grf;
+ struct regmap *php_grf;
+};
+
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
+#define GRF_CLR_BIT(nr) (BIT(nr+16))
+
+#define DELAY_ENABLE(soc, tx, rx) \
+ (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
+ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+
+#define PX30_GRF_GMAC_CON1 0x0904
+
+/* PX30_GRF_GMAC_CON1 */
+#define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
+ GRF_BIT(6))
+#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
+#define PX30_GMAC_SPEED_100M GRF_BIT(2)
+
+static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
+ PX30_GMAC_PHY_INTF_SEL_RMII);
+}
+
+static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
+ struct device *dev = &bsp_priv->pdev->dev;
+ int ret;
+
+ if (!clk_mac_speed) {
+ dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
+ PX30_GMAC_SPEED_10M);
+
+ ret = clk_set_rate(clk_mac_speed, 2500000);
+ if (ret)
+ dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
+ __func__, ret);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
+ PX30_GMAC_SPEED_100M);
+
+ ret = clk_set_rate(clk_mac_speed, 25000000);
+ if (ret)
+ dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
+ __func__, ret);
+
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops px30_ops = {
+ .set_to_rmii = px30_set_to_rmii,
+ .set_rmii_speed = px30_set_rmii_speed,
+};
+
+#define RK3128_GRF_MAC_CON0 0x0168
+#define RK3128_GRF_MAC_CON1 0x016c
+
+/* RK3128_GRF_MAC_CON0 */
+#define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
+#define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
+#define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/* RK3128_GRF_MAC_CON1 */
+#define RK3128_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
+#define RK3128_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
+#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
+#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
+#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
+#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
+#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
+#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
+#define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
+#define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
+#define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
+#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
+#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
+
+static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_PHY_INTF_SEL_RGMII |
+ RK3128_GMAC_RMII_MODE_CLR);
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
+ DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
+ RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
+}
+
+static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_RMII_CLK_2_5M |
+ RK3128_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_RMII_CLK_25M |
+ RK3128_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rk3128_ops = {
+ .set_to_rgmii = rk3128_set_to_rgmii,
+ .set_to_rmii = rk3128_set_to_rmii,
+ .set_rgmii_speed = rk3128_set_rgmii_speed,
+ .set_rmii_speed = rk3128_set_rmii_speed,
+};
+
+#define RK3228_GRF_MAC_CON0 0x0900
+#define RK3228_GRF_MAC_CON1 0x0904
+
+#define RK3228_GRF_CON_MUX 0x50
+
+/* RK3228_GRF_MAC_CON0 */
+#define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/* RK3228_GRF_MAC_CON1 */
+#define RK3228_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3228_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
+#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
+#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
+#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
+#define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
+#define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
+#define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
+#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
+#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
+#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+
+/* RK3228_GRF_COM_MUX */
+#define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
+
+static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_PHY_INTF_SEL_RGMII |
+ RK3228_GMAC_RMII_MODE_CLR |
+ DELAY_ENABLE(RK3228, tx_delay, rx_delay));
+
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
+ RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_PHY_INTF_SEL_RMII |
+ RK3228_GMAC_RMII_MODE);
+
+ /* set MAC to RMII mode */
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
+}
+
+static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_RMII_CLK_2_5M |
+ RK3228_GMAC_SPEED_10M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_RMII_CLK_25M |
+ RK3228_GMAC_SPEED_100M);
+ else
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+}
+
+static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK3228_GRF_CON_MUX,
+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
+}
+
+static const struct rk_gmac_ops rk3228_ops = {
+ .set_to_rgmii = rk3228_set_to_rgmii,
+ .set_to_rmii = rk3228_set_to_rmii,
+ .set_rgmii_speed = rk3228_set_rgmii_speed,
+ .set_rmii_speed = rk3228_set_rmii_speed,
+ .integrated_phy_powerup = rk3228_integrated_phy_powerup,
+};
+
+#define RK3288_GRF_SOC_CON1 0x0248
+#define RK3288_GRF_SOC_CON3 0x0250
+
+/*RK3288_GRF_SOC_CON1*/
+#define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
+ GRF_CLR_BIT(8))
+#define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
+ GRF_BIT(8))
+#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
+#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
+#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
+#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
+#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
+#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
+#define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
+#define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
+#define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
+#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
+#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
+
+/*RK3288_GRF_SOC_CON3*/
+#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
+#define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
+#define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_PHY_INTF_SEL_RGMII |
+ RK3288_GMAC_RMII_MODE_CLR);
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
+ DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
+ RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
+}
+
+static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_RMII_CLK_2_5M |
+ RK3288_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_RMII_CLK_25M |
+ RK3288_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rk3288_ops = {
+ .set_to_rgmii = rk3288_set_to_rgmii,
+ .set_to_rmii = rk3288_set_to_rmii,
+ .set_rgmii_speed = rk3288_set_rgmii_speed,
+ .set_rmii_speed = rk3288_set_rmii_speed,
+};
+
+#define RK3308_GRF_MAC_CON0 0x04a0
+
+/* RK3308_GRF_MAC_CON0 */
+#define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
+ GRF_BIT(4))
+#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
+#define RK3308_GMAC_SPEED_100M GRF_BIT(0)
+
+static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
+ RK3308_GMAC_PHY_INTF_SEL_RMII);
+}
+
+static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
+ RK3308_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
+ RK3308_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rk3308_ops = {
+ .set_to_rmii = rk3308_set_to_rmii,
+ .set_rmii_speed = rk3308_set_rmii_speed,
+};
+
+#define RK3328_GRF_MAC_CON0 0x0900
+#define RK3328_GRF_MAC_CON1 0x0904
+#define RK3328_GRF_MAC_CON2 0x0908
+#define RK3328_GRF_MACPHY_CON1 0xb04
+
+/* RK3328_GRF_MAC_CON0 */
+#define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/* RK3328_GRF_MAC_CON1 */
+#define RK3328_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3328_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
+#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
+#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
+#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
+#define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
+#define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
+#define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
+#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
+#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
+#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+
+/* RK3328_GRF_MACPHY_CON1 */
+#define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
+
+static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ RK3328_GMAC_PHY_INTF_SEL_RGMII |
+ RK3328_GMAC_RMII_MODE_CLR |
+ RK3328_GMAC_RXCLK_DLY_ENABLE |
+ RK3328_GMAC_TXCLK_DLY_ENABLE);
+
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
+ RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int reg;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
+ RK3328_GRF_MAC_CON1;
+
+ regmap_write(bsp_priv->grf, reg,
+ RK3328_GMAC_PHY_INTF_SEL_RMII |
+ RK3328_GMAC_RMII_MODE);
+}
+
+static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ RK3328_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ RK3328_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ RK3328_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int reg;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
+ RK3328_GRF_MAC_CON1;
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, reg,
+ RK3328_GMAC_RMII_CLK_2_5M |
+ RK3328_GMAC_SPEED_10M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, reg,
+ RK3328_GMAC_RMII_CLK_25M |
+ RK3328_GMAC_SPEED_100M);
+ else
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+}
+
+static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
+ RK3328_MACPHY_RMII_MODE);
+}
+
+static const struct rk_gmac_ops rk3328_ops = {
+ .set_to_rgmii = rk3328_set_to_rgmii,
+ .set_to_rmii = rk3328_set_to_rmii,
+ .set_rgmii_speed = rk3328_set_rgmii_speed,
+ .set_rmii_speed = rk3328_set_rmii_speed,
+ .integrated_phy_powerup = rk3328_integrated_phy_powerup,
+};
+
+#define RK3366_GRF_SOC_CON6 0x0418
+#define RK3366_GRF_SOC_CON7 0x041c
+
+/* RK3366_GRF_SOC_CON6 */
+#define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
+ GRF_CLR_BIT(11))
+#define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
+ GRF_BIT(11))
+#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
+#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
+#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
+#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
+#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
+#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
+#define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
+#define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
+#define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
+#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
+
+/* RK3366_GRF_SOC_CON7 */
+#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
+#define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
+#define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_PHY_INTF_SEL_RGMII |
+ RK3366_GMAC_RMII_MODE_CLR);
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
+ DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
+ RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
+}
+
+static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_RMII_CLK_2_5M |
+ RK3366_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_RMII_CLK_25M |
+ RK3366_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rk3366_ops = {
+ .set_to_rgmii = rk3366_set_to_rgmii,
+ .set_to_rmii = rk3366_set_to_rmii,
+ .set_rgmii_speed = rk3366_set_rgmii_speed,
+ .set_rmii_speed = rk3366_set_rmii_speed,
+};
+
+#define RK3368_GRF_SOC_CON15 0x043c
+#define RK3368_GRF_SOC_CON16 0x0440
+
+/* RK3368_GRF_SOC_CON15 */
+#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
+ GRF_CLR_BIT(11))
+#define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
+ GRF_BIT(11))
+#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
+#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
+#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
+#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
+#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
+#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
+#define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
+#define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
+#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
+
+/* RK3368_GRF_SOC_CON16 */
+#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
+#define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
+#define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_PHY_INTF_SEL_RGMII |
+ RK3368_GMAC_RMII_MODE_CLR);
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
+ DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
+ RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
+}
+
+static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_RMII_CLK_2_5M |
+ RK3368_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_RMII_CLK_25M |
+ RK3368_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rk3368_ops = {
+ .set_to_rgmii = rk3368_set_to_rgmii,
+ .set_to_rmii = rk3368_set_to_rmii,
+ .set_rgmii_speed = rk3368_set_rgmii_speed,
+ .set_rmii_speed = rk3368_set_rmii_speed,
+};
+
+#define RK3399_GRF_SOC_CON5 0xc214
+#define RK3399_GRF_SOC_CON6 0xc218
+
+/* RK3399_GRF_SOC_CON5 */
+#define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
+ GRF_CLR_BIT(11))
+#define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
+ GRF_BIT(11))
+#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
+#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
+#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
+#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
+#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
+#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
+#define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
+#define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
+#define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
+#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
+
+/* RK3399_GRF_SOC_CON6 */
+#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
+#define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
+#define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_PHY_INTF_SEL_RGMII |
+ RK3399_GMAC_RMII_MODE_CLR);
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
+ DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
+ RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
+}
+
+static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_CLK_125M);
+ else
+ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
+}
+
+static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_RMII_CLK_2_5M |
+ RK3399_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_RMII_CLK_25M |
+ RK3399_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rk3399_ops = {
+ .set_to_rgmii = rk3399_set_to_rgmii,
+ .set_to_rmii = rk3399_set_to_rmii,
+ .set_rgmii_speed = rk3399_set_rgmii_speed,
+ .set_rmii_speed = rk3399_set_rmii_speed,
+};
+
+#define RK3568_GRF_GMAC0_CON0 0x0380
+#define RK3568_GRF_GMAC0_CON1 0x0384
+#define RK3568_GRF_GMAC1_CON0 0x0388
+#define RK3568_GRF_GMAC1_CON1 0x038c
+
+/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3568_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+
+/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
+#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ u32 con0, con1;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
+ RK3568_GRF_GMAC0_CON0;
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
+ RK3568_GRF_GMAC0_CON1;
+
+ regmap_write(bsp_priv->grf, con0,
+ RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ regmap_write(bsp_priv->grf, con1,
+ RK3568_GMAC_PHY_INTF_SEL_RGMII |
+ RK3568_GMAC_RXCLK_DLY_ENABLE |
+ RK3568_GMAC_TXCLK_DLY_ENABLE);
+}
+
+static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ u32 con1;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
+ RK3568_GRF_GMAC0_CON1;
+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
+}
+
+static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned long rate;
+ int ret;
+
+ switch (speed) {
+ case 10:
+ rate = 2500000;
+ break;
+ case 100:
+ rate = 25000000;
+ break;
+ case 1000:
+ rate = 125000000;
+ break;
+ default:
+ dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
+ return;
+ }
+
+ ret = clk_set_rate(clk_mac_speed, rate);
+ if (ret)
+ dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
+ __func__, rate, ret);
+}
+
+static const struct rk_gmac_ops rk3568_ops = {
+ .set_to_rgmii = rk3568_set_to_rgmii,
+ .set_to_rmii = rk3568_set_to_rmii,
+ .set_rgmii_speed = rk3568_set_gmac_speed,
+ .set_rmii_speed = rk3568_set_gmac_speed,
+ .regs_valid = true,
+ .regs = {
+ 0xfe2a0000, /* gmac0 */
+ 0xfe010000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+};
+
+/* sys_grf */
+#define RK3588_GRF_GMAC_CON7 0X031c
+#define RK3588_GRF_GMAC_CON8 0X0320
+#define RK3588_GRF_GMAC_CON9 0X0324
+
+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
+#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
+#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
+#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
+
+#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+
+/* php_grf */
+#define RK3588_GRF_GMAC_CON0 0X0008
+#define RK3588_GRF_CLK_CON1 0X0070
+
+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
+ (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
+#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
+ (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
+
+#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
+#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
+
+#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
+#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
+
+#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
+#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
+
+#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
+ (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
+#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
+ (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
+#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
+ (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
+
+#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
+#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
+
+static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ u32 offset_con, id = bsp_priv->id;
+
+ if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
+ dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
+ return;
+ }
+
+ offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
+ RK3588_GRF_GMAC_CON8;
+
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
+ RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
+
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
+ RK3588_GMAC_CLK_RGMII_MODE(id));
+
+ regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
+ RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
+ RK3588_GMAC_TXCLK_DLY_ENABLE(id));
+
+ regmap_write(bsp_priv->grf, offset_con,
+ RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->php_grf)) {
+ dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
+ RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
+
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
+ RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
+}
+
+static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int val = 0, id = bsp_priv->id;
+
+ switch (speed) {
+ case 10:
+ if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
+ val = RK3588_GMA_CLK_RMII_DIV20(id);
+ else
+ val = RK3588_GMAC_CLK_RGMII_DIV50(id);
+ break;
+ case 100:
+ if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
+ val = RK3588_GMA_CLK_RMII_DIV2(id);
+ else
+ val = RK3588_GMAC_CLK_RGMII_DIV5(id);
+ break;
+ case 1000:
+ if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
+ val = RK3588_GMAC_CLK_RGMII_DIV1(id);
+ else
+ goto err;
+ break;
+ default:
+ goto err;
+ }
+
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
+
+ return;
+err:
+ dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
+}
+
+static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
+ bool enable)
+{
+ unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) :
+ RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id);
+
+ val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
+ RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
+
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
+}
+
+static const struct rk_gmac_ops rk3588_ops = {
+ .set_to_rgmii = rk3588_set_to_rgmii,
+ .set_to_rmii = rk3588_set_to_rmii,
+ .set_rgmii_speed = rk3588_set_gmac_speed,
+ .set_rmii_speed = rk3588_set_gmac_speed,
+ .set_clock_selection = rk3588_set_clock_selection,
+ .regs_valid = true,
+ .regs = {
+ 0xfe1b0000, /* gmac0 */
+ 0xfe1c0000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+};
+
+#define RV1108_GRF_GMAC_CON0 0X0900
+
+/* RV1108_GRF_GMAC_CON0 */
+#define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
+ GRF_BIT(6))
+#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
+#define RV1108_GMAC_SPEED_100M GRF_BIT(2)
+#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
+#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
+
+static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
+ RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
+static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
+ RV1108_GMAC_RMII_CLK_2_5M |
+ RV1108_GMAC_SPEED_10M);
+ } else if (speed == 100) {
+ regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
+ RV1108_GMAC_RMII_CLK_25M |
+ RV1108_GMAC_SPEED_100M);
+ } else {
+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
+ }
+}
+
+static const struct rk_gmac_ops rv1108_ops = {
+ .set_to_rmii = rv1108_set_to_rmii,
+ .set_rmii_speed = rv1108_set_rmii_speed,
+};
+
+#define RV1126_GRF_GMAC_CON0 0X0070
+#define RV1126_GRF_GMAC_CON1 0X0074
+#define RV1126_GRF_GMAC_CON2 0X0078
+
+/* RV1126_GRF_GMAC_CON0 */
+#define RV1126_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RV1126_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
+#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
+#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
+#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
+#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
+#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
+
+/* RV1126_GRF_GMAC_CON1 */
+#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+/* RV1126_GRF_GMAC_CON2 */
+#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
+ RV1126_GMAC_PHY_INTF_SEL_RGMII |
+ RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
+ RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
+ RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
+ RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
+
+ regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
+ RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
+ RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
+
+ regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
+ RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
+ RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
+ RV1126_GMAC_PHY_INTF_SEL_RMII);
+}
+
+static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned long rate;
+ int ret;
+
+ switch (speed) {
+ case 10:
+ rate = 2500000;
+ break;
+ case 100:
+ rate = 25000000;
+ break;
+ case 1000:
+ rate = 125000000;
+ break;
+ default:
+ dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
+ return;
+ }
+
+ ret = clk_set_rate(clk_mac_speed, rate);
+ if (ret)
+ dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
+ __func__, rate, ret);
+}
+
+static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned long rate;
+ int ret;
+
+ switch (speed) {
+ case 10:
+ rate = 2500000;
+ break;
+ case 100:
+ rate = 25000000;
+ break;
+ default:
+ dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
+ return;
+ }
+
+ ret = clk_set_rate(clk_mac_speed, rate);
+ if (ret)
+ dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
+ __func__, rate, ret);
+}
+
+static const struct rk_gmac_ops rv1126_ops = {
+ .set_to_rgmii = rv1126_set_to_rgmii,
+ .set_to_rmii = rv1126_set_to_rmii,
+ .set_rgmii_speed = rv1126_set_rgmii_speed,
+ .set_rmii_speed = rv1126_set_rmii_speed,
+};
+
+#define RK_GRF_MACPHY_CON0 0xb00
+#define RK_GRF_MACPHY_CON1 0xb04
+#define RK_GRF_MACPHY_CON2 0xb08
+#define RK_GRF_MACPHY_CON3 0xb0c
+
+#define RK_MACPHY_ENABLE GRF_BIT(0)
+#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
+#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
+#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
+#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
+#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
+
+static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
+{
+ if (priv->ops->integrated_phy_powerup)
+ priv->ops->integrated_phy_powerup(priv);
+
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
+
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
+
+ if (priv->phy_reset) {
+ /* PHY needs to be disabled before trying to reset it */
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->phy_reset)
+ reset_control_assert(priv->phy_reset);
+ usleep_range(10, 20);
+ if (priv->phy_reset)
+ reset_control_deassert(priv->phy_reset);
+ usleep_range(10, 20);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
+ msleep(30);
+ }
+}
+
+static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->phy_reset)
+ reset_control_assert(priv->phy_reset);
+}
+
+static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
+{
+ struct rk_priv_data *bsp_priv = plat->bsp_priv;
+ struct device *dev = &bsp_priv->pdev->dev;
+ int phy_iface = bsp_priv->phy_iface;
+ int i, j, ret;
+
+ bsp_priv->clk_enabled = false;
+
+ bsp_priv->num_clks = ARRAY_SIZE(rk_clocks);
+ if (phy_iface == PHY_INTERFACE_MODE_RMII)
+ bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks);
+
+ bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks,
+ sizeof(*bsp_priv->clks), GFP_KERNEL);
+ if (!bsp_priv->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(rk_clocks); i++)
+ bsp_priv->clks[i].id = rk_clocks[i];
+
+ if (phy_iface == PHY_INTERFACE_MODE_RMII) {
+ for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++)
+ bsp_priv->clks[i++].id = rk_rmii_clocks[j];
+ }
+
+ ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
+ bsp_priv->clks);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get clocks\n");
+
+ /* "stmmaceth" will be enabled by the core */
+ bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
+ ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac);
+ if (ret)
+ return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n");
+
+ if (bsp_priv->clock_input) {
+ dev_info(dev, "clock input from PHY\n");
+ } else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
+ clk_set_rate(bsp_priv->clk_mac, 50000000);
+ }
+
+ if (plat->phy_node && bsp_priv->integrated_phy) {
+ bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
+ ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
+ if (ret)
+ return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
+ clk_set_rate(bsp_priv->clk_phy, 50000000);
+ }
+
+ return 0;
+}
+
+static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
+{
+ int ret;
+
+ if (enable) {
+ if (!bsp_priv->clk_enabled) {
+ ret = clk_bulk_prepare_enable(bsp_priv->num_clks,
+ bsp_priv->clks);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(bsp_priv->clk_phy);
+ if (ret)
+ return ret;
+
+ if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
+ bsp_priv->ops->set_clock_selection(bsp_priv,
+ bsp_priv->clock_input, true);
+
+ mdelay(5);
+ bsp_priv->clk_enabled = true;
+ }
+ } else {
+ if (bsp_priv->clk_enabled) {
+ clk_bulk_disable_unprepare(bsp_priv->num_clks,
+ bsp_priv->clks);
+ clk_disable_unprepare(bsp_priv->clk_phy);
+
+ if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
+ bsp_priv->ops->set_clock_selection(bsp_priv,
+ bsp_priv->clock_input, false);
+
+ bsp_priv->clk_enabled = false;
+ }
+ }
+
+ return 0;
+}
+
+static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
+{
+ struct regulator *ldo = bsp_priv->regulator;
+ int ret;
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (enable) {
+ ret = regulator_enable(ldo);
+ if (ret)
+ dev_err(dev, "fail to enable phy-supply\n");
+ } else {
+ ret = regulator_disable(ldo);
+ if (ret)
+ dev_err(dev, "fail to disable phy-supply\n");
+ }
+
+ return 0;
+}
+
+static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
+ struct plat_stmmacenet_data *plat,
+ const struct rk_gmac_ops *ops)
+{
+ struct rk_priv_data *bsp_priv;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int ret;
+ const char *strings = NULL;
+ int value;
+
+ bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
+ if (!bsp_priv)
+ return ERR_PTR(-ENOMEM);
+
+ of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
+ bsp_priv->ops = ops;
+
+ /* Some SoCs have multiple MAC controllers, which need
+ * to be distinguished.
+ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res && ops->regs_valid) {
+ int i = 0;
+
+ while (ops->regs[i]) {
+ if (ops->regs[i] == res->start) {
+ bsp_priv->id = i;
+ break;
+ }
+ i++;
+ }
+ }
+
+ bsp_priv->regulator = devm_regulator_get(dev, "phy");
+ if (IS_ERR(bsp_priv->regulator)) {
+ ret = PTR_ERR(bsp_priv->regulator);
+ dev_err_probe(dev, ret, "failed to get phy regulator\n");
+ return ERR_PTR(ret);
+ }
+
+ ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
+ if (ret) {
+ dev_err(dev, "Can not read property: clock_in_out.\n");
+ bsp_priv->clock_input = true;
+ } else {
+ dev_info(dev, "clock input or output? (%s).\n",
+ strings);
+ if (!strcmp(strings, "input"))
+ bsp_priv->clock_input = true;
+ else
+ bsp_priv->clock_input = false;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
+ if (ret) {
+ bsp_priv->tx_delay = 0x30;
+ dev_err(dev, "Can not read property: tx_delay.");
+ dev_err(dev, "set tx_delay to 0x%x\n",
+ bsp_priv->tx_delay);
+ } else {
+ dev_info(dev, "TX delay(0x%x).\n", value);
+ bsp_priv->tx_delay = value;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
+ if (ret) {
+ bsp_priv->rx_delay = 0x10;
+ dev_err(dev, "Can not read property: rx_delay.");
+ dev_err(dev, "set rx_delay to 0x%x\n",
+ bsp_priv->rx_delay);
+ } else {
+ dev_info(dev, "RX delay(0x%x).\n", value);
+ bsp_priv->rx_delay = value;
+ }
+
+ bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "rockchip,grf");
+ bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "rockchip,php-grf");
+
+ if (plat->phy_node) {
+ bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
+ "phy-is-integrated");
+ if (bsp_priv->integrated_phy) {
+ bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
+ if (IS_ERR(bsp_priv->phy_reset)) {
+ dev_err(&pdev->dev, "No PHY reset control found.\n");
+ bsp_priv->phy_reset = NULL;
+ }
+ }
+ }
+ dev_info(dev, "integrated PHY? (%s).\n",
+ bsp_priv->integrated_phy ? "yes" : "no");
+
+ bsp_priv->pdev = pdev;
+
+ return bsp_priv;
+}
+
+static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->phy_iface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ if (!bsp_priv->ops->set_to_rgmii)
+ return -EINVAL;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (!bsp_priv->ops->set_to_rmii)
+ return -EINVAL;
+ break;
+ default:
+ dev_err(&bsp_priv->pdev->dev,
+ "unsupported interface %d", bsp_priv->phy_iface);
+ }
+ return 0;
+}
+
+static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
+{
+ int ret;
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ ret = rk_gmac_check_ops(bsp_priv);
+ if (ret)
+ return ret;
+
+ ret = gmac_clk_enable(bsp_priv, true);
+ if (ret)
+ return ret;
+
+ /*rmii or rgmii*/
+ switch (bsp_priv->phy_iface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ dev_info(dev, "init for RGMII\n");
+ bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
+ bsp_priv->rx_delay);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ dev_info(dev, "init for RGMII_ID\n");
+ bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ dev_info(dev, "init for RGMII_RXID\n");
+ bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ dev_info(dev, "init for RGMII_TXID\n");
+ bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ dev_info(dev, "init for RMII\n");
+ bsp_priv->ops->set_to_rmii(bsp_priv);
+ break;
+ default:
+ dev_err(dev, "NO interface defined!\n");
+ }
+
+ ret = phy_power_on(bsp_priv, true);
+ if (ret) {
+ gmac_clk_enable(bsp_priv, false);
+ return ret;
+ }
+
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
+ if (bsp_priv->integrated_phy)
+ rk_gmac_integrated_phy_powerup(bsp_priv);
+
+ return 0;
+}
+
+static void rk_gmac_powerdown(struct rk_priv_data *gmac)
+{
+ struct device *dev = &gmac->pdev->dev;
+
+ if (gmac->integrated_phy)
+ rk_gmac_integrated_phy_powerdown(gmac);
+
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
+ phy_power_on(gmac, false);
+ gmac_clk_enable(gmac, false);
+}
+
+static void rk_fix_speed(void *priv, unsigned int speed)
+{
+ struct rk_priv_data *bsp_priv = priv;
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ switch (bsp_priv->phy_iface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ if (bsp_priv->ops->set_rgmii_speed)
+ bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (bsp_priv->ops->set_rmii_speed)
+ bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
+ break;
+ default:
+ dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
+ }
+}
+
+static int rk_gmac_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ const struct rk_gmac_ops *data;
+ int ret;
+
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data) {
+ dev_err(&pdev->dev, "no of match data provided\n");
+ return -EINVAL;
+ }
+
+ ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (ret)
+ return ret;
+
+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return PTR_ERR(plat_dat);
+
+ /* If the stmmac is not already selected as gmac4,
+ * then make sure we fallback to gmac.
+ */
+ if (!plat_dat->has_gmac4)
+ plat_dat->has_gmac = true;
+ plat_dat->fix_mac_speed = rk_fix_speed;
+
+ plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
+ if (IS_ERR(plat_dat->bsp_priv)) {
+ ret = PTR_ERR(plat_dat->bsp_priv);
+ goto err_remove_config_dt;
+ }
+
+ ret = rk_gmac_clk_init(plat_dat);
+ if (ret)
+ goto err_remove_config_dt;
+
+ ret = rk_gmac_powerup(plat_dat->bsp_priv);
+ if (ret)
+ goto err_remove_config_dt;
+
+ ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+ if (ret)
+ goto err_gmac_powerdown;
+
+ return 0;
+
+err_gmac_powerdown:
+ rk_gmac_powerdown(plat_dat->bsp_priv);
+err_remove_config_dt:
+ stmmac_remove_config_dt(pdev, plat_dat);
+
+ return ret;
+}
+
+static int rk_gmac_remove(struct platform_device *pdev)
+{
+ struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
+
+ stmmac_dvr_remove(&pdev->dev);
+
+ rk_gmac_powerdown(bsp_priv);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rk_gmac_suspend(struct device *dev)
+{
+ struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
+ int ret = stmmac_suspend(dev);
+
+ /* Keep the PHY up if we use Wake-on-Lan. */
+ if (!device_may_wakeup(dev)) {
+ rk_gmac_powerdown(bsp_priv);
+ bsp_priv->suspended = true;
+ }
+
+ return ret;
+}
+
+static int rk_gmac_resume(struct device *dev)
+{
+ struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
+
+ /* The PHY was up for Wake-on-Lan. */
+ if (bsp_priv->suspended) {
+ rk_gmac_powerup(bsp_priv);
+ bsp_priv->suspended = false;
+ }
+
+ return stmmac_resume(dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
+
+static const struct of_device_id rk_gmac_dwmac_match[] = {
+ { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
+ { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
+ { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
+ { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
+ { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
+ { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
+ { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
+ { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
+ { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
+ { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
+ { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
+ { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
+ { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
+ { }
+};
+MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
+
+static struct platform_driver rk_gmac_dwmac_driver = {
+ .probe = rk_gmac_probe,
+ .remove = rk_gmac_remove,
+ .driver = {
+ .name = "rk_gmac-dwmac",
+ .pm = &rk_gmac_pm_ops,
+ .of_match_table = rk_gmac_dwmac_match,
+ },
+};
+module_platform_driver(rk_gmac_dwmac_driver);
+
+MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
+MODULE_LICENSE("GPL");
Index: v6.x/create-6.3.10-host-limits-patch/create.patch.sh
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/create.patch.sh (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/create.patch.sh (revision 151)
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+VERSION=6.3.10
+
+tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
+mv linux-$VERSION linux-$VERSION-orig
+
+cp -rf ./linux-$VERSION-new ./linux-$VERSION
+
+diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-host-limits.patch
+
+mv linux-$VERSION-host-limits.patch ../patches
+
+rm -rf ./linux-$VERSION
+rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.3.10-host-limits-patch/create.patch.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-host-limits-patch/file.list
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/file.list (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/file.list (revision 151)
@@ -0,0 +1,7 @@
+linux-6.3.10/scripts/kconfig/conf.c
+linux-6.3.10/scripts/kconfig/confdata.c
+linux-6.3.10/scripts/kconfig/lexer.l
+linux-6.3.10/scripts/mod/modpost.c
+linux-6.3.10/scripts/mod/sumversion.c
+linux-6.3.10/tools/build/fixdep.c
+linux-6.3.10/usr/gen_init_cpio.c
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/conf.c
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/conf.c (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/conf.c (revision 151)
@@ -0,0 +1,921 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
+ */
+
+#include <ctype.h>
+#include <linux/limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+#include <getopt.h>
+#include <sys/time.h>
+#include <errno.h>
+
+#include "lkc.h"
+
+static void conf(struct menu *menu);
+static void check_conf(struct menu *menu);
+
+enum input_mode {
+ oldaskconfig,
+ syncconfig,
+ oldconfig,
+ allnoconfig,
+ allyesconfig,
+ allmodconfig,
+ alldefconfig,
+ randconfig,
+ defconfig,
+ savedefconfig,
+ listnewconfig,
+ helpnewconfig,
+ olddefconfig,
+ yes2modconfig,
+ mod2yesconfig,
+ mod2noconfig,
+};
+static enum input_mode input_mode = oldaskconfig;
+static int input_mode_opt;
+static int indent = 1;
+static int tty_stdio;
+static int sync_kconfig;
+static int conf_cnt;
+static char line[PATH_MAX];
+static struct menu *rootEntry;
+
+static void print_help(struct menu *menu)
+{
+ struct gstr help = str_new();
+
+ menu_get_ext_help(menu, &help);
+
+ printf("\n%s\n", str_get(&help));
+ str_free(&help);
+}
+
+static void strip(char *str)
+{
+ char *p = str;
+ int l;
+
+ while ((isspace(*p)))
+ p++;
+ l = strlen(p);
+ if (p != str)
+ memmove(str, p, l + 1);
+ if (!l)
+ return;
+ p = str + l - 1;
+ while ((isspace(*p)))
+ *p-- = 0;
+}
+
+/* Helper function to facilitate fgets() by Jean Sacren. */
+static void xfgets(char *str, int size, FILE *in)
+{
+ if (!fgets(str, size, in))
+ fprintf(stderr, "\nError in reading or end of file.\n");
+
+ if (!tty_stdio)
+ printf("%s", str);
+}
+
+static void set_randconfig_seed(void)
+{
+ unsigned int seed;
+ char *env;
+ bool seed_set = false;
+
+ env = getenv("KCONFIG_SEED");
+ if (env && *env) {
+ char *endp;
+
+ seed = strtol(env, &endp, 0);
+ if (*endp == '\0')
+ seed_set = true;
+ }
+
+ if (!seed_set) {
+ struct timeval now;
+
+ /*
+ * Use microseconds derived seed, compensate for systems where it may
+ * be zero.
+ */
+ gettimeofday(&now, NULL);
+ seed = (now.tv_sec + 1) * (now.tv_usec + 1);
+ }
+
+ printf("KCONFIG_SEED=0x%X\n", seed);
+ srand(seed);
+}
+
+static bool randomize_choice_values(struct symbol *csym)
+{
+ struct property *prop;
+ struct symbol *sym;
+ struct expr *e;
+ int cnt, def;
+
+ /*
+ * If choice is mod then we may have more items selected
+ * and if no then no-one.
+ * In both cases stop.
+ */
+ if (csym->curr.tri != yes)
+ return false;
+
+ prop = sym_get_choice_prop(csym);
+
+ /* count entries in choice block */
+ cnt = 0;
+ expr_list_for_each_sym(prop->expr, e, sym)
+ cnt++;
+
+ /*
+ * find a random value and set it to yes,
+ * set the rest to no so we have only one set
+ */
+ def = rand() % cnt;
+
+ cnt = 0;
+ expr_list_for_each_sym(prop->expr, e, sym) {
+ if (def == cnt++) {
+ sym->def[S_DEF_USER].tri = yes;
+ csym->def[S_DEF_USER].val = sym;
+ } else {
+ sym->def[S_DEF_USER].tri = no;
+ }
+ sym->flags |= SYMBOL_DEF_USER;
+ /* clear VALID to get value calculated */
+ sym->flags &= ~SYMBOL_VALID;
+ }
+ csym->flags |= SYMBOL_DEF_USER;
+ /* clear VALID to get value calculated */
+ csym->flags &= ~SYMBOL_VALID;
+
+ return true;
+}
+
+enum conf_def_mode {
+ def_default,
+ def_yes,
+ def_mod,
+ def_no,
+ def_random
+};
+
+static bool conf_set_all_new_symbols(enum conf_def_mode mode)
+{
+ struct symbol *sym, *csym;
+ int i, cnt;
+ /*
+ * can't go as the default in switch-case below, otherwise gcc whines
+ * about -Wmaybe-uninitialized
+ */
+ int pby = 50; /* probability of bool = y */
+ int pty = 33; /* probability of tristate = y */
+ int ptm = 33; /* probability of tristate = m */
+ bool has_changed = false;
+
+ if (mode == def_random) {
+ int n, p[3];
+ char *env = getenv("KCONFIG_PROBABILITY");
+
+ n = 0;
+ while (env && *env) {
+ char *endp;
+ int tmp = strtol(env, &endp, 10);
+
+ if (tmp >= 0 && tmp <= 100) {
+ p[n++] = tmp;
+ } else {
+ errno = ERANGE;
+ perror("KCONFIG_PROBABILITY");
+ exit(1);
+ }
+ env = (*endp == ':') ? endp + 1 : endp;
+ if (n >= 3)
+ break;
+ }
+ switch (n) {
+ case 1:
+ pby = p[0];
+ ptm = pby / 2;
+ pty = pby - ptm;
+ break;
+ case 2:
+ pty = p[0];
+ ptm = p[1];
+ pby = pty + ptm;
+ break;
+ case 3:
+ pby = p[0];
+ pty = p[1];
+ ptm = p[2];
+ break;
+ }
+
+ if (pty + ptm > 100) {
+ errno = ERANGE;
+ perror("KCONFIG_PROBABILITY");
+ exit(1);
+ }
+ }
+
+ for_all_symbols(i, sym) {
+ if (sym_has_value(sym) || sym->flags & SYMBOL_VALID)
+ continue;
+ switch (sym_get_type(sym)) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ has_changed = true;
+ switch (mode) {
+ case def_yes:
+ sym->def[S_DEF_USER].tri = yes;
+ break;
+ case def_mod:
+ sym->def[S_DEF_USER].tri = mod;
+ break;
+ case def_no:
+ sym->def[S_DEF_USER].tri = no;
+ break;
+ case def_random:
+ sym->def[S_DEF_USER].tri = no;
+ cnt = rand() % 100;
+ if (sym->type == S_TRISTATE) {
+ if (cnt < pty)
+ sym->def[S_DEF_USER].tri = yes;
+ else if (cnt < pty + ptm)
+ sym->def[S_DEF_USER].tri = mod;
+ } else if (cnt < pby)
+ sym->def[S_DEF_USER].tri = yes;
+ break;
+ default:
+ continue;
+ }
+ if (!(sym_is_choice(sym) && mode == def_random))
+ sym->flags |= SYMBOL_DEF_USER;
+ break;
+ default:
+ break;
+ }
+
+ }
+
+ sym_clear_all_valid();
+
+ /*
+ * We have different type of choice blocks.
+ * If curr.tri equals to mod then we can select several
+ * choice symbols in one block.
+ * In this case we do nothing.
+ * If curr.tri equals yes then only one symbol can be
+ * selected in a choice block and we set it to yes,
+ * and the rest to no.
+ */
+ if (mode != def_random) {
+ for_all_symbols(i, csym) {
+ if ((sym_is_choice(csym) && !sym_has_value(csym)) ||
+ sym_is_choice_value(csym))
+ csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES;
+ }
+ }
+
+ for_all_symbols(i, csym) {
+ if (sym_has_value(csym) || !sym_is_choice(csym))
+ continue;
+
+ sym_calc_value(csym);
+ if (mode == def_random)
+ has_changed |= randomize_choice_values(csym);
+ else {
+ set_all_choice_values(csym);
+ has_changed = true;
+ }
+ }
+
+ return has_changed;
+}
+
+static void conf_rewrite_tristates(tristate old_val, tristate new_val)
+{
+ struct symbol *sym;
+ int i;
+
+ for_all_symbols(i, sym) {
+ if (sym_get_type(sym) == S_TRISTATE &&
+ sym->def[S_DEF_USER].tri == old_val)
+ sym->def[S_DEF_USER].tri = new_val;
+ }
+ sym_clear_all_valid();
+}
+
+static int conf_askvalue(struct symbol *sym, const char *def)
+{
+ if (!sym_has_value(sym))
+ printf("(NEW) ");
+
+ line[0] = '\n';
+ line[1] = 0;
+
+ if (!sym_is_changeable(sym)) {
+ printf("%s\n", def);
+ line[0] = '\n';
+ line[1] = 0;
+ return 0;
+ }
+
+ switch (input_mode) {
+ case oldconfig:
+ case syncconfig:
+ if (sym_has_value(sym)) {
+ printf("%s\n", def);
+ return 0;
+ }
+ /* fall through */
+ default:
+ fflush(stdout);
+ xfgets(line, sizeof(line), stdin);
+ break;
+ }
+
+ return 1;
+}
+
+static int conf_string(struct menu *menu)
+{
+ struct symbol *sym = menu->sym;
+ const char *def;
+
+ while (1) {
+ printf("%*s%s ", indent - 1, "", menu->prompt->text);
+ printf("(%s) ", sym->name);
+ def = sym_get_string_value(sym);
+ if (def)
+ printf("[%s] ", def);
+ if (!conf_askvalue(sym, def))
+ return 0;
+ switch (line[0]) {
+ case '\n':
+ break;
+ case '?':
+ /* print help */
+ if (line[1] == '\n') {
+ print_help(menu);
+ def = NULL;
+ break;
+ }
+ /* fall through */
+ default:
+ line[strlen(line)-1] = 0;
+ def = line;
+ }
+ if (def && sym_set_string_value(sym, def))
+ return 0;
+ }
+}
+
+static int conf_sym(struct menu *menu)
+{
+ struct symbol *sym = menu->sym;
+ tristate oldval, newval;
+
+ while (1) {
+ printf("%*s%s ", indent - 1, "", menu->prompt->text);
+ if (sym->name)
+ printf("(%s) ", sym->name);
+ putchar('[');
+ oldval = sym_get_tristate_value(sym);
+ switch (oldval) {
+ case no:
+ putchar('N');
+ break;
+ case mod:
+ putchar('M');
+ break;
+ case yes:
+ putchar('Y');
+ break;
+ }
+ if (oldval != no && sym_tristate_within_range(sym, no))
+ printf("/n");
+ if (oldval != mod && sym_tristate_within_range(sym, mod))
+ printf("/m");
+ if (oldval != yes && sym_tristate_within_range(sym, yes))
+ printf("/y");
+ printf("/?] ");
+ if (!conf_askvalue(sym, sym_get_string_value(sym)))
+ return 0;
+ strip(line);
+
+ switch (line[0]) {
+ case 'n':
+ case 'N':
+ newval = no;
+ if (!line[1] || !strcmp(&line[1], "o"))
+ break;
+ continue;
+ case 'm':
+ case 'M':
+ newval = mod;
+ if (!line[1])
+ break;
+ continue;
+ case 'y':
+ case 'Y':
+ newval = yes;
+ if (!line[1] || !strcmp(&line[1], "es"))
+ break;
+ continue;
+ case 0:
+ newval = oldval;
+ break;
+ case '?':
+ goto help;
+ default:
+ continue;
+ }
+ if (sym_set_tristate_value(sym, newval))
+ return 0;
+help:
+ print_help(menu);
+ }
+}
+
+static int conf_choice(struct menu *menu)
+{
+ struct symbol *sym, *def_sym;
+ struct menu *child;
+ bool is_new;
+
+ sym = menu->sym;
+ is_new = !sym_has_value(sym);
+ if (sym_is_changeable(sym)) {
+ conf_sym(menu);
+ sym_calc_value(sym);
+ switch (sym_get_tristate_value(sym)) {
+ case no:
+ return 1;
+ case mod:
+ return 0;
+ case yes:
+ break;
+ }
+ } else {
+ switch (sym_get_tristate_value(sym)) {
+ case no:
+ return 1;
+ case mod:
+ printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu));
+ return 0;
+ case yes:
+ break;
+ }
+ }
+
+ while (1) {
+ int cnt, def;
+
+ printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu));
+ def_sym = sym_get_choice_value(sym);
+ cnt = def = 0;
+ line[0] = 0;
+ for (child = menu->list; child; child = child->next) {
+ if (!menu_is_visible(child))
+ continue;
+ if (!child->sym) {
+ printf("%*c %s\n", indent, '*', menu_get_prompt(child));
+ continue;
+ }
+ cnt++;
+ if (child->sym == def_sym) {
+ def = cnt;
+ printf("%*c", indent, '>');
+ } else
+ printf("%*c", indent, ' ');
+ printf(" %d. %s", cnt, menu_get_prompt(child));
+ if (child->sym->name)
+ printf(" (%s)", child->sym->name);
+ if (!sym_has_value(child->sym))
+ printf(" (NEW)");
+ printf("\n");
+ }
+ printf("%*schoice", indent - 1, "");
+ if (cnt == 1) {
+ printf("[1]: 1\n");
+ goto conf_childs;
+ }
+ printf("[1-%d?]: ", cnt);
+ switch (input_mode) {
+ case oldconfig:
+ case syncconfig:
+ if (!is_new) {
+ cnt = def;
+ printf("%d\n", cnt);
+ break;
+ }
+ /* fall through */
+ case oldaskconfig:
+ fflush(stdout);
+ xfgets(line, sizeof(line), stdin);
+ strip(line);
+ if (line[0] == '?') {
+ print_help(menu);
+ continue;
+ }
+ if (!line[0])
+ cnt = def;
+ else if (isdigit(line[0]))
+ cnt = atoi(line);
+ else
+ continue;
+ break;
+ default:
+ break;
+ }
+
+ conf_childs:
+ for (child = menu->list; child; child = child->next) {
+ if (!child->sym || !menu_is_visible(child))
+ continue;
+ if (!--cnt)
+ break;
+ }
+ if (!child)
+ continue;
+ if (line[0] && line[strlen(line) - 1] == '?') {
+ print_help(child);
+ continue;
+ }
+ sym_set_tristate_value(child->sym, yes);
+ for (child = child->list; child; child = child->next) {
+ indent += 2;
+ conf(child);
+ indent -= 2;
+ }
+ return 1;
+ }
+}
+
+static void conf(struct menu *menu)
+{
+ struct symbol *sym;
+ struct property *prop;
+ struct menu *child;
+
+ if (!menu_is_visible(menu))
+ return;
+
+ sym = menu->sym;
+ prop = menu->prompt;
+ if (prop) {
+ const char *prompt;
+
+ switch (prop->type) {
+ case P_MENU:
+ /*
+ * Except in oldaskconfig mode, we show only menus that
+ * contain new symbols.
+ */
+ if (input_mode != oldaskconfig && rootEntry != menu) {
+ check_conf(menu);
+ return;
+ }
+ /* fall through */
+ case P_COMMENT:
+ prompt = menu_get_prompt(menu);
+ if (prompt)
+ printf("%*c\n%*c %s\n%*c\n",
+ indent, '*',
+ indent, '*', prompt,
+ indent, '*');
+ default:
+ ;
+ }
+ }
+
+ if (!sym)
+ goto conf_childs;
+
+ if (sym_is_choice(sym)) {
+ conf_choice(menu);
+ if (sym->curr.tri != mod)
+ return;
+ goto conf_childs;
+ }
+
+ switch (sym->type) {
+ case S_INT:
+ case S_HEX:
+ case S_STRING:
+ conf_string(menu);
+ break;
+ default:
+ conf_sym(menu);
+ break;
+ }
+
+conf_childs:
+ if (sym)
+ indent += 2;
+ for (child = menu->list; child; child = child->next)
+ conf(child);
+ if (sym)
+ indent -= 2;
+}
+
+static void check_conf(struct menu *menu)
+{
+ struct symbol *sym;
+ struct menu *child;
+
+ if (!menu_is_visible(menu))
+ return;
+
+ sym = menu->sym;
+ if (sym && !sym_has_value(sym) &&
+ (sym_is_changeable(sym) ||
+ (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes))) {
+
+ switch (input_mode) {
+ case listnewconfig:
+ if (sym->name)
+ print_symbol_for_listconfig(sym);
+ break;
+ case helpnewconfig:
+ printf("-----\n");
+ print_help(menu);
+ printf("-----\n");
+ break;
+ default:
+ if (!conf_cnt++)
+ printf("*\n* Restart config...\n*\n");
+ rootEntry = menu_get_parent_menu(menu);
+ conf(rootEntry);
+ break;
+ }
+ }
+
+ for (child = menu->list; child; child = child->next)
+ check_conf(child);
+}
+
+static const struct option long_opts[] = {
+ {"help", no_argument, NULL, 'h'},
+ {"silent", no_argument, NULL, 's'},
+ {"oldaskconfig", no_argument, &input_mode_opt, oldaskconfig},
+ {"oldconfig", no_argument, &input_mode_opt, oldconfig},
+ {"syncconfig", no_argument, &input_mode_opt, syncconfig},
+ {"defconfig", required_argument, &input_mode_opt, defconfig},
+ {"savedefconfig", required_argument, &input_mode_opt, savedefconfig},
+ {"allnoconfig", no_argument, &input_mode_opt, allnoconfig},
+ {"allyesconfig", no_argument, &input_mode_opt, allyesconfig},
+ {"allmodconfig", no_argument, &input_mode_opt, allmodconfig},
+ {"alldefconfig", no_argument, &input_mode_opt, alldefconfig},
+ {"randconfig", no_argument, &input_mode_opt, randconfig},
+ {"listnewconfig", no_argument, &input_mode_opt, listnewconfig},
+ {"helpnewconfig", no_argument, &input_mode_opt, helpnewconfig},
+ {"olddefconfig", no_argument, &input_mode_opt, olddefconfig},
+ {"yes2modconfig", no_argument, &input_mode_opt, yes2modconfig},
+ {"mod2yesconfig", no_argument, &input_mode_opt, mod2yesconfig},
+ {"mod2noconfig", no_argument, &input_mode_opt, mod2noconfig},
+ {NULL, 0, NULL, 0}
+};
+
+static void conf_usage(const char *progname)
+{
+ printf("Usage: %s [options] <kconfig-file>\n", progname);
+ printf("\n");
+ printf("Generic options:\n");
+ printf(" -h, --help Print this message and exit.\n");
+ printf(" -s, --silent Do not print log.\n");
+ printf("\n");
+ printf("Mode options:\n");
+ printf(" --listnewconfig List new options\n");
+ printf(" --helpnewconfig List new options and help text\n");
+ printf(" --oldaskconfig Start a new configuration using a line-oriented program\n");
+ printf(" --oldconfig Update a configuration using a provided .config as base\n");
+ printf(" --syncconfig Similar to oldconfig but generates configuration in\n"
+ " include/{generated/,config/}\n");
+ printf(" --olddefconfig Same as oldconfig but sets new symbols to their default value\n");
+ printf(" --defconfig <file> New config with default defined in <file>\n");
+ printf(" --savedefconfig <file> Save the minimal current configuration to <file>\n");
+ printf(" --allnoconfig New config where all options are answered with no\n");
+ printf(" --allyesconfig New config where all options are answered with yes\n");
+ printf(" --allmodconfig New config where all options are answered with mod\n");
+ printf(" --alldefconfig New config with all symbols set to default\n");
+ printf(" --randconfig New config with random answer to all options\n");
+ printf(" --yes2modconfig Change answers from yes to mod if possible\n");
+ printf(" --mod2yesconfig Change answers from mod to yes if possible\n");
+ printf(" --mod2noconfig Change answers from mod to no if possible\n");
+ printf(" (If none of the above is given, --oldaskconfig is the default)\n");
+}
+
+int main(int ac, char **av)
+{
+ const char *progname = av[0];
+ int opt;
+ const char *name, *defconfig_file = NULL /* gcc uninit */;
+ int no_conf_write = 0;
+
+ tty_stdio = isatty(0) && isatty(1);
+
+ while ((opt = getopt_long(ac, av, "hs", long_opts, NULL)) != -1) {
+ switch (opt) {
+ case 'h':
+ conf_usage(progname);
+ exit(1);
+ break;
+ case 's':
+ conf_set_message_callback(NULL);
+ break;
+ case 0:
+ input_mode = input_mode_opt;
+ switch (input_mode) {
+ case syncconfig:
+ /*
+ * syncconfig is invoked during the build stage.
+ * Suppress distracting
+ * "configuration written to ..."
+ */
+ conf_set_message_callback(NULL);
+ sync_kconfig = 1;
+ break;
+ case defconfig:
+ case savedefconfig:
+ defconfig_file = optarg;
+ break;
+ case randconfig:
+ set_randconfig_seed();
+ break;
+ default:
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ if (ac == optind) {
+ fprintf(stderr, "%s: Kconfig file missing\n", av[0]);
+ conf_usage(progname);
+ exit(1);
+ }
+ conf_parse(av[optind]);
+ //zconfdump(stdout);
+
+ switch (input_mode) {
+ case defconfig:
+ if (conf_read(defconfig_file)) {
+ fprintf(stderr,
+ "***\n"
+ "*** Can't find default configuration \"%s\"!\n"
+ "***\n",
+ defconfig_file);
+ exit(1);
+ }
+ break;
+ case savedefconfig:
+ case syncconfig:
+ case oldaskconfig:
+ case oldconfig:
+ case listnewconfig:
+ case helpnewconfig:
+ case olddefconfig:
+ case yes2modconfig:
+ case mod2yesconfig:
+ case mod2noconfig:
+ conf_read(NULL);
+ break;
+ case allnoconfig:
+ case allyesconfig:
+ case allmodconfig:
+ case alldefconfig:
+ case randconfig:
+ name = getenv("KCONFIG_ALLCONFIG");
+ if (!name)
+ break;
+ if ((strcmp(name, "") != 0) && (strcmp(name, "1") != 0)) {
+ if (conf_read_simple(name, S_DEF_USER)) {
+ fprintf(stderr,
+ "*** Can't read seed configuration \"%s\"!\n",
+ name);
+ exit(1);
+ }
+ break;
+ }
+ switch (input_mode) {
+ case allnoconfig: name = "allno.config"; break;
+ case allyesconfig: name = "allyes.config"; break;
+ case allmodconfig: name = "allmod.config"; break;
+ case alldefconfig: name = "alldef.config"; break;
+ case randconfig: name = "allrandom.config"; break;
+ default: break;
+ }
+ if (conf_read_simple(name, S_DEF_USER) &&
+ conf_read_simple("all.config", S_DEF_USER)) {
+ fprintf(stderr,
+ "*** KCONFIG_ALLCONFIG set, but no \"%s\" or \"all.config\" file found\n",
+ name);
+ exit(1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (sync_kconfig) {
+ name = getenv("KCONFIG_NOSILENTUPDATE");
+ if (name && *name) {
+ if (conf_get_changed()) {
+ fprintf(stderr,
+ "\n*** The configuration requires explicit update.\n\n");
+ return 1;
+ }
+ no_conf_write = 1;
+ }
+ }
+
+ switch (input_mode) {
+ case allnoconfig:
+ conf_set_all_new_symbols(def_no);
+ break;
+ case allyesconfig:
+ conf_set_all_new_symbols(def_yes);
+ break;
+ case allmodconfig:
+ conf_set_all_new_symbols(def_mod);
+ break;
+ case alldefconfig:
+ conf_set_all_new_symbols(def_default);
+ break;
+ case randconfig:
+ /* Really nothing to do in this loop */
+ while (conf_set_all_new_symbols(def_random)) ;
+ break;
+ case defconfig:
+ conf_set_all_new_symbols(def_default);
+ break;
+ case savedefconfig:
+ break;
+ case yes2modconfig:
+ conf_rewrite_tristates(yes, mod);
+ break;
+ case mod2yesconfig:
+ conf_rewrite_tristates(mod, yes);
+ break;
+ case mod2noconfig:
+ conf_rewrite_tristates(mod, no);
+ break;
+ case oldaskconfig:
+ rootEntry = &rootmenu;
+ conf(&rootmenu);
+ input_mode = oldconfig;
+ /* fall through */
+ case oldconfig:
+ case listnewconfig:
+ case helpnewconfig:
+ case syncconfig:
+ /* Update until a loop caused no more changes */
+ do {
+ conf_cnt = 0;
+ check_conf(&rootmenu);
+ } while (conf_cnt);
+ break;
+ case olddefconfig:
+ default:
+ break;
+ }
+
+ if (input_mode == savedefconfig) {
+ if (conf_write_defconfig(defconfig_file)) {
+ fprintf(stderr, "n*** Error while saving defconfig to: %s\n\n",
+ defconfig_file);
+ return 1;
+ }
+ } else if (input_mode != listnewconfig && input_mode != helpnewconfig) {
+ if (!no_conf_write && conf_write(NULL)) {
+ fprintf(stderr, "\n*** Error during writing of the configuration.\n\n");
+ exit(1);
+ }
+
+ /*
+ * Create auto.conf if it does not exist.
+ * This prevents GNU Make 4.1 or older from emitting
+ * "include/config/auto.conf: No such file or directory"
+ * in the top-level Makefile
+ *
+ * syncconfig always creates or updates auto.conf because it is
+ * used during the build.
+ */
+ if (conf_write_autoconf(sync_kconfig) && sync_kconfig) {
+ fprintf(stderr,
+ "\n*** Error during sync of the configuration.\n\n");
+ return 1;
+ }
+ }
+ return 0;
+}
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/confdata.c
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/confdata.c (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/confdata.c (revision 151)
@@ -0,0 +1,1265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
+ */
+
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <ctype.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <linux/limits.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+
+#include "lkc.h"
+
+/* return true if 'path' exists, false otherwise */
+static bool is_present(const char *path)
+{
+ struct stat st;
+
+ return !stat(path, &st);
+}
+
+/* return true if 'path' exists and it is a directory, false otherwise */
+static bool is_dir(const char *path)
+{
+ struct stat st;
+
+ if (stat(path, &st))
+ return false;
+
+ return S_ISDIR(st.st_mode);
+}
+
+/* return true if the given two files are the same, false otherwise */
+static bool is_same(const char *file1, const char *file2)
+{
+ int fd1, fd2;
+ struct stat st1, st2;
+ void *map1, *map2;
+ bool ret = false;
+
+ fd1 = open(file1, O_RDONLY);
+ if (fd1 < 0)
+ return ret;
+
+ fd2 = open(file2, O_RDONLY);
+ if (fd2 < 0)
+ goto close1;
+
+ ret = fstat(fd1, &st1);
+ if (ret)
+ goto close2;
+ ret = fstat(fd2, &st2);
+ if (ret)
+ goto close2;
+
+ if (st1.st_size != st2.st_size)
+ goto close2;
+
+ map1 = mmap(NULL, st1.st_size, PROT_READ, MAP_PRIVATE, fd1, 0);
+ if (map1 == MAP_FAILED)
+ goto close2;
+
+ map2 = mmap(NULL, st2.st_size, PROT_READ, MAP_PRIVATE, fd2, 0);
+ if (map2 == MAP_FAILED)
+ goto close2;
+
+ if (bcmp(map1, map2, st1.st_size))
+ goto close2;
+
+ ret = true;
+close2:
+ close(fd2);
+close1:
+ close(fd1);
+
+ return ret;
+}
+
+/*
+ * Create the parent directory of the given path.
+ *
+ * For example, if 'include/config/auto.conf' is given, create 'include/config'.
+ */
+static int make_parent_dir(const char *path)
+{
+ char tmp[PATH_MAX + 1];
+ char *p;
+
+ strncpy(tmp, path, sizeof(tmp));
+ tmp[sizeof(tmp) - 1] = 0;
+
+ /* Remove the base name. Just return if nothing is left */
+ p = strrchr(tmp, '/');
+ if (!p)
+ return 0;
+ *(p + 1) = 0;
+
+ /* Just in case it is an absolute path */
+ p = tmp;
+ while (*p == '/')
+ p++;
+
+ while ((p = strchr(p, '/'))) {
+ *p = 0;
+
+ /* skip if the directory exists */
+ if (!is_dir(tmp) && mkdir(tmp, 0755))
+ return -1;
+
+ *p = '/';
+ while (*p == '/')
+ p++;
+ }
+
+ return 0;
+}
+
+static char depfile_path[PATH_MAX];
+static size_t depfile_prefix_len;
+
+/* touch depfile for symbol 'name' */
+static int conf_touch_dep(const char *name)
+{
+ int fd;
+
+ /* check overflow: prefix + name + '\0' must fit in buffer. */
+ if (depfile_prefix_len + strlen(name) + 1 > sizeof(depfile_path))
+ return -1;
+
+ strcpy(depfile_path + depfile_prefix_len, name);
+
+ fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+ if (fd == -1)
+ return -1;
+ close(fd);
+
+ return 0;
+}
+
+static void conf_warning(const char *fmt, ...)
+ __attribute__ ((format (printf, 1, 2)));
+
+static void conf_message(const char *fmt, ...)
+ __attribute__ ((format (printf, 1, 2)));
+
+static const char *conf_filename;
+static int conf_lineno, conf_warnings;
+
+static void conf_warning(const char *fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+ fprintf(stderr, "%s:%d:warning: ", conf_filename, conf_lineno);
+ vfprintf(stderr, fmt, ap);
+ fprintf(stderr, "\n");
+ va_end(ap);
+ conf_warnings++;
+}
+
+static void conf_default_message_callback(const char *s)
+{
+ printf("#\n# ");
+ printf("%s", s);
+ printf("\n#\n");
+}
+
+static void (*conf_message_callback)(const char *s) =
+ conf_default_message_callback;
+void conf_set_message_callback(void (*fn)(const char *s))
+{
+ conf_message_callback = fn;
+}
+
+static void conf_message(const char *fmt, ...)
+{
+ va_list ap;
+ char buf[4096];
+
+ if (!conf_message_callback)
+ return;
+
+ va_start(ap, fmt);
+
+ vsnprintf(buf, sizeof(buf), fmt, ap);
+ conf_message_callback(buf);
+ va_end(ap);
+}
+
+const char *conf_get_configname(void)
+{
+ char *name = getenv("KCONFIG_CONFIG");
+
+ return name ? name : ".config";
+}
+
+static const char *conf_get_autoconfig_name(void)
+{
+ char *name = getenv("KCONFIG_AUTOCONFIG");
+
+ return name ? name : "include/config/auto.conf";
+}
+
+static const char *conf_get_autoheader_name(void)
+{
+ char *name = getenv("KCONFIG_AUTOHEADER");
+
+ return name ? name : "include/generated/autoconf.h";
+}
+
+static const char *conf_get_rustccfg_name(void)
+{
+ char *name = getenv("KCONFIG_RUSTCCFG");
+
+ return name ? name : "include/generated/rustc_cfg";
+}
+
+static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
+{
+ char *p2;
+
+ switch (sym->type) {
+ case S_TRISTATE:
+ if (p[0] == 'm') {
+ sym->def[def].tri = mod;
+ sym->flags |= def_flags;
+ break;
+ }
+ /* fall through */
+ case S_BOOLEAN:
+ if (p[0] == 'y') {
+ sym->def[def].tri = yes;
+ sym->flags |= def_flags;
+ break;
+ }
+ if (p[0] == 'n') {
+ sym->def[def].tri = no;
+ sym->flags |= def_flags;
+ break;
+ }
+ if (def != S_DEF_AUTO)
+ conf_warning("symbol value '%s' invalid for %s",
+ p, sym->name);
+ return 1;
+ case S_STRING:
+ /* No escaping for S_DEF_AUTO (include/config/auto.conf) */
+ if (def != S_DEF_AUTO) {
+ if (*p++ != '"')
+ break;
+ for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) {
+ if (*p2 == '"') {
+ *p2 = 0;
+ break;
+ }
+ memmove(p2, p2 + 1, strlen(p2));
+ }
+ if (!p2) {
+ conf_warning("invalid string found");
+ return 1;
+ }
+ }
+ /* fall through */
+ case S_INT:
+ case S_HEX:
+ if (sym_string_valid(sym, p)) {
+ sym->def[def].val = xstrdup(p);
+ sym->flags |= def_flags;
+ } else {
+ if (def != S_DEF_AUTO)
+ conf_warning("symbol value '%s' invalid for %s",
+ p, sym->name);
+ return 1;
+ }
+ break;
+ default:
+ ;
+ }
+ return 0;
+}
+
+#define LINE_GROWTH 16
+static int add_byte(int c, char **lineptr, size_t slen, size_t *n)
+{
+ char *nline;
+ size_t new_size = slen + 1;
+ if (new_size > *n) {
+ new_size += LINE_GROWTH - 1;
+ new_size *= 2;
+ nline = xrealloc(*lineptr, new_size);
+ if (!nline)
+ return -1;
+
+ *lineptr = nline;
+ *n = new_size;
+ }
+
+ (*lineptr)[slen] = c;
+
+ return 0;
+}
+
+static ssize_t compat_getline(char **lineptr, size_t *n, FILE *stream)
+{
+ char *line = *lineptr;
+ size_t slen = 0;
+
+ for (;;) {
+ int c = getc(stream);
+
+ switch (c) {
+ case '\n':
+ if (add_byte(c, &line, slen, n) < 0)
+ goto e_out;
+ slen++;
+ /* fall through */
+ case EOF:
+ if (add_byte('\0', &line, slen, n) < 0)
+ goto e_out;
+ *lineptr = line;
+ if (slen == 0)
+ return -1;
+ return slen;
+ default:
+ if (add_byte(c, &line, slen, n) < 0)
+ goto e_out;
+ slen++;
+ }
+ }
+
+e_out:
+ line[slen-1] = '\0';
+ *lineptr = line;
+ return -1;
+}
+
+int conf_read_simple(const char *name, int def)
+{
+ FILE *in = NULL;
+ char *line = NULL;
+ size_t line_asize = 0;
+ char *p, *p2;
+ struct symbol *sym;
+ int i, def_flags;
+
+ if (name) {
+ in = zconf_fopen(name);
+ } else {
+ char *env;
+
+ name = conf_get_configname();
+ in = zconf_fopen(name);
+ if (in)
+ goto load;
+ conf_set_changed(true);
+
+ env = getenv("KCONFIG_DEFCONFIG_LIST");
+ if (!env)
+ return 1;
+
+ while (1) {
+ bool is_last;
+
+ while (isspace(*env))
+ env++;
+
+ if (!*env)
+ break;
+
+ p = env;
+ while (*p && !isspace(*p))
+ p++;
+
+ is_last = (*p == '\0');
+
+ *p = '\0';
+
+ in = zconf_fopen(env);
+ if (in) {
+ conf_message("using defaults found in %s",
+ env);
+ goto load;
+ }
+
+ if (is_last)
+ break;
+
+ env = p + 1;
+ }
+ }
+ if (!in)
+ return 1;
+
+load:
+ conf_filename = name;
+ conf_lineno = 0;
+ conf_warnings = 0;
+
+ def_flags = SYMBOL_DEF << def;
+ for_all_symbols(i, sym) {
+ sym->flags |= SYMBOL_CHANGED;
+ sym->flags &= ~(def_flags|SYMBOL_VALID);
+ if (sym_is_choice(sym))
+ sym->flags |= def_flags;
+ switch (sym->type) {
+ case S_INT:
+ case S_HEX:
+ case S_STRING:
+ if (sym->def[def].val)
+ free(sym->def[def].val);
+ /* fall through */
+ default:
+ sym->def[def].val = NULL;
+ sym->def[def].tri = no;
+ }
+ }
+
+ while (compat_getline(&line, &line_asize, in) != -1) {
+ conf_lineno++;
+ sym = NULL;
+ if (line[0] == '#') {
+ if (memcmp(line + 2, CONFIG_, strlen(CONFIG_)))
+ continue;
+ p = strchr(line + 2 + strlen(CONFIG_), ' ');
+ if (!p)
+ continue;
+ *p++ = 0;
+ if (strncmp(p, "is not set", 10))
+ continue;
+ if (def == S_DEF_USER) {
+ sym = sym_find(line + 2 + strlen(CONFIG_));
+ if (!sym) {
+ conf_set_changed(true);
+ continue;
+ }
+ } else {
+ sym = sym_lookup(line + 2 + strlen(CONFIG_), 0);
+ if (sym->type == S_UNKNOWN)
+ sym->type = S_BOOLEAN;
+ }
+ if (sym->flags & def_flags) {
+ conf_warning("override: reassigning to symbol %s", sym->name);
+ }
+ switch (sym->type) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ sym->def[def].tri = no;
+ sym->flags |= def_flags;
+ break;
+ default:
+ ;
+ }
+ } else if (memcmp(line, CONFIG_, strlen(CONFIG_)) == 0) {
+ p = strchr(line + strlen(CONFIG_), '=');
+ if (!p)
+ continue;
+ *p++ = 0;
+ p2 = strchr(p, '\n');
+ if (p2) {
+ *p2-- = 0;
+ if (*p2 == '\r')
+ *p2 = 0;
+ }
+
+ sym = sym_find(line + strlen(CONFIG_));
+ if (!sym) {
+ if (def == S_DEF_AUTO)
+ /*
+ * Reading from include/config/auto.conf
+ * If CONFIG_FOO previously existed in
+ * auto.conf but it is missing now,
+ * include/config/FOO must be touched.
+ */
+ conf_touch_dep(line + strlen(CONFIG_));
+ else
+ conf_set_changed(true);
+ continue;
+ }
+
+ if (sym->flags & def_flags) {
+ conf_warning("override: reassigning to symbol %s", sym->name);
+ }
+ if (conf_set_sym_val(sym, def, def_flags, p))
+ continue;
+ } else {
+ if (line[0] != '\r' && line[0] != '\n')
+ conf_warning("unexpected data: %.*s",
+ (int)strcspn(line, "\r\n"), line);
+
+ continue;
+ }
+
+ if (sym && sym_is_choice_value(sym)) {
+ struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));
+ switch (sym->def[def].tri) {
+ case no:
+ break;
+ case mod:
+ if (cs->def[def].tri == yes) {
+ conf_warning("%s creates inconsistent choice state", sym->name);
+ cs->flags &= ~def_flags;
+ }
+ break;
+ case yes:
+ if (cs->def[def].tri != no)
+ conf_warning("override: %s changes choice state", sym->name);
+ cs->def[def].val = sym;
+ break;
+ }
+ cs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri);
+ }
+ }
+ free(line);
+ fclose(in);
+ return 0;
+}
+
+int conf_read(const char *name)
+{
+ struct symbol *sym;
+ int conf_unsaved = 0;
+ int i;
+
+ conf_set_changed(false);
+
+ if (conf_read_simple(name, S_DEF_USER)) {
+ sym_calc_value(modules_sym);
+ return 1;
+ }
+
+ sym_calc_value(modules_sym);
+
+ for_all_symbols(i, sym) {
+ sym_calc_value(sym);
+ if (sym_is_choice(sym) || (sym->flags & SYMBOL_NO_WRITE))
+ continue;
+ if (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) {
+ /* check that calculated value agrees with saved value */
+ switch (sym->type) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ if (sym->def[S_DEF_USER].tri == sym_get_tristate_value(sym))
+ continue;
+ break;
+ default:
+ if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val))
+ continue;
+ break;
+ }
+ } else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE))
+ /* no previous value and not saved */
+ continue;
+ conf_unsaved++;
+ /* maybe print value in verbose mode... */
+ }
+
+ for_all_symbols(i, sym) {
+ if (sym_has_value(sym) && !sym_is_choice_value(sym)) {
+ /* Reset values of generates values, so they'll appear
+ * as new, if they should become visible, but that
+ * doesn't quite work if the Kconfig and the saved
+ * configuration disagree.
+ */
+ if (sym->visible == no && !conf_unsaved)
+ sym->flags &= ~SYMBOL_DEF_USER;
+ switch (sym->type) {
+ case S_STRING:
+ case S_INT:
+ case S_HEX:
+ /* Reset a string value if it's out of range */
+ if (sym_string_within_range(sym, sym->def[S_DEF_USER].val))
+ break;
+ sym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER);
+ conf_unsaved++;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ if (conf_warnings || conf_unsaved)
+ conf_set_changed(true);
+
+ return 0;
+}
+
+struct comment_style {
+ const char *decoration;
+ const char *prefix;
+ const char *postfix;
+};
+
+static const struct comment_style comment_style_pound = {
+ .decoration = "#",
+ .prefix = "#",
+ .postfix = "#",
+};
+
+static const struct comment_style comment_style_c = {
+ .decoration = " *",
+ .prefix = "/*",
+ .postfix = " */",
+};
+
+static void conf_write_heading(FILE *fp, const struct comment_style *cs)
+{
+ if (!cs)
+ return;
+
+ fprintf(fp, "%s\n", cs->prefix);
+
+ fprintf(fp, "%s Automatically generated file; DO NOT EDIT.\n",
+ cs->decoration);
+
+ fprintf(fp, "%s %s\n", cs->decoration, rootmenu.prompt->text);
+
+ fprintf(fp, "%s\n", cs->postfix);
+}
+
+/* The returned pointer must be freed on the caller side */
+static char *escape_string_value(const char *in)
+{
+ const char *p;
+ char *out;
+ size_t len;
+
+ len = strlen(in) + strlen("\"\"") + 1;
+
+ p = in;
+ while (1) {
+ p += strcspn(p, "\"\\");
+
+ if (p[0] == '\0')
+ break;
+
+ len++;
+ p++;
+ }
+
+ out = xmalloc(len);
+ out[0] = '\0';
+
+ strcat(out, "\"");
+
+ p = in;
+ while (1) {
+ len = strcspn(p, "\"\\");
+ strncat(out, p, len);
+ p += len;
+
+ if (p[0] == '\0')
+ break;
+
+ strcat(out, "\\");
+ strncat(out, p++, 1);
+ }
+
+ strcat(out, "\"");
+
+ return out;
+}
+
+enum output_n { OUTPUT_N, OUTPUT_N_AS_UNSET, OUTPUT_N_NONE };
+
+static void __print_symbol(FILE *fp, struct symbol *sym, enum output_n output_n,
+ bool escape_string)
+{
+ const char *val;
+ char *escaped = NULL;
+
+ if (sym->type == S_UNKNOWN)
+ return;
+
+ val = sym_get_string_value(sym);
+
+ if ((sym->type == S_BOOLEAN || sym->type == S_TRISTATE) &&
+ output_n != OUTPUT_N && *val == 'n') {
+ if (output_n == OUTPUT_N_AS_UNSET)
+ fprintf(fp, "# %s%s is not set\n", CONFIG_, sym->name);
+ return;
+ }
+
+ if (sym->type == S_STRING && escape_string) {
+ escaped = escape_string_value(val);
+ val = escaped;
+ }
+
+ fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, val);
+
+ free(escaped);
+}
+
+static void print_symbol_for_dotconfig(FILE *fp, struct symbol *sym)
+{
+ __print_symbol(fp, sym, OUTPUT_N_AS_UNSET, true);
+}
+
+static void print_symbol_for_autoconf(FILE *fp, struct symbol *sym)
+{
+ __print_symbol(fp, sym, OUTPUT_N_NONE, false);
+}
+
+void print_symbol_for_listconfig(struct symbol *sym)
+{
+ __print_symbol(stdout, sym, OUTPUT_N, true);
+}
+
+static void print_symbol_for_c(FILE *fp, struct symbol *sym)
+{
+ const char *val;
+ const char *sym_suffix = "";
+ const char *val_prefix = "";
+ char *escaped = NULL;
+
+ if (sym->type == S_UNKNOWN)
+ return;
+
+ val = sym_get_string_value(sym);
+
+ switch (sym->type) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ switch (*val) {
+ case 'n':
+ return;
+ case 'm':
+ sym_suffix = "_MODULE";
+ /* fall through */
+ default:
+ val = "1";
+ }
+ break;
+ case S_HEX:
+ if (val[0] != '0' || (val[1] != 'x' && val[1] != 'X'))
+ val_prefix = "0x";
+ break;
+ case S_STRING:
+ escaped = escape_string_value(val);
+ val = escaped;
+ default:
+ break;
+ }
+
+ fprintf(fp, "#define %s%s%s %s%s\n", CONFIG_, sym->name, sym_suffix,
+ val_prefix, val);
+
+ free(escaped);
+}
+
+static void print_symbol_for_rustccfg(FILE *fp, struct symbol *sym)
+{
+ const char *val;
+ const char *val_prefix = "";
+ char *val_prefixed = NULL;
+ size_t val_prefixed_len;
+ char *escaped = NULL;
+
+ if (sym->type == S_UNKNOWN)
+ return;
+
+ val = sym_get_string_value(sym);
+
+ switch (sym->type) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ /*
+ * We do not care about disabled ones, i.e. no need for
+ * what otherwise are "comments" in other printers.
+ */
+ if (*val == 'n')
+ return;
+
+ /*
+ * To have similar functionality to the C macro `IS_ENABLED()`
+ * we provide an empty `--cfg CONFIG_X` here in both `y`
+ * and `m` cases.
+ *
+ * Then, the common `fprintf()` below will also give us
+ * a `--cfg CONFIG_X="y"` or `--cfg CONFIG_X="m"`, which can
+ * be used as the equivalent of `IS_BUILTIN()`/`IS_MODULE()`.
+ */
+ fprintf(fp, "--cfg=%s%s\n", CONFIG_, sym->name);
+ break;
+ case S_HEX:
+ if (val[0] != '0' || (val[1] != 'x' && val[1] != 'X'))
+ val_prefix = "0x";
+ break;
+ default:
+ break;
+ }
+
+ if (strlen(val_prefix) > 0) {
+ val_prefixed_len = strlen(val) + strlen(val_prefix) + 1;
+ val_prefixed = xmalloc(val_prefixed_len);
+ snprintf(val_prefixed, val_prefixed_len, "%s%s", val_prefix, val);
+ val = val_prefixed;
+ }
+
+ /* All values get escaped: the `--cfg` option only takes strings */
+ escaped = escape_string_value(val);
+ val = escaped;
+
+ fprintf(fp, "--cfg=%s%s=%s\n", CONFIG_, sym->name, val);
+
+ free(escaped);
+ free(val_prefixed);
+}
+
+/*
+ * Write out a minimal config.
+ * All values that has default values are skipped as this is redundant.
+ */
+int conf_write_defconfig(const char *filename)
+{
+ struct symbol *sym;
+ struct menu *menu;
+ FILE *out;
+
+ out = fopen(filename, "w");
+ if (!out)
+ return 1;
+
+ sym_clear_all_valid();
+
+ /* Traverse all menus to find all relevant symbols */
+ menu = rootmenu.list;
+
+ while (menu != NULL)
+ {
+ sym = menu->sym;
+ if (sym == NULL) {
+ if (!menu_is_visible(menu))
+ goto next_menu;
+ } else if (!sym_is_choice(sym)) {
+ sym_calc_value(sym);
+ if (!(sym->flags & SYMBOL_WRITE))
+ goto next_menu;
+ sym->flags &= ~SYMBOL_WRITE;
+ /* If we cannot change the symbol - skip */
+ if (!sym_is_changeable(sym))
+ goto next_menu;
+ /* If symbol equals to default value - skip */
+ if (strcmp(sym_get_string_value(sym), sym_get_string_default(sym)) == 0)
+ goto next_menu;
+
+ /*
+ * If symbol is a choice value and equals to the
+ * default for a choice - skip.
+ * But only if value is bool and equal to "y" and
+ * choice is not "optional".
+ * (If choice is "optional" then all values can be "n")
+ */
+ if (sym_is_choice_value(sym)) {
+ struct symbol *cs;
+ struct symbol *ds;
+
+ cs = prop_get_symbol(sym_get_choice_prop(sym));
+ ds = sym_choice_default(cs);
+ if (!sym_is_optional(cs) && sym == ds) {
+ if ((sym->type == S_BOOLEAN) &&
+ sym_get_tristate_value(sym) == yes)
+ goto next_menu;
+ }
+ }
+ print_symbol_for_dotconfig(out, sym);
+ }
+next_menu:
+ if (menu->list != NULL) {
+ menu = menu->list;
+ }
+ else if (menu->next != NULL) {
+ menu = menu->next;
+ } else {
+ while ((menu = menu->parent)) {
+ if (menu->next != NULL) {
+ menu = menu->next;
+ break;
+ }
+ }
+ }
+ }
+ fclose(out);
+ return 0;
+}
+
+int conf_write(const char *name)
+{
+ FILE *out;
+ struct symbol *sym;
+ struct menu *menu;
+ const char *str;
+ char tmpname[PATH_MAX + 1], oldname[PATH_MAX + 1];
+ char *env;
+ int i;
+ bool need_newline = false;
+
+ if (!name)
+ name = conf_get_configname();
+
+ if (!*name) {
+ fprintf(stderr, "config name is empty\n");
+ return -1;
+ }
+
+ if (is_dir(name)) {
+ fprintf(stderr, "%s: Is a directory\n", name);
+ return -1;
+ }
+
+ if (make_parent_dir(name))
+ return -1;
+
+ env = getenv("KCONFIG_OVERWRITECONFIG");
+ if (env && *env) {
+ *tmpname = 0;
+ out = fopen(name, "w");
+ } else {
+ snprintf(tmpname, sizeof(tmpname), "%s.%d.tmp",
+ name, (int)getpid());
+ out = fopen(tmpname, "w");
+ }
+ if (!out)
+ return 1;
+
+ conf_write_heading(out, &comment_style_pound);
+
+ if (!conf_get_changed())
+ sym_clear_all_valid();
+
+ menu = rootmenu.list;
+ while (menu) {
+ sym = menu->sym;
+ if (!sym) {
+ if (!menu_is_visible(menu))
+ goto next;
+ str = menu_get_prompt(menu);
+ fprintf(out, "\n"
+ "#\n"
+ "# %s\n"
+ "#\n", str);
+ need_newline = false;
+ } else if (!(sym->flags & SYMBOL_CHOICE) &&
+ !(sym->flags & SYMBOL_WRITTEN)) {
+ sym_calc_value(sym);
+ if (!(sym->flags & SYMBOL_WRITE))
+ goto next;
+ if (need_newline) {
+ fprintf(out, "\n");
+ need_newline = false;
+ }
+ sym->flags |= SYMBOL_WRITTEN;
+ print_symbol_for_dotconfig(out, sym);
+ }
+
+next:
+ if (menu->list) {
+ menu = menu->list;
+ continue;
+ }
+
+end_check:
+ if (!menu->sym && menu_is_visible(menu) && menu != &rootmenu &&
+ menu->prompt->type == P_MENU) {
+ fprintf(out, "# end of %s\n", menu_get_prompt(menu));
+ need_newline = true;
+ }
+
+ if (menu->next) {
+ menu = menu->next;
+ } else {
+ menu = menu->parent;
+ if (menu)
+ goto end_check;
+ }
+ }
+ fclose(out);
+
+ for_all_symbols(i, sym)
+ sym->flags &= ~SYMBOL_WRITTEN;
+
+ if (*tmpname) {
+ if (is_same(name, tmpname)) {
+ conf_message("No change to %s", name);
+ unlink(tmpname);
+ conf_set_changed(false);
+ return 0;
+ }
+
+ snprintf(oldname, sizeof(oldname), "%s.old", name);
+ rename(name, oldname);
+ if (rename(tmpname, name))
+ return 1;
+ }
+
+ conf_message("configuration written to %s", name);
+
+ conf_set_changed(false);
+
+ return 0;
+}
+
+/* write a dependency file as used by kbuild to track dependencies */
+static int conf_write_autoconf_cmd(const char *autoconf_name)
+{
+ char name[PATH_MAX], tmp[PATH_MAX];
+ struct file *file;
+ FILE *out;
+ int ret;
+
+ ret = snprintf(name, sizeof(name), "%s.cmd", autoconf_name);
+ if (ret >= sizeof(name)) /* check truncation */
+ return -1;
+
+ if (make_parent_dir(name))
+ return -1;
+
+ ret = snprintf(tmp, sizeof(tmp), "%s.cmd.tmp", autoconf_name);
+ if (ret >= sizeof(tmp)) /* check truncation */
+ return -1;
+
+ out = fopen(tmp, "w");
+ if (!out) {
+ perror("fopen");
+ return -1;
+ }
+
+ fprintf(out, "deps_config := \\\n");
+ for (file = file_list; file; file = file->next)
+ fprintf(out, "\t%s \\\n", file->name);
+
+ fprintf(out, "\n%s: $(deps_config)\n\n", autoconf_name);
+
+ env_write_dep(out, autoconf_name);
+
+ fprintf(out, "\n$(deps_config): ;\n");
+
+ fflush(out);
+ ret = ferror(out); /* error check for all fprintf() calls */
+ fclose(out);
+ if (ret)
+ return -1;
+
+ if (rename(tmp, name)) {
+ perror("rename");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int conf_touch_deps(void)
+{
+ const char *name, *tmp;
+ struct symbol *sym;
+ int res, i;
+
+ name = conf_get_autoconfig_name();
+ tmp = strrchr(name, '/');
+ depfile_prefix_len = tmp ? tmp - name + 1 : 0;
+ if (depfile_prefix_len + 1 > sizeof(depfile_path))
+ return -1;
+
+ strncpy(depfile_path, name, depfile_prefix_len);
+ depfile_path[depfile_prefix_len] = 0;
+
+ conf_read_simple(name, S_DEF_AUTO);
+ sym_calc_value(modules_sym);
+
+ for_all_symbols(i, sym) {
+ sym_calc_value(sym);
+ if ((sym->flags & SYMBOL_NO_WRITE) || !sym->name)
+ continue;
+ if (sym->flags & SYMBOL_WRITE) {
+ if (sym->flags & SYMBOL_DEF_AUTO) {
+ /*
+ * symbol has old and new value,
+ * so compare them...
+ */
+ switch (sym->type) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ if (sym_get_tristate_value(sym) ==
+ sym->def[S_DEF_AUTO].tri)
+ continue;
+ break;
+ case S_STRING:
+ case S_HEX:
+ case S_INT:
+ if (!strcmp(sym_get_string_value(sym),
+ sym->def[S_DEF_AUTO].val))
+ continue;
+ break;
+ default:
+ break;
+ }
+ } else {
+ /*
+ * If there is no old value, only 'no' (unset)
+ * is allowed as new value.
+ */
+ switch (sym->type) {
+ case S_BOOLEAN:
+ case S_TRISTATE:
+ if (sym_get_tristate_value(sym) == no)
+ continue;
+ break;
+ default:
+ break;
+ }
+ }
+ } else if (!(sym->flags & SYMBOL_DEF_AUTO))
+ /* There is neither an old nor a new value. */
+ continue;
+ /* else
+ * There is an old value, but no new value ('no' (unset)
+ * isn't saved in auto.conf, so the old value is always
+ * different from 'no').
+ */
+
+ res = conf_touch_dep(sym->name);
+ if (res)
+ return res;
+ }
+
+ return 0;
+}
+
+static int __conf_write_autoconf(const char *filename,
+ void (*print_symbol)(FILE *, struct symbol *),
+ const struct comment_style *comment_style)
+{
+ char tmp[PATH_MAX];
+ FILE *file;
+ struct symbol *sym;
+ int ret, i;
+
+ if (make_parent_dir(filename))
+ return -1;
+
+ ret = snprintf(tmp, sizeof(tmp), "%s.tmp", filename);
+ if (ret >= sizeof(tmp)) /* check truncation */
+ return -1;
+
+ file = fopen(tmp, "w");
+ if (!file) {
+ perror("fopen");
+ return -1;
+ }
+
+ conf_write_heading(file, comment_style);
+
+ for_all_symbols(i, sym)
+ if ((sym->flags & SYMBOL_WRITE) && sym->name)
+ print_symbol(file, sym);
+
+ fflush(file);
+ /* check possible errors in conf_write_heading() and print_symbol() */
+ ret = ferror(file);
+ fclose(file);
+ if (ret)
+ return -1;
+
+ if (rename(tmp, filename)) {
+ perror("rename");
+ return -1;
+ }
+
+ return 0;
+}
+
+int conf_write_autoconf(int overwrite)
+{
+ struct symbol *sym;
+ const char *autoconf_name = conf_get_autoconfig_name();
+ int ret, i;
+
+ if (!overwrite && is_present(autoconf_name))
+ return 0;
+
+ ret = conf_write_autoconf_cmd(autoconf_name);
+ if (ret)
+ return -1;
+
+ if (conf_touch_deps())
+ return 1;
+
+ for_all_symbols(i, sym)
+ sym_calc_value(sym);
+
+ ret = __conf_write_autoconf(conf_get_autoheader_name(),
+ print_symbol_for_c,
+ &comment_style_c);
+ if (ret)
+ return ret;
+
+ ret = __conf_write_autoconf(conf_get_rustccfg_name(),
+ print_symbol_for_rustccfg,
+ NULL);
+ if (ret)
+ return ret;
+
+ /*
+ * Create include/config/auto.conf. This must be the last step because
+ * Kbuild has a dependency on auto.conf and this marks the successful
+ * completion of the previous steps.
+ */
+ ret = __conf_write_autoconf(conf_get_autoconfig_name(),
+ print_symbol_for_autoconf,
+ &comment_style_pound);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static bool conf_changed;
+static void (*conf_changed_callback)(void);
+
+void conf_set_changed(bool val)
+{
+ bool changed = conf_changed != val;
+
+ conf_changed = val;
+
+ if (conf_changed_callback && changed)
+ conf_changed_callback();
+}
+
+bool conf_get_changed(void)
+{
+ return conf_changed;
+}
+
+void conf_set_changed_callback(void (*fn)(void))
+{
+ conf_changed_callback = fn;
+}
+
+void set_all_choice_values(struct symbol *csym)
+{
+ struct property *prop;
+ struct symbol *sym;
+ struct expr *e;
+
+ prop = sym_get_choice_prop(csym);
+
+ /*
+ * Set all non-assinged choice values to no
+ */
+ expr_list_for_each_sym(prop->expr, e, sym) {
+ if (!sym_has_value(sym))
+ sym->def[S_DEF_USER].tri = no;
+ }
+ csym->flags |= SYMBOL_DEF_USER;
+ /* clear VALID to get value calculated */
+ csym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES);
+}
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/lexer.l
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/lexer.l (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/kconfig/lexer.l (revision 151)
@@ -0,0 +1,468 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
+ */
+%option nostdinit noyywrap never-interactive full ecs
+%option 8bit nodefault yylineno
+%x ASSIGN_VAL HELP STRING
+%{
+
+#include <assert.h>
+#include <linux/limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "lkc.h"
+#include "parser.tab.h"
+
+#define YY_DECL static int yylex1(void)
+
+#define START_STRSIZE 16
+
+static struct {
+ struct file *file;
+ int lineno;
+} current_pos;
+
+static int prev_prev_token = T_EOL;
+static int prev_token = T_EOL;
+static char *text;
+static int text_size, text_asize;
+
+struct buffer {
+ struct buffer *parent;
+ YY_BUFFER_STATE state;
+};
+
+static struct buffer *current_buf;
+
+static int last_ts, first_ts;
+
+static char *expand_token(const char *in, size_t n);
+static void append_expanded_string(const char *in);
+static void zconf_endhelp(void);
+static void zconf_endfile(void);
+
+static void new_string(void)
+{
+ text = xmalloc(START_STRSIZE);
+ text_asize = START_STRSIZE;
+ text_size = 0;
+ *text = 0;
+}
+
+static void append_string(const char *str, int size)
+{
+ int new_size = text_size + size + 1;
+ if (new_size > text_asize) {
+ new_size += START_STRSIZE - 1;
+ new_size &= -START_STRSIZE;
+ text = xrealloc(text, new_size);
+ text_asize = new_size;
+ }
+ memcpy(text + text_size, str, size);
+ text_size += size;
+ text[text_size] = 0;
+}
+
+static void alloc_string(const char *str, int size)
+{
+ text = xmalloc(size + 1);
+ memcpy(text, str, size);
+ text[size] = 0;
+}
+
+static void warn_ignored_character(char chr)
+{
+ fprintf(stderr,
+ "%s:%d:warning: ignoring unsupported character '%c'\n",
+ current_file->name, yylineno, chr);
+}
+%}
+
+n [A-Za-z0-9_-]
+
+%%
+ char open_quote = 0;
+
+#.* /* ignore comment */
+[ \t]* /* whitespaces */
+\\\n /* escaped new line */
+\n return T_EOL;
+"bool" return T_BOOL;
+"choice" return T_CHOICE;
+"comment" return T_COMMENT;
+"config" return T_CONFIG;
+"def_bool" return T_DEF_BOOL;
+"def_tristate" return T_DEF_TRISTATE;
+"default" return T_DEFAULT;
+"depends" return T_DEPENDS;
+"endchoice" return T_ENDCHOICE;
+"endif" return T_ENDIF;
+"endmenu" return T_ENDMENU;
+"help" return T_HELP;
+"hex" return T_HEX;
+"if" return T_IF;
+"imply" return T_IMPLY;
+"int" return T_INT;
+"mainmenu" return T_MAINMENU;
+"menu" return T_MENU;
+"menuconfig" return T_MENUCONFIG;
+"modules" return T_MODULES;
+"on" return T_ON;
+"optional" return T_OPTIONAL;
+"prompt" return T_PROMPT;
+"range" return T_RANGE;
+"select" return T_SELECT;
+"source" return T_SOURCE;
+"string" return T_STRING;
+"tristate" return T_TRISTATE;
+"visible" return T_VISIBLE;
+"||" return T_OR;
+"&&" return T_AND;
+"=" return T_EQUAL;
+"!=" return T_UNEQUAL;
+"<" return T_LESS;
+"<=" return T_LESS_EQUAL;
+">" return T_GREATER;
+">=" return T_GREATER_EQUAL;
+"!" return T_NOT;
+"(" return T_OPEN_PAREN;
+")" return T_CLOSE_PAREN;
+":=" return T_COLON_EQUAL;
+"+=" return T_PLUS_EQUAL;
+\"|\' {
+ open_quote = yytext[0];
+ new_string();
+ BEGIN(STRING);
+ }
+{n}+ {
+ alloc_string(yytext, yyleng);
+ yylval.string = text;
+ return T_WORD;
+ }
+({n}|$)+ {
+ /* this token includes at least one '$' */
+ yylval.string = expand_token(yytext, yyleng);
+ if (strlen(yylval.string))
+ return T_WORD;
+ free(yylval.string);
+ }
+. warn_ignored_character(*yytext);
+
+<ASSIGN_VAL>{
+ [^[:blank:]\n]+.* {
+ alloc_string(yytext, yyleng);
+ yylval.string = text;
+ return T_ASSIGN_VAL;
+ }
+ \n { BEGIN(INITIAL); return T_EOL; }
+ .
+}
+
+<STRING>{
+ "$".* append_expanded_string(yytext);
+ [^$'"\\\n]+ {
+ append_string(yytext, yyleng);
+ }
+ \\.? {
+ append_string(yytext + 1, yyleng - 1);
+ }
+ \'|\" {
+ if (open_quote == yytext[0]) {
+ BEGIN(INITIAL);
+ yylval.string = text;
+ return T_WORD_QUOTE;
+ } else
+ append_string(yytext, 1);
+ }
+ \n {
+ fprintf(stderr,
+ "%s:%d:warning: multi-line strings not supported\n",
+ zconf_curname(), zconf_lineno());
+ unput('\n');
+ BEGIN(INITIAL);
+ yylval.string = text;
+ return T_WORD_QUOTE;
+ }
+ <<EOF>> {
+ BEGIN(INITIAL);
+ yylval.string = text;
+ return T_WORD_QUOTE;
+ }
+}
+
+<HELP>{
+ [ \t]+ {
+ int ts, i;
+
+ ts = 0;
+ for (i = 0; i < yyleng; i++) {
+ if (yytext[i] == '\t')
+ ts = (ts & ~7) + 8;
+ else
+ ts++;
+ }
+ last_ts = ts;
+ if (first_ts) {
+ if (ts < first_ts) {
+ zconf_endhelp();
+ return T_HELPTEXT;
+ }
+ ts -= first_ts;
+ while (ts > 8) {
+ append_string(" ", 8);
+ ts -= 8;
+ }
+ append_string(" ", ts);
+ }
+ }
+ [ \t]*\n/[^ \t\n] {
+ zconf_endhelp();
+ return T_HELPTEXT;
+ }
+ [ \t]*\n {
+ append_string("\n", 1);
+ }
+ [^ \t\n].* {
+ while (yyleng) {
+ if ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\t'))
+ break;
+ yyleng--;
+ }
+ append_string(yytext, yyleng);
+ if (!first_ts)
+ first_ts = last_ts;
+ }
+ <<EOF>> {
+ zconf_endhelp();
+ return T_HELPTEXT;
+ }
+}
+
+<<EOF>> {
+ BEGIN(INITIAL);
+
+ if (prev_token != T_EOL && prev_token != T_HELPTEXT)
+ fprintf(stderr, "%s:%d:warning: no new line at end of file\n",
+ current_file->name, yylineno);
+
+ if (current_file) {
+ zconf_endfile();
+ return T_EOL;
+ }
+ fclose(yyin);
+ yyterminate();
+}
+
+%%
+
+/* second stage lexer */
+int yylex(void)
+{
+ int token;
+
+repeat:
+ token = yylex1();
+
+ if (prev_token == T_EOL || prev_token == T_HELPTEXT) {
+ if (token == T_EOL) {
+ /* Do not pass unneeded T_EOL to the parser. */
+ goto repeat;
+ } else {
+ /*
+ * For the parser, update file/lineno at the first token
+ * of each statement. Generally, \n is a statement
+ * terminator in Kconfig, but it is not always true
+ * because \n could be escaped by a backslash.
+ */
+ current_pos.file = current_file;
+ current_pos.lineno = yylineno;
+ }
+ }
+
+ if (prev_prev_token == T_EOL && prev_token == T_WORD &&
+ (token == T_EQUAL || token == T_COLON_EQUAL || token == T_PLUS_EQUAL))
+ BEGIN(ASSIGN_VAL);
+
+ prev_prev_token = prev_token;
+ prev_token = token;
+
+ return token;
+}
+
+static char *expand_token(const char *in, size_t n)
+{
+ char *out;
+ int c;
+ char c2;
+ const char *rest, *end;
+
+ new_string();
+ append_string(in, n);
+
+ /* get the whole line because we do not know the end of token. */
+ while ((c = input()) != EOF) {
+ if (c == '\n') {
+ unput(c);
+ break;
+ }
+ c2 = c;
+ append_string(&c2, 1);
+ }
+
+ rest = text;
+ out = expand_one_token(&rest);
+
+ /* push back unused characters to the input stream */
+ end = rest + strlen(rest);
+ while (end > rest)
+ unput(*--end);
+
+ free(text);
+
+ return out;
+}
+
+static void append_expanded_string(const char *str)
+{
+ const char *end;
+ char *res;
+
+ str++;
+
+ res = expand_dollar(&str);
+
+ /* push back unused characters to the input stream */
+ end = str + strlen(str);
+ while (end > str)
+ unput(*--end);
+
+ append_string(res, strlen(res));
+
+ free(res);
+}
+
+void zconf_starthelp(void)
+{
+ new_string();
+ last_ts = first_ts = 0;
+ BEGIN(HELP);
+}
+
+static void zconf_endhelp(void)
+{
+ yylval.string = text;
+ BEGIN(INITIAL);
+}
+
+
+/*
+ * Try to open specified file with following names:
+ * ./name
+ * $(srctree)/name
+ * The latter is used when srctree is separate from objtree
+ * when compiling the kernel.
+ * Return NULL if file is not found.
+ */
+FILE *zconf_fopen(const char *name)
+{
+ char *env, fullname[PATH_MAX+1];
+ FILE *f;
+
+ f = fopen(name, "r");
+ if (!f && name != NULL && name[0] != '/') {
+ env = getenv(SRCTREE);
+ if (env) {
+ snprintf(fullname, sizeof(fullname),
+ "%s/%s", env, name);
+ f = fopen(fullname, "r");
+ }
+ }
+ return f;
+}
+
+void zconf_initscan(const char *name)
+{
+ yyin = zconf_fopen(name);
+ if (!yyin) {
+ fprintf(stderr, "can't find file %s\n", name);
+ exit(1);
+ }
+
+ current_buf = xmalloc(sizeof(*current_buf));
+ memset(current_buf, 0, sizeof(*current_buf));
+
+ current_file = file_lookup(name);
+ yylineno = 1;
+}
+
+void zconf_nextfile(const char *name)
+{
+ struct file *iter;
+ struct file *file = file_lookup(name);
+ struct buffer *buf = xmalloc(sizeof(*buf));
+ memset(buf, 0, sizeof(*buf));
+
+ current_buf->state = YY_CURRENT_BUFFER;
+ yyin = zconf_fopen(file->name);
+ if (!yyin) {
+ fprintf(stderr, "%s:%d: can't open file \"%s\"\n",
+ zconf_curname(), zconf_lineno(), file->name);
+ exit(1);
+ }
+ yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));
+ buf->parent = current_buf;
+ current_buf = buf;
+
+ current_file->lineno = yylineno;
+ file->parent = current_file;
+
+ for (iter = current_file; iter; iter = iter->parent) {
+ if (!strcmp(iter->name, file->name)) {
+ fprintf(stderr,
+ "Recursive inclusion detected.\n"
+ "Inclusion path:\n"
+ " current file : %s\n", file->name);
+ iter = file;
+ do {
+ iter = iter->parent;
+ fprintf(stderr, " included from: %s:%d\n",
+ iter->name, iter->lineno - 1);
+ } while (strcmp(iter->name, file->name));
+ exit(1);
+ }
+ }
+
+ yylineno = 1;
+ current_file = file;
+}
+
+static void zconf_endfile(void)
+{
+ struct buffer *parent;
+
+ current_file = current_file->parent;
+ if (current_file)
+ yylineno = current_file->lineno;
+
+ parent = current_buf->parent;
+ if (parent) {
+ fclose(yyin);
+ yy_delete_buffer(YY_CURRENT_BUFFER);
+ yy_switch_to_buffer(parent->state);
+ }
+ free(current_buf);
+ current_buf = parent;
+}
+
+int zconf_lineno(void)
+{
+ return current_pos.lineno;
+}
+
+const char *zconf_curname(void)
+{
+ return current_pos.file ? current_pos.file->name : "<none>";
+}
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/mod/modpost.c
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/mod/modpost.c (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/mod/modpost.c (revision 151)
@@ -0,0 +1,2420 @@
+/* Postprocess module symbol versions
+ *
+ * Copyright 2003 Kai Germaschewski
+ * Copyright 2002-2004 Rusty Russell, IBM Corporation
+ * Copyright 2006-2008 Sam Ravnborg
+ * Based in part on module-init-tools/depmod.c,file2alias
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by reference.
+ *
+ * Usage: modpost vmlinux module1.o module2.o ...
+ */
+
+#define _GNU_SOURCE
+#include <elf.h>
+#include <fnmatch.h>
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+#include <linux/limits.h>
+#include <stdbool.h>
+#include <errno.h>
+#include "modpost.h"
+#include "../../include/linux/license.h"
+
+/* Are we using CONFIG_MODVERSIONS? */
+static bool modversions;
+/* Is CONFIG_MODULE_SRCVERSION_ALL set? */
+static bool all_versions;
+/* If we are modposting external module set to 1 */
+static bool external_module;
+/* Only warn about unresolved symbols */
+static bool warn_unresolved;
+
+static int sec_mismatch_count;
+static bool sec_mismatch_warn_only = true;
+/* ignore missing files */
+static bool ignore_missing_files;
+/* If set to 1, only warn (instead of error) about missing ns imports */
+static bool allow_missing_ns_imports;
+
+static bool error_occurred;
+
+/*
+ * Cut off the warnings when there are too many. This typically occurs when
+ * vmlinux is missing. ('make modules' without building vmlinux.)
+ */
+#define MAX_UNRESOLVED_REPORTS 10
+static unsigned int nr_unresolved;
+
+/* In kernel, this size is defined in linux/module.h;
+ * here we use Elf_Addr instead of long for covering cross-compile
+ */
+
+#define MODULE_NAME_LEN (64 - sizeof(Elf_Addr))
+
+void __attribute__((format(printf, 2, 3)))
+modpost_log(enum loglevel loglevel, const char *fmt, ...)
+{
+ va_list arglist;
+
+ switch (loglevel) {
+ case LOG_WARN:
+ fprintf(stderr, "WARNING: ");
+ break;
+ case LOG_ERROR:
+ fprintf(stderr, "ERROR: ");
+ break;
+ case LOG_FATAL:
+ fprintf(stderr, "FATAL: ");
+ break;
+ default: /* invalid loglevel, ignore */
+ break;
+ }
+
+ fprintf(stderr, "modpost: ");
+
+ va_start(arglist, fmt);
+ vfprintf(stderr, fmt, arglist);
+ va_end(arglist);
+
+ if (loglevel == LOG_FATAL)
+ exit(1);
+ if (loglevel == LOG_ERROR)
+ error_occurred = true;
+}
+
+static inline bool strends(const char *str, const char *postfix)
+{
+ if (strlen(str) < strlen(postfix))
+ return false;
+
+ return strcmp(str + strlen(str) - strlen(postfix), postfix) == 0;
+}
+
+void *do_nofail(void *ptr, const char *expr)
+{
+ if (!ptr)
+ fatal("Memory allocation failure: %s.\n", expr);
+
+ return ptr;
+}
+
+char *read_text_file(const char *filename)
+{
+ struct stat st;
+ size_t nbytes;
+ int fd;
+ char *buf;
+
+ fd = open(filename, O_RDONLY);
+ if (fd < 0) {
+ perror(filename);
+ exit(1);
+ }
+
+ if (fstat(fd, &st) < 0) {
+ perror(filename);
+ exit(1);
+ }
+
+ buf = NOFAIL(malloc(st.st_size + 1));
+
+ nbytes = st.st_size;
+
+ while (nbytes) {
+ ssize_t bytes_read;
+
+ bytes_read = read(fd, buf, nbytes);
+ if (bytes_read < 0) {
+ perror(filename);
+ exit(1);
+ }
+
+ nbytes -= bytes_read;
+ }
+ buf[st.st_size] = '\0';
+
+ close(fd);
+
+ return buf;
+}
+
+char *get_line(char **stringp)
+{
+ char *orig = *stringp, *next;
+
+ /* do not return the unwanted extra line at EOF */
+ if (!orig || *orig == '\0')
+ return NULL;
+
+ /* don't use strsep here, it is not available everywhere */
+ next = strchr(orig, '\n');
+ if (next)
+ *next++ = '\0';
+
+ *stringp = next;
+
+ return orig;
+}
+
+/* A list of all modules we processed */
+LIST_HEAD(modules);
+
+static struct module *find_module(const char *modname)
+{
+ struct module *mod;
+
+ list_for_each_entry(mod, &modules, list) {
+ if (strcmp(mod->name, modname) == 0)
+ return mod;
+ }
+ return NULL;
+}
+
+static struct module *new_module(const char *name, size_t namelen)
+{
+ struct module *mod;
+
+ mod = NOFAIL(malloc(sizeof(*mod) + namelen + 1));
+ memset(mod, 0, sizeof(*mod));
+
+ INIT_LIST_HEAD(&mod->exported_symbols);
+ INIT_LIST_HEAD(&mod->unresolved_symbols);
+ INIT_LIST_HEAD(&mod->missing_namespaces);
+ INIT_LIST_HEAD(&mod->imported_namespaces);
+
+ memcpy(mod->name, name, namelen);
+ mod->name[namelen] = '\0';
+ mod->is_vmlinux = (strcmp(mod->name, "vmlinux") == 0);
+
+ /*
+ * Set mod->is_gpl_compatible to true by default. If MODULE_LICENSE()
+ * is missing, do not check the use for EXPORT_SYMBOL_GPL() becasue
+ * modpost will exit wiht error anyway.
+ */
+ mod->is_gpl_compatible = true;
+
+ list_add_tail(&mod->list, &modules);
+
+ return mod;
+}
+
+/* A hash of all exported symbols,
+ * struct symbol is also used for lists of unresolved symbols */
+
+#define SYMBOL_HASH_SIZE 1024
+
+struct symbol {
+ struct symbol *next;
+ struct list_head list; /* link to module::exported_symbols or module::unresolved_symbols */
+ struct module *module;
+ char *namespace;
+ unsigned int crc;
+ bool crc_valid;
+ bool weak;
+ bool is_gpl_only; /* exported by EXPORT_SYMBOL_GPL */
+ char name[];
+};
+
+static struct symbol *symbolhash[SYMBOL_HASH_SIZE];
+
+/* This is based on the hash algorithm from gdbm, via tdb */
+static inline unsigned int tdb_hash(const char *name)
+{
+ unsigned value; /* Used to compute the hash value. */
+ unsigned i; /* Used to cycle through random values. */
+
+ /* Set the initial value from the key size. */
+ for (value = 0x238F13AF * strlen(name), i = 0; name[i]; i++)
+ value = (value + (((unsigned char *)name)[i] << (i*5 % 24)));
+
+ return (1103515243 * value + 12345);
+}
+
+/**
+ * Allocate a new symbols for use in the hash of exported symbols or
+ * the list of unresolved symbols per module
+ **/
+static struct symbol *alloc_symbol(const char *name)
+{
+ struct symbol *s = NOFAIL(malloc(sizeof(*s) + strlen(name) + 1));
+
+ memset(s, 0, sizeof(*s));
+ strcpy(s->name, name);
+
+ return s;
+}
+
+/* For the hash of exported symbols */
+static void hash_add_symbol(struct symbol *sym)
+{
+ unsigned int hash;
+
+ hash = tdb_hash(sym->name) % SYMBOL_HASH_SIZE;
+ sym->next = symbolhash[hash];
+ symbolhash[hash] = sym;
+}
+
+static void sym_add_unresolved(const char *name, struct module *mod, bool weak)
+{
+ struct symbol *sym;
+
+ sym = alloc_symbol(name);
+ sym->weak = weak;
+
+ list_add_tail(&sym->list, &mod->unresolved_symbols);
+}
+
+static struct symbol *sym_find_with_module(const char *name, struct module *mod)
+{
+ struct symbol *s;
+
+ /* For our purposes, .foo matches foo. PPC64 needs this. */
+ if (name[0] == '.')
+ name++;
+
+ for (s = symbolhash[tdb_hash(name) % SYMBOL_HASH_SIZE]; s; s = s->next) {
+ if (strcmp(s->name, name) == 0 && (!mod || s->module == mod))
+ return s;
+ }
+ return NULL;
+}
+
+static struct symbol *find_symbol(const char *name)
+{
+ return sym_find_with_module(name, NULL);
+}
+
+struct namespace_list {
+ struct list_head list;
+ char namespace[];
+};
+
+static bool contains_namespace(struct list_head *head, const char *namespace)
+{
+ struct namespace_list *list;
+
+ list_for_each_entry(list, head, list) {
+ if (!strcmp(list->namespace, namespace))
+ return true;
+ }
+
+ return false;
+}
+
+static void add_namespace(struct list_head *head, const char *namespace)
+{
+ struct namespace_list *ns_entry;
+
+ if (!contains_namespace(head, namespace)) {
+ ns_entry = NOFAIL(malloc(sizeof(*ns_entry) +
+ strlen(namespace) + 1));
+ strcpy(ns_entry->namespace, namespace);
+ list_add_tail(&ns_entry->list, head);
+ }
+}
+
+static void *sym_get_data_by_offset(const struct elf_info *info,
+ unsigned int secindex, unsigned long offset)
+{
+ Elf_Shdr *sechdr = &info->sechdrs[secindex];
+
+ return (void *)info->hdr + sechdr->sh_offset + offset;
+}
+
+void *sym_get_data(const struct elf_info *info, const Elf_Sym *sym)
+{
+ return sym_get_data_by_offset(info, get_secindex(info, sym),
+ sym->st_value);
+}
+
+static const char *sech_name(const struct elf_info *info, Elf_Shdr *sechdr)
+{
+ return sym_get_data_by_offset(info, info->secindex_strings,
+ sechdr->sh_name);
+}
+
+static const char *sec_name(const struct elf_info *info, unsigned int secindex)
+{
+ /*
+ * If sym->st_shndx is a special section index, there is no
+ * corresponding section header.
+ * Return "" if the index is out of range of info->sechdrs[] array.
+ */
+ if (secindex >= info->num_sections)
+ return "";
+
+ return sech_name(info, &info->sechdrs[secindex]);
+}
+
+#define strstarts(str, prefix) (strncmp(str, prefix, strlen(prefix)) == 0)
+
+static void sym_update_namespace(const char *symname, const char *namespace)
+{
+ struct symbol *s = find_symbol(symname);
+
+ /*
+ * That symbol should have been created earlier and thus this is
+ * actually an assertion.
+ */
+ if (!s) {
+ error("Could not update namespace(%s) for symbol %s\n",
+ namespace, symname);
+ return;
+ }
+
+ free(s->namespace);
+ s->namespace = namespace[0] ? NOFAIL(strdup(namespace)) : NULL;
+}
+
+static struct symbol *sym_add_exported(const char *name, struct module *mod,
+ bool gpl_only)
+{
+ struct symbol *s = find_symbol(name);
+
+ if (s && (!external_module || s->module->is_vmlinux || s->module == mod)) {
+ error("%s: '%s' exported twice. Previous export was in %s%s\n",
+ mod->name, name, s->module->name,
+ s->module->is_vmlinux ? "" : ".ko");
+ }
+
+ s = alloc_symbol(name);
+ s->module = mod;
+ s->is_gpl_only = gpl_only;
+ list_add_tail(&s->list, &mod->exported_symbols);
+ hash_add_symbol(s);
+
+ return s;
+}
+
+static void sym_set_crc(struct symbol *sym, unsigned int crc)
+{
+ sym->crc = crc;
+ sym->crc_valid = true;
+}
+
+static void *grab_file(const char *filename, size_t *size)
+{
+ struct stat st;
+ void *map = MAP_FAILED;
+ int fd;
+
+ fd = open(filename, O_RDONLY);
+ if (fd < 0)
+ return NULL;
+ if (fstat(fd, &st))
+ goto failed;
+
+ *size = st.st_size;
+ map = mmap(NULL, *size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
+
+failed:
+ close(fd);
+ if (map == MAP_FAILED)
+ return NULL;
+ return map;
+}
+
+static void release_file(void *file, size_t size)
+{
+ munmap(file, size);
+}
+
+static int parse_elf(struct elf_info *info, const char *filename)
+{
+ unsigned int i;
+ Elf_Ehdr *hdr;
+ Elf_Shdr *sechdrs;
+ Elf_Sym *sym;
+ const char *secstrings;
+ unsigned int symtab_idx = ~0U, symtab_shndx_idx = ~0U;
+
+ hdr = grab_file(filename, &info->size);
+ if (!hdr) {
+ if (ignore_missing_files) {
+ fprintf(stderr, "%s: %s (ignored)\n", filename,
+ strerror(errno));
+ return 0;
+ }
+ perror(filename);
+ exit(1);
+ }
+ info->hdr = hdr;
+ if (info->size < sizeof(*hdr)) {
+ /* file too small, assume this is an empty .o file */
+ return 0;
+ }
+ /* Is this a valid ELF file? */
+ if ((hdr->e_ident[EI_MAG0] != ELFMAG0) ||
+ (hdr->e_ident[EI_MAG1] != ELFMAG1) ||
+ (hdr->e_ident[EI_MAG2] != ELFMAG2) ||
+ (hdr->e_ident[EI_MAG3] != ELFMAG3)) {
+ /* Not an ELF file - silently ignore it */
+ return 0;
+ }
+ /* Fix endianness in ELF header */
+ hdr->e_type = TO_NATIVE(hdr->e_type);
+ hdr->e_machine = TO_NATIVE(hdr->e_machine);
+ hdr->e_version = TO_NATIVE(hdr->e_version);
+ hdr->e_entry = TO_NATIVE(hdr->e_entry);
+ hdr->e_phoff = TO_NATIVE(hdr->e_phoff);
+ hdr->e_shoff = TO_NATIVE(hdr->e_shoff);
+ hdr->e_flags = TO_NATIVE(hdr->e_flags);
+ hdr->e_ehsize = TO_NATIVE(hdr->e_ehsize);
+ hdr->e_phentsize = TO_NATIVE(hdr->e_phentsize);
+ hdr->e_phnum = TO_NATIVE(hdr->e_phnum);
+ hdr->e_shentsize = TO_NATIVE(hdr->e_shentsize);
+ hdr->e_shnum = TO_NATIVE(hdr->e_shnum);
+ hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx);
+ sechdrs = (void *)hdr + hdr->e_shoff;
+ info->sechdrs = sechdrs;
+
+ /* modpost only works for relocatable objects */
+ if (hdr->e_type != ET_REL)
+ fatal("%s: not relocatable object.", filename);
+
+ /* Check if file offset is correct */
+ if (hdr->e_shoff > info->size) {
+ fatal("section header offset=%lu in file '%s' is bigger than filesize=%zu\n",
+ (unsigned long)hdr->e_shoff, filename, info->size);
+ return 0;
+ }
+
+ if (hdr->e_shnum == SHN_UNDEF) {
+ /*
+ * There are more than 64k sections,
+ * read count from .sh_size.
+ */
+ info->num_sections = TO_NATIVE(sechdrs[0].sh_size);
+ }
+ else {
+ info->num_sections = hdr->e_shnum;
+ }
+ if (hdr->e_shstrndx == SHN_XINDEX) {
+ info->secindex_strings = TO_NATIVE(sechdrs[0].sh_link);
+ }
+ else {
+ info->secindex_strings = hdr->e_shstrndx;
+ }
+
+ /* Fix endianness in section headers */
+ for (i = 0; i < info->num_sections; i++) {
+ sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name);
+ sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type);
+ sechdrs[i].sh_flags = TO_NATIVE(sechdrs[i].sh_flags);
+ sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr);
+ sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset);
+ sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size);
+ sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link);
+ sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info);
+ sechdrs[i].sh_addralign = TO_NATIVE(sechdrs[i].sh_addralign);
+ sechdrs[i].sh_entsize = TO_NATIVE(sechdrs[i].sh_entsize);
+ }
+ /* Find symbol table. */
+ secstrings = (void *)hdr + sechdrs[info->secindex_strings].sh_offset;
+ for (i = 1; i < info->num_sections; i++) {
+ const char *secname;
+ int nobits = sechdrs[i].sh_type == SHT_NOBITS;
+
+ if (!nobits && sechdrs[i].sh_offset > info->size) {
+ fatal("%s is truncated. sechdrs[i].sh_offset=%lu > sizeof(*hrd)=%zu\n",
+ filename, (unsigned long)sechdrs[i].sh_offset,
+ sizeof(*hdr));
+ return 0;
+ }
+ secname = secstrings + sechdrs[i].sh_name;
+ if (strcmp(secname, ".modinfo") == 0) {
+ if (nobits)
+ fatal("%s has NOBITS .modinfo\n", filename);
+ info->modinfo = (void *)hdr + sechdrs[i].sh_offset;
+ info->modinfo_len = sechdrs[i].sh_size;
+ }
+
+ if (sechdrs[i].sh_type == SHT_SYMTAB) {
+ unsigned int sh_link_idx;
+ symtab_idx = i;
+ info->symtab_start = (void *)hdr +
+ sechdrs[i].sh_offset;
+ info->symtab_stop = (void *)hdr +
+ sechdrs[i].sh_offset + sechdrs[i].sh_size;
+ sh_link_idx = sechdrs[i].sh_link;
+ info->strtab = (void *)hdr +
+ sechdrs[sh_link_idx].sh_offset;
+ }
+
+ /* 32bit section no. table? ("more than 64k sections") */
+ if (sechdrs[i].sh_type == SHT_SYMTAB_SHNDX) {
+ symtab_shndx_idx = i;
+ info->symtab_shndx_start = (void *)hdr +
+ sechdrs[i].sh_offset;
+ info->symtab_shndx_stop = (void *)hdr +
+ sechdrs[i].sh_offset + sechdrs[i].sh_size;
+ }
+ }
+ if (!info->symtab_start)
+ fatal("%s has no symtab?\n", filename);
+
+ /* Fix endianness in symbols */
+ for (sym = info->symtab_start; sym < info->symtab_stop; sym++) {
+ sym->st_shndx = TO_NATIVE(sym->st_shndx);
+ sym->st_name = TO_NATIVE(sym->st_name);
+ sym->st_value = TO_NATIVE(sym->st_value);
+ sym->st_size = TO_NATIVE(sym->st_size);
+ }
+
+ if (symtab_shndx_idx != ~0U) {
+ Elf32_Word *p;
+ if (symtab_idx != sechdrs[symtab_shndx_idx].sh_link)
+ fatal("%s: SYMTAB_SHNDX has bad sh_link: %u!=%u\n",
+ filename, sechdrs[symtab_shndx_idx].sh_link,
+ symtab_idx);
+ /* Fix endianness */
+ for (p = info->symtab_shndx_start; p < info->symtab_shndx_stop;
+ p++)
+ *p = TO_NATIVE(*p);
+ }
+
+ return 1;
+}
+
+static void parse_elf_finish(struct elf_info *info)
+{
+ release_file(info->hdr, info->size);
+}
+
+static int ignore_undef_symbol(struct elf_info *info, const char *symname)
+{
+ /* ignore __this_module, it will be resolved shortly */
+ if (strcmp(symname, "__this_module") == 0)
+ return 1;
+ /* ignore global offset table */
+ if (strcmp(symname, "_GLOBAL_OFFSET_TABLE_") == 0)
+ return 1;
+ if (info->hdr->e_machine == EM_PPC)
+ /* Special register function linked on all modules during final link of .ko */
+ if (strstarts(symname, "_restgpr_") ||
+ strstarts(symname, "_savegpr_") ||
+ strstarts(symname, "_rest32gpr_") ||
+ strstarts(symname, "_save32gpr_") ||
+ strstarts(symname, "_restvr_") ||
+ strstarts(symname, "_savevr_"))
+ return 1;
+ if (info->hdr->e_machine == EM_PPC64)
+ /* Special register function linked on all modules during final link of .ko */
+ if (strstarts(symname, "_restgpr0_") ||
+ strstarts(symname, "_savegpr0_") ||
+ strstarts(symname, "_restvr_") ||
+ strstarts(symname, "_savevr_") ||
+ strcmp(symname, ".TOC.") == 0)
+ return 1;
+
+ if (info->hdr->e_machine == EM_S390)
+ /* Expoline thunks are linked on all kernel modules during final link of .ko */
+ if (strstarts(symname, "__s390_indirect_jump_r"))
+ return 1;
+ /* Do not ignore this symbol */
+ return 0;
+}
+
+static void handle_symbol(struct module *mod, struct elf_info *info,
+ const Elf_Sym *sym, const char *symname)
+{
+ switch (sym->st_shndx) {
+ case SHN_COMMON:
+ if (strstarts(symname, "__gnu_lto_")) {
+ /* Should warn here, but modpost runs before the linker */
+ } else
+ warn("\"%s\" [%s] is COMMON symbol\n", symname, mod->name);
+ break;
+ case SHN_UNDEF:
+ /* undefined symbol */
+ if (ELF_ST_BIND(sym->st_info) != STB_GLOBAL &&
+ ELF_ST_BIND(sym->st_info) != STB_WEAK)
+ break;
+ if (ignore_undef_symbol(info, symname))
+ break;
+ if (info->hdr->e_machine == EM_SPARC ||
+ info->hdr->e_machine == EM_SPARCV9) {
+ /* Ignore register directives. */
+ if (ELF_ST_TYPE(sym->st_info) == STT_SPARC_REGISTER)
+ break;
+ if (symname[0] == '.') {
+ char *munged = NOFAIL(strdup(symname));
+ munged[0] = '_';
+ munged[1] = toupper(munged[1]);
+ symname = munged;
+ }
+ }
+
+ sym_add_unresolved(symname, mod,
+ ELF_ST_BIND(sym->st_info) == STB_WEAK);
+ break;
+ default:
+ /* All exported symbols */
+ if (strstarts(symname, "__ksymtab_")) {
+ const char *name, *secname;
+
+ name = symname + strlen("__ksymtab_");
+ secname = sec_name(info, get_secindex(info, sym));
+
+ if (strstarts(secname, "___ksymtab_gpl+"))
+ sym_add_exported(name, mod, true);
+ else if (strstarts(secname, "___ksymtab+"))
+ sym_add_exported(name, mod, false);
+ }
+ if (strcmp(symname, "init_module") == 0)
+ mod->has_init = true;
+ if (strcmp(symname, "cleanup_module") == 0)
+ mod->has_cleanup = true;
+ break;
+ }
+}
+
+/**
+ * Parse tag=value strings from .modinfo section
+ **/
+static char *next_string(char *string, unsigned long *secsize)
+{
+ /* Skip non-zero chars */
+ while (string[0]) {
+ string++;
+ if ((*secsize)-- <= 1)
+ return NULL;
+ }
+
+ /* Skip any zero padding. */
+ while (!string[0]) {
+ string++;
+ if ((*secsize)-- <= 1)
+ return NULL;
+ }
+ return string;
+}
+
+static char *get_next_modinfo(struct elf_info *info, const char *tag,
+ char *prev)
+{
+ char *p;
+ unsigned int taglen = strlen(tag);
+ char *modinfo = info->modinfo;
+ unsigned long size = info->modinfo_len;
+
+ if (prev) {
+ size -= prev - modinfo;
+ modinfo = next_string(prev, &size);
+ }
+
+ for (p = modinfo; p; p = next_string(p, &size)) {
+ if (strncmp(p, tag, taglen) == 0 && p[taglen] == '=')
+ return p + taglen + 1;
+ }
+ return NULL;
+}
+
+static char *get_modinfo(struct elf_info *info, const char *tag)
+
+{
+ return get_next_modinfo(info, tag, NULL);
+}
+
+static const char *sym_name(struct elf_info *elf, Elf_Sym *sym)
+{
+ if (sym)
+ return elf->strtab + sym->st_name;
+ else
+ return "(unknown)";
+}
+
+/*
+ * Check whether the 'string' argument matches one of the 'patterns',
+ * an array of shell wildcard patterns (glob).
+ *
+ * Return true is there is a match.
+ */
+static bool match(const char *string, const char *const patterns[])
+{
+ const char *pattern;
+
+ while ((pattern = *patterns++)) {
+ if (!fnmatch(pattern, string, 0))
+ return true;
+ }
+
+ return false;
+}
+
+/* useful to pass patterns to match() directly */
+#define PATTERNS(...) \
+ ({ \
+ static const char *const patterns[] = {__VA_ARGS__, NULL}; \
+ patterns; \
+ })
+
+/* sections that we do not want to do full section mismatch check on */
+static const char *const section_white_list[] =
+{
+ ".comment*",
+ ".debug*",
+ ".zdebug*", /* Compressed debug sections. */
+ ".GCC.command.line", /* record-gcc-switches */
+ ".mdebug*", /* alpha, score, mips etc. */
+ ".pdr", /* alpha, score, mips etc. */
+ ".stab*",
+ ".note*",
+ ".got*",
+ ".toc*",
+ ".xt.prop", /* xtensa */
+ ".xt.lit", /* xtensa */
+ ".arcextmap*", /* arc */
+ ".gnu.linkonce.arcext*", /* arc : modules */
+ ".cmem*", /* EZchip */
+ ".fmt_slot*", /* EZchip */
+ ".gnu.lto*",
+ ".discard.*",
+ NULL
+};
+
+/*
+ * This is used to find sections missing the SHF_ALLOC flag.
+ * The cause of this is often a section specified in assembler
+ * without "ax" / "aw".
+ */
+static void check_section(const char *modname, struct elf_info *elf,
+ Elf_Shdr *sechdr)
+{
+ const char *sec = sech_name(elf, sechdr);
+
+ if (sechdr->sh_type == SHT_PROGBITS &&
+ !(sechdr->sh_flags & SHF_ALLOC) &&
+ !match(sec, section_white_list)) {
+ warn("%s (%s): unexpected non-allocatable section.\n"
+ "Did you forget to use \"ax\"/\"aw\" in a .S file?\n"
+ "Note that for example <linux/init.h> contains\n"
+ "section definitions for use in .S files.\n\n",
+ modname, sec);
+ }
+}
+
+
+
+#define ALL_INIT_DATA_SECTIONS \
+ ".init.setup", ".init.rodata", ".meminit.rodata", \
+ ".init.data", ".meminit.data"
+#define ALL_EXIT_DATA_SECTIONS \
+ ".exit.data", ".memexit.data"
+
+#define ALL_INIT_TEXT_SECTIONS \
+ ".init.text", ".meminit.text"
+#define ALL_EXIT_TEXT_SECTIONS \
+ ".exit.text", ".memexit.text"
+
+#define ALL_PCI_INIT_SECTIONS \
+ ".pci_fixup_early", ".pci_fixup_header", ".pci_fixup_final", \
+ ".pci_fixup_enable", ".pci_fixup_resume", \
+ ".pci_fixup_resume_early", ".pci_fixup_suspend"
+
+#define ALL_XXXINIT_SECTIONS MEM_INIT_SECTIONS
+#define ALL_XXXEXIT_SECTIONS MEM_EXIT_SECTIONS
+
+#define ALL_INIT_SECTIONS INIT_SECTIONS, ALL_XXXINIT_SECTIONS
+#define ALL_EXIT_SECTIONS EXIT_SECTIONS, ALL_XXXEXIT_SECTIONS
+
+#define DATA_SECTIONS ".data", ".data.rel"
+#define TEXT_SECTIONS ".text", ".text.*", ".sched.text", \
+ ".kprobes.text", ".cpuidle.text", ".noinstr.text"
+#define OTHER_TEXT_SECTIONS ".ref.text", ".head.text", ".spinlock.text", \
+ ".fixup", ".entry.text", ".exception.text", \
+ ".coldtext", ".softirqentry.text"
+
+#define INIT_SECTIONS ".init.*"
+#define MEM_INIT_SECTIONS ".meminit.*"
+
+#define EXIT_SECTIONS ".exit.*"
+#define MEM_EXIT_SECTIONS ".memexit.*"
+
+#define ALL_TEXT_SECTIONS ALL_INIT_TEXT_SECTIONS, ALL_EXIT_TEXT_SECTIONS, \
+ TEXT_SECTIONS, OTHER_TEXT_SECTIONS
+
+/* init data sections */
+static const char *const init_data_sections[] =
+ { ALL_INIT_DATA_SECTIONS, NULL };
+
+/* all init sections */
+static const char *const init_sections[] = { ALL_INIT_SECTIONS, NULL };
+
+/* all text sections */
+static const char *const text_sections[] = { ALL_TEXT_SECTIONS, NULL };
+
+/* data section */
+static const char *const data_sections[] = { DATA_SECTIONS, NULL };
+
+static const char *const head_sections[] = { ".head.text*", NULL };
+static const char *const linker_symbols[] =
+ { "__init_begin", "_sinittext", "_einittext", NULL };
+static const char *const optim_symbols[] = { "*.constprop.*", NULL };
+
+enum mismatch {
+ TEXT_TO_ANY_INIT,
+ DATA_TO_ANY_INIT,
+ TEXT_TO_ANY_EXIT,
+ DATA_TO_ANY_EXIT,
+ XXXINIT_TO_SOME_INIT,
+ XXXEXIT_TO_SOME_EXIT,
+ ANY_INIT_TO_ANY_EXIT,
+ ANY_EXIT_TO_ANY_INIT,
+ EXPORT_TO_INIT_EXIT,
+ EXTABLE_TO_NON_TEXT,
+};
+
+/**
+ * Describe how to match sections on different criteria:
+ *
+ * @fromsec: Array of sections to be matched.
+ *
+ * @bad_tosec: Relocations applied to a section in @fromsec to a section in
+ * this array is forbidden (black-list). Can be empty.
+ *
+ * @good_tosec: Relocations applied to a section in @fromsec must be
+ * targeting sections in this array (white-list). Can be empty.
+ *
+ * @mismatch: Type of mismatch.
+ *
+ * @handler: Specific handler to call when a match is found. If NULL,
+ * default_mismatch_handler() will be called.
+ *
+ */
+struct sectioncheck {
+ const char *fromsec[20];
+ const char *bad_tosec[20];
+ const char *good_tosec[20];
+ enum mismatch mismatch;
+ void (*handler)(const char *modname, struct elf_info *elf,
+ const struct sectioncheck* const mismatch,
+ Elf_Rela *r, Elf_Sym *sym, const char *fromsec);
+
+};
+
+static void extable_mismatch_handler(const char *modname, struct elf_info *elf,
+ const struct sectioncheck* const mismatch,
+ Elf_Rela *r, Elf_Sym *sym,
+ const char *fromsec);
+
+static const struct sectioncheck sectioncheck[] = {
+/* Do not reference init/exit code/data from
+ * normal code and data
+ */
+{
+ .fromsec = { TEXT_SECTIONS, NULL },
+ .bad_tosec = { ALL_INIT_SECTIONS, NULL },
+ .mismatch = TEXT_TO_ANY_INIT,
+},
+{
+ .fromsec = { DATA_SECTIONS, NULL },
+ .bad_tosec = { ALL_XXXINIT_SECTIONS, NULL },
+ .mismatch = DATA_TO_ANY_INIT,
+},
+{
+ .fromsec = { DATA_SECTIONS, NULL },
+ .bad_tosec = { INIT_SECTIONS, NULL },
+ .mismatch = DATA_TO_ANY_INIT,
+},
+{
+ .fromsec = { TEXT_SECTIONS, NULL },
+ .bad_tosec = { ALL_EXIT_SECTIONS, NULL },
+ .mismatch = TEXT_TO_ANY_EXIT,
+},
+{
+ .fromsec = { DATA_SECTIONS, NULL },
+ .bad_tosec = { ALL_EXIT_SECTIONS, NULL },
+ .mismatch = DATA_TO_ANY_EXIT,
+},
+/* Do not reference init code/data from meminit code/data */
+{
+ .fromsec = { ALL_XXXINIT_SECTIONS, NULL },
+ .bad_tosec = { INIT_SECTIONS, NULL },
+ .mismatch = XXXINIT_TO_SOME_INIT,
+},
+/* Do not reference exit code/data from memexit code/data */
+{
+ .fromsec = { ALL_XXXEXIT_SECTIONS, NULL },
+ .bad_tosec = { EXIT_SECTIONS, NULL },
+ .mismatch = XXXEXIT_TO_SOME_EXIT,
+},
+/* Do not use exit code/data from init code */
+{
+ .fromsec = { ALL_INIT_SECTIONS, NULL },
+ .bad_tosec = { ALL_EXIT_SECTIONS, NULL },
+ .mismatch = ANY_INIT_TO_ANY_EXIT,
+},
+/* Do not use init code/data from exit code */
+{
+ .fromsec = { ALL_EXIT_SECTIONS, NULL },
+ .bad_tosec = { ALL_INIT_SECTIONS, NULL },
+ .mismatch = ANY_EXIT_TO_ANY_INIT,
+},
+{
+ .fromsec = { ALL_PCI_INIT_SECTIONS, NULL },
+ .bad_tosec = { INIT_SECTIONS, NULL },
+ .mismatch = ANY_INIT_TO_ANY_EXIT,
+},
+/* Do not export init/exit functions or data */
+{
+ .fromsec = { "___ksymtab*", NULL },
+ .bad_tosec = { INIT_SECTIONS, EXIT_SECTIONS, NULL },
+ .mismatch = EXPORT_TO_INIT_EXIT,
+},
+{
+ .fromsec = { "__ex_table", NULL },
+ /* If you're adding any new black-listed sections in here, consider
+ * adding a special 'printer' for them in scripts/check_extable.
+ */
+ .bad_tosec = { ".altinstr_replacement", NULL },
+ .good_tosec = {ALL_TEXT_SECTIONS , NULL},
+ .mismatch = EXTABLE_TO_NON_TEXT,
+ .handler = extable_mismatch_handler,
+}
+};
+
+static const struct sectioncheck *section_mismatch(
+ const char *fromsec, const char *tosec)
+{
+ int i;
+
+ /*
+ * The target section could be the SHT_NUL section when we're
+ * handling relocations to un-resolved symbols, trying to match it
+ * doesn't make much sense and causes build failures on parisc
+ * architectures.
+ */
+ if (*tosec == '\0')
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(sectioncheck); i++) {
+ const struct sectioncheck *check = §ioncheck[i];
+
+ if (match(fromsec, check->fromsec)) {
+ if (check->bad_tosec[0] && match(tosec, check->bad_tosec))
+ return check;
+ if (check->good_tosec[0] && !match(tosec, check->good_tosec))
+ return check;
+ }
+ }
+ return NULL;
+}
+
+/**
+ * Whitelist to allow certain references to pass with no warning.
+ *
+ * Pattern 1:
+ * If a module parameter is declared __initdata and permissions=0
+ * then this is legal despite the warning generated.
+ * We cannot see value of permissions here, so just ignore
+ * this pattern.
+ * The pattern is identified by:
+ * tosec = .init.data
+ * fromsec = .data*
+ * atsym =__param*
+ *
+ * Pattern 1a:
+ * module_param_call() ops can refer to __init set function if permissions=0
+ * The pattern is identified by:
+ * tosec = .init.text
+ * fromsec = .data*
+ * atsym = __param_ops_*
+ *
+ * Pattern 3:
+ * Whitelist all references from .head.text to any init section
+ *
+ * Pattern 4:
+ * Some symbols belong to init section but still it is ok to reference
+ * these from non-init sections as these symbols don't have any memory
+ * allocated for them and symbol address and value are same. So even
+ * if init section is freed, its ok to reference those symbols.
+ * For ex. symbols marking the init section boundaries.
+ * This pattern is identified by
+ * refsymname = __init_begin, _sinittext, _einittext
+ *
+ * Pattern 5:
+ * GCC may optimize static inlines when fed constant arg(s) resulting
+ * in functions like cpumask_empty() -- generating an associated symbol
+ * cpumask_empty.constprop.3 that appears in the audit. If the const that
+ * is passed in comes from __init, like say nmi_ipi_mask, we get a
+ * meaningless section warning. May need to add isra symbols too...
+ * This pattern is identified by
+ * tosec = init section
+ * fromsec = text section
+ * refsymname = *.constprop.*
+ *
+ * Pattern 6:
+ * Hide section mismatch warnings for ELF local symbols. The goal
+ * is to eliminate false positive modpost warnings caused by
+ * compiler-generated ELF local symbol names such as ".LANCHOR1".
+ * Autogenerated symbol names bypass modpost's "Pattern 2"
+ * whitelisting, which relies on pattern-matching against symbol
+ * names to work. (One situation where gcc can autogenerate ELF
+ * local symbols is when "-fsection-anchors" is used.)
+ **/
+static int secref_whitelist(const struct sectioncheck *mismatch,
+ const char *fromsec, const char *fromsym,
+ const char *tosec, const char *tosym)
+{
+ /* Check for pattern 1 */
+ if (match(tosec, init_data_sections) &&
+ match(fromsec, data_sections) &&
+ strstarts(fromsym, "__param"))
+ return 0;
+
+ /* Check for pattern 1a */
+ if (strcmp(tosec, ".init.text") == 0 &&
+ match(fromsec, data_sections) &&
+ strstarts(fromsym, "__param_ops_"))
+ return 0;
+
+ /* symbols in data sections that may refer to any init/exit sections */
+ if (match(fromsec, PATTERNS(DATA_SECTIONS)) &&
+ match(tosec, PATTERNS(ALL_INIT_SECTIONS, ALL_EXIT_SECTIONS)) &&
+ match(fromsym, PATTERNS("*_template", // scsi uses *_template a lot
+ "*_timer", // arm uses ops structures named _timer a lot
+ "*_sht", // scsi also used *_sht to some extent
+ "*_ops",
+ "*_probe",
+ "*_probe_one",
+ "*_console")))
+ return 0;
+
+ /* symbols in data sections that may refer to meminit/exit sections */
+ if (match(fromsec, PATTERNS(DATA_SECTIONS)) &&
+ match(tosec, PATTERNS(ALL_XXXINIT_SECTIONS, ALL_EXIT_SECTIONS)) &&
+ match(fromsym, PATTERNS("*driver")))
+ return 0;
+
+ /* Check for pattern 3 */
+ if (match(fromsec, head_sections) &&
+ match(tosec, init_sections))
+ return 0;
+
+ /* Check for pattern 4 */
+ if (match(tosym, linker_symbols))
+ return 0;
+
+ /* Check for pattern 5 */
+ if (match(fromsec, text_sections) &&
+ match(tosec, init_sections) &&
+ match(fromsym, optim_symbols))
+ return 0;
+
+ /* Check for pattern 6 */
+ if (strstarts(fromsym, ".L"))
+ return 0;
+
+ return 1;
+}
+
+static inline int is_arm_mapping_symbol(const char *str)
+{
+ return str[0] == '$' &&
+ (str[1] == 'a' || str[1] == 'd' || str[1] == 't' || str[1] == 'x')
+ && (str[2] == '\0' || str[2] == '.');
+}
+
+/*
+ * If there's no name there, ignore it; likewise, ignore it if it's
+ * one of the magic symbols emitted used by current ARM tools.
+ *
+ * Otherwise if find_symbols_between() returns those symbols, they'll
+ * fail the whitelist tests and cause lots of false alarms ... fixable
+ * only by merging __exit and __init sections into __text, bloating
+ * the kernel (which is especially evil on embedded platforms).
+ */
+static inline int is_valid_name(struct elf_info *elf, Elf_Sym *sym)
+{
+ const char *name = elf->strtab + sym->st_name;
+
+ if (!name || !strlen(name))
+ return 0;
+ return !is_arm_mapping_symbol(name);
+}
+
+/**
+ * Find symbol based on relocation record info.
+ * In some cases the symbol supplied is a valid symbol so
+ * return refsym. If st_name != 0 we assume this is a valid symbol.
+ * In other cases the symbol needs to be looked up in the symbol table
+ * based on section and address.
+ * **/
+static Elf_Sym *find_elf_symbol(struct elf_info *elf, Elf64_Sword addr,
+ Elf_Sym *relsym)
+{
+ Elf_Sym *sym;
+ Elf_Sym *near = NULL;
+ Elf64_Sword distance = 20;
+ Elf64_Sword d;
+ unsigned int relsym_secindex;
+
+ if (relsym->st_name != 0)
+ return relsym;
+
+ relsym_secindex = get_secindex(elf, relsym);
+ for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) {
+ if (get_secindex(elf, sym) != relsym_secindex)
+ continue;
+ if (ELF_ST_TYPE(sym->st_info) == STT_SECTION)
+ continue;
+ if (!is_valid_name(elf, sym))
+ continue;
+ if (sym->st_value == addr)
+ return sym;
+ /* Find a symbol nearby - addr are maybe negative */
+ d = sym->st_value - addr;
+ if (d < 0)
+ d = addr - sym->st_value;
+ if (d < distance) {
+ distance = d;
+ near = sym;
+ }
+ }
+ /* We need a close match */
+ if (distance < 20)
+ return near;
+ else
+ return NULL;
+}
+
+/*
+ * Find symbols before or equal addr and after addr - in the section sec.
+ * If we find two symbols with equal offset prefer one with a valid name.
+ * The ELF format may have a better way to detect what type of symbol
+ * it is, but this works for now.
+ **/
+static Elf_Sym *find_elf_symbol2(struct elf_info *elf, Elf_Addr addr,
+ const char *sec)
+{
+ Elf_Sym *sym;
+ Elf_Sym *near = NULL;
+ Elf_Addr distance = ~0;
+
+ for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) {
+ const char *symsec;
+
+ if (is_shndx_special(sym->st_shndx))
+ continue;
+ symsec = sec_name(elf, get_secindex(elf, sym));
+ if (strcmp(symsec, sec) != 0)
+ continue;
+ if (!is_valid_name(elf, sym))
+ continue;
+ if (sym->st_value <= addr && addr - sym->st_value <= distance) {
+ distance = addr - sym->st_value;
+ near = sym;
+ }
+ }
+ return near;
+}
+
+static int is_function(Elf_Sym *sym)
+{
+ if (sym)
+ return ELF_ST_TYPE(sym->st_info) == STT_FUNC;
+ else
+ return -1;
+}
+
+static inline void get_pretty_name(int is_func, const char** name, const char** name_p)
+{
+ switch (is_func) {
+ case 0: *name = "variable"; *name_p = ""; break;
+ case 1: *name = "function"; *name_p = "()"; break;
+ default: *name = "(unknown reference)"; *name_p = ""; break;
+ }
+}
+
+/*
+ * Print a warning about a section mismatch.
+ * Try to find symbols near it so user can find it.
+ * Check whitelist before warning - it may be a false positive.
+ */
+static void report_sec_mismatch(const char *modname,
+ const struct sectioncheck *mismatch,
+ const char *fromsec,
+ const char *fromsym,
+ const char *tosec, const char *tosym)
+{
+ sec_mismatch_count++;
+
+ switch (mismatch->mismatch) {
+ case TEXT_TO_ANY_INIT:
+ case DATA_TO_ANY_INIT:
+ case TEXT_TO_ANY_EXIT:
+ case DATA_TO_ANY_EXIT:
+ case XXXINIT_TO_SOME_INIT:
+ case XXXEXIT_TO_SOME_EXIT:
+ case ANY_INIT_TO_ANY_EXIT:
+ case ANY_EXIT_TO_ANY_INIT:
+ warn("%s: section mismatch in reference: %s (section: %s) -> %s (section: %s)\n",
+ modname, fromsym, fromsec, tosym, tosec);
+ break;
+ case EXPORT_TO_INIT_EXIT:
+ warn("%s: EXPORT_SYMBOL used for init/exit symbol: %s (section: %s)\n",
+ modname, tosym, tosec);
+ break;
+ case EXTABLE_TO_NON_TEXT:
+ fatal("There's a special handler for this mismatch type, we should never get here.\n");
+ break;
+ }
+}
+
+static void default_mismatch_handler(const char *modname, struct elf_info *elf,
+ const struct sectioncheck* const mismatch,
+ Elf_Rela *r, Elf_Sym *sym, const char *fromsec)
+{
+ const char *tosec;
+ Elf_Sym *to;
+ Elf_Sym *from;
+ const char *tosym;
+ const char *fromsym;
+
+ from = find_elf_symbol2(elf, r->r_offset, fromsec);
+ fromsym = sym_name(elf, from);
+
+ tosec = sec_name(elf, get_secindex(elf, sym));
+ to = find_elf_symbol(elf, r->r_addend, sym);
+ tosym = sym_name(elf, to);
+
+ /* check whitelist - we may ignore it */
+ if (secref_whitelist(mismatch,
+ fromsec, fromsym, tosec, tosym)) {
+ report_sec_mismatch(modname, mismatch,
+ fromsec, fromsym, tosec, tosym);
+ }
+}
+
+static int is_executable_section(struct elf_info* elf, unsigned int section_index)
+{
+ if (section_index > elf->num_sections)
+ fatal("section_index is outside elf->num_sections!\n");
+
+ return ((elf->sechdrs[section_index].sh_flags & SHF_EXECINSTR) == SHF_EXECINSTR);
+}
+
+/*
+ * We rely on a gross hack in section_rel[a]() calling find_extable_entry_size()
+ * to know the sizeof(struct exception_table_entry) for the target architecture.
+ */
+static unsigned int extable_entry_size = 0;
+static void find_extable_entry_size(const char* const sec, const Elf_Rela* r)
+{
+ /*
+ * If we're currently checking the second relocation within __ex_table,
+ * that relocation offset tells us the offsetof(struct
+ * exception_table_entry, fixup) which is equal to sizeof(struct
+ * exception_table_entry) divided by two. We use that to our advantage
+ * since there's no portable way to get that size as every architecture
+ * seems to go with different sized types. Not pretty but better than
+ * hard-coding the size for every architecture..
+ */
+ if (!extable_entry_size)
+ extable_entry_size = r->r_offset * 2;
+}
+
+static inline bool is_extable_fault_address(Elf_Rela *r)
+{
+ /*
+ * extable_entry_size is only discovered after we've handled the
+ * _second_ relocation in __ex_table, so only abort when we're not
+ * handling the first reloc and extable_entry_size is zero.
+ */
+ if (r->r_offset && extable_entry_size == 0)
+ fatal("extable_entry size hasn't been discovered!\n");
+
+ return ((r->r_offset == 0) ||
+ (r->r_offset % extable_entry_size == 0));
+}
+
+#define is_second_extable_reloc(Start, Cur, Sec) \
+ (((Cur) == (Start) + 1) && (strcmp("__ex_table", (Sec)) == 0))
+
+static void report_extable_warnings(const char* modname, struct elf_info* elf,
+ const struct sectioncheck* const mismatch,
+ Elf_Rela* r, Elf_Sym* sym,
+ const char* fromsec, const char* tosec)
+{
+ Elf_Sym* fromsym = find_elf_symbol2(elf, r->r_offset, fromsec);
+ const char* fromsym_name = sym_name(elf, fromsym);
+ Elf_Sym* tosym = find_elf_symbol(elf, r->r_addend, sym);
+ const char* tosym_name = sym_name(elf, tosym);
+ const char* from_pretty_name;
+ const char* from_pretty_name_p;
+ const char* to_pretty_name;
+ const char* to_pretty_name_p;
+
+ get_pretty_name(is_function(fromsym),
+ &from_pretty_name, &from_pretty_name_p);
+ get_pretty_name(is_function(tosym),
+ &to_pretty_name, &to_pretty_name_p);
+
+ warn("%s(%s+0x%lx): Section mismatch in reference from the %s %s%s to the %s %s:%s%s\n",
+ modname, fromsec, (long)r->r_offset, from_pretty_name,
+ fromsym_name, from_pretty_name_p,
+ to_pretty_name, tosec, tosym_name, to_pretty_name_p);
+
+ if (!match(tosec, mismatch->bad_tosec) &&
+ is_executable_section(elf, get_secindex(elf, sym)))
+ fprintf(stderr,
+ "The relocation at %s+0x%lx references\n"
+ "section \"%s\" which is not in the list of\n"
+ "authorized sections. If you're adding a new section\n"
+ "and/or if this reference is valid, add \"%s\" to the\n"
+ "list of authorized sections to jump to on fault.\n"
+ "This can be achieved by adding \"%s\" to \n"
+ "OTHER_TEXT_SECTIONS in scripts/mod/modpost.c.\n",
+ fromsec, (long)r->r_offset, tosec, tosec, tosec);
+}
+
+static void extable_mismatch_handler(const char* modname, struct elf_info *elf,
+ const struct sectioncheck* const mismatch,
+ Elf_Rela* r, Elf_Sym* sym,
+ const char *fromsec)
+{
+ const char* tosec = sec_name(elf, get_secindex(elf, sym));
+
+ sec_mismatch_count++;
+
+ report_extable_warnings(modname, elf, mismatch, r, sym, fromsec, tosec);
+
+ if (match(tosec, mismatch->bad_tosec))
+ fatal("The relocation at %s+0x%lx references\n"
+ "section \"%s\" which is black-listed.\n"
+ "Something is seriously wrong and should be fixed.\n"
+ "You might get more information about where this is\n"
+ "coming from by using scripts/check_extable.sh %s\n",
+ fromsec, (long)r->r_offset, tosec, modname);
+ else if (!is_executable_section(elf, get_secindex(elf, sym))) {
+ if (is_extable_fault_address(r))
+ fatal("The relocation at %s+0x%lx references\n"
+ "section \"%s\" which is not executable, IOW\n"
+ "it is not possible for the kernel to fault\n"
+ "at that address. Something is seriously wrong\n"
+ "and should be fixed.\n",
+ fromsec, (long)r->r_offset, tosec);
+ else
+ fatal("The relocation at %s+0x%lx references\n"
+ "section \"%s\" which is not executable, IOW\n"
+ "the kernel will fault if it ever tries to\n"
+ "jump to it. Something is seriously wrong\n"
+ "and should be fixed.\n",
+ fromsec, (long)r->r_offset, tosec);
+ }
+}
+
+static void check_section_mismatch(const char *modname, struct elf_info *elf,
+ Elf_Rela *r, Elf_Sym *sym, const char *fromsec)
+{
+ const char *tosec = sec_name(elf, get_secindex(elf, sym));
+ const struct sectioncheck *mismatch = section_mismatch(fromsec, tosec);
+
+ if (mismatch) {
+ if (mismatch->handler)
+ mismatch->handler(modname, elf, mismatch,
+ r, sym, fromsec);
+ else
+ default_mismatch_handler(modname, elf, mismatch,
+ r, sym, fromsec);
+ }
+}
+
+static unsigned int *reloc_location(struct elf_info *elf,
+ Elf_Shdr *sechdr, Elf_Rela *r)
+{
+ return sym_get_data_by_offset(elf, sechdr->sh_info, r->r_offset);
+}
+
+static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
+{
+ unsigned int r_typ = ELF_R_TYPE(r->r_info);
+ unsigned int *location = reloc_location(elf, sechdr, r);
+
+ switch (r_typ) {
+ case R_386_32:
+ r->r_addend = TO_NATIVE(*location);
+ break;
+ case R_386_PC32:
+ r->r_addend = TO_NATIVE(*location) + 4;
+ break;
+ }
+ return 0;
+}
+
+#ifndef R_ARM_CALL
+#define R_ARM_CALL 28
+#endif
+#ifndef R_ARM_JUMP24
+#define R_ARM_JUMP24 29
+#endif
+
+#ifndef R_ARM_THM_CALL
+#define R_ARM_THM_CALL 10
+#endif
+#ifndef R_ARM_THM_JUMP24
+#define R_ARM_THM_JUMP24 30
+#endif
+#ifndef R_ARM_THM_JUMP19
+#define R_ARM_THM_JUMP19 51
+#endif
+
+static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
+{
+ unsigned int r_typ = ELF_R_TYPE(r->r_info);
+
+ switch (r_typ) {
+ case R_ARM_ABS32:
+ /* From ARM ABI: (S + A) | T */
+ r->r_addend = (int)(long)
+ (elf->symtab_start + ELF_R_SYM(r->r_info));
+ break;
+ case R_ARM_PC24:
+ case R_ARM_CALL:
+ case R_ARM_JUMP24:
+ case R_ARM_THM_CALL:
+ case R_ARM_THM_JUMP24:
+ case R_ARM_THM_JUMP19:
+ /* From ARM ABI: ((S + A) | T) - P */
+ r->r_addend = (int)(long)(elf->hdr +
+ sechdr->sh_offset +
+ (r->r_offset - sechdr->sh_addr));
+ break;
+ default:
+ return 1;
+ }
+ return 0;
+}
+
+static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r)
+{
+ unsigned int r_typ = ELF_R_TYPE(r->r_info);
+ unsigned int *location = reloc_location(elf, sechdr, r);
+ unsigned int inst;
+
+ if (r_typ == R_MIPS_HI16)
+ return 1; /* skip this */
+ inst = TO_NATIVE(*location);
+ switch (r_typ) {
+ case R_MIPS_LO16:
+ r->r_addend = inst & 0xffff;
+ break;
+ case R_MIPS_26:
+ r->r_addend = (inst & 0x03ffffff) << 2;
+ break;
+ case R_MIPS_32:
+ r->r_addend = inst;
+ break;
+ }
+ return 0;
+}
+
+#ifndef EM_RISCV
+#define EM_RISCV 243
+#endif
+
+#ifndef R_RISCV_SUB32
+#define R_RISCV_SUB32 39
+#endif
+
+#ifndef EM_LOONGARCH
+#define EM_LOONGARCH 258
+#endif
+
+#ifndef R_LARCH_SUB32
+#define R_LARCH_SUB32 55
+#endif
+
+static void section_rela(const char *modname, struct elf_info *elf,
+ Elf_Shdr *sechdr)
+{
+ Elf_Sym *sym;
+ Elf_Rela *rela;
+ Elf_Rela r;
+ unsigned int r_sym;
+ const char *fromsec;
+
+ Elf_Rela *start = (void *)elf->hdr + sechdr->sh_offset;
+ Elf_Rela *stop = (void *)start + sechdr->sh_size;
+
+ fromsec = sec_name(elf, sechdr->sh_info);
+ /* if from section (name) is know good then skip it */
+ if (match(fromsec, section_white_list))
+ return;
+
+ for (rela = start; rela < stop; rela++) {
+ r.r_offset = TO_NATIVE(rela->r_offset);
+#if KERNEL_ELFCLASS == ELFCLASS64
+ if (elf->hdr->e_machine == EM_MIPS) {
+ unsigned int r_typ;
+ r_sym = ELF64_MIPS_R_SYM(rela->r_info);
+ r_sym = TO_NATIVE(r_sym);
+ r_typ = ELF64_MIPS_R_TYPE(rela->r_info);
+ r.r_info = ELF64_R_INFO(r_sym, r_typ);
+ } else {
+ r.r_info = TO_NATIVE(rela->r_info);
+ r_sym = ELF_R_SYM(r.r_info);
+ }
+#else
+ r.r_info = TO_NATIVE(rela->r_info);
+ r_sym = ELF_R_SYM(r.r_info);
+#endif
+ r.r_addend = TO_NATIVE(rela->r_addend);
+ switch (elf->hdr->e_machine) {
+ case EM_RISCV:
+ if (!strcmp("__ex_table", fromsec) &&
+ ELF_R_TYPE(r.r_info) == R_RISCV_SUB32)
+ continue;
+ break;
+ case EM_LOONGARCH:
+ if (!strcmp("__ex_table", fromsec) &&
+ ELF_R_TYPE(r.r_info) == R_LARCH_SUB32)
+ continue;
+ break;
+ }
+ sym = elf->symtab_start + r_sym;
+ /* Skip special sections */
+ if (is_shndx_special(sym->st_shndx))
+ continue;
+ if (is_second_extable_reloc(start, rela, fromsec))
+ find_extable_entry_size(fromsec, &r);
+ check_section_mismatch(modname, elf, &r, sym, fromsec);
+ }
+}
+
+static void section_rel(const char *modname, struct elf_info *elf,
+ Elf_Shdr *sechdr)
+{
+ Elf_Sym *sym;
+ Elf_Rel *rel;
+ Elf_Rela r;
+ unsigned int r_sym;
+ const char *fromsec;
+
+ Elf_Rel *start = (void *)elf->hdr + sechdr->sh_offset;
+ Elf_Rel *stop = (void *)start + sechdr->sh_size;
+
+ fromsec = sec_name(elf, sechdr->sh_info);
+ /* if from section (name) is know good then skip it */
+ if (match(fromsec, section_white_list))
+ return;
+
+ for (rel = start; rel < stop; rel++) {
+ r.r_offset = TO_NATIVE(rel->r_offset);
+#if KERNEL_ELFCLASS == ELFCLASS64
+ if (elf->hdr->e_machine == EM_MIPS) {
+ unsigned int r_typ;
+ r_sym = ELF64_MIPS_R_SYM(rel->r_info);
+ r_sym = TO_NATIVE(r_sym);
+ r_typ = ELF64_MIPS_R_TYPE(rel->r_info);
+ r.r_info = ELF64_R_INFO(r_sym, r_typ);
+ } else {
+ r.r_info = TO_NATIVE(rel->r_info);
+ r_sym = ELF_R_SYM(r.r_info);
+ }
+#else
+ r.r_info = TO_NATIVE(rel->r_info);
+ r_sym = ELF_R_SYM(r.r_info);
+#endif
+ r.r_addend = 0;
+ switch (elf->hdr->e_machine) {
+ case EM_386:
+ if (addend_386_rel(elf, sechdr, &r))
+ continue;
+ break;
+ case EM_ARM:
+ if (addend_arm_rel(elf, sechdr, &r))
+ continue;
+ break;
+ case EM_MIPS:
+ if (addend_mips_rel(elf, sechdr, &r))
+ continue;
+ break;
+ }
+ sym = elf->symtab_start + r_sym;
+ /* Skip special sections */
+ if (is_shndx_special(sym->st_shndx))
+ continue;
+ if (is_second_extable_reloc(start, rel, fromsec))
+ find_extable_entry_size(fromsec, &r);
+ check_section_mismatch(modname, elf, &r, sym, fromsec);
+ }
+}
+
+/**
+ * A module includes a number of sections that are discarded
+ * either when loaded or when used as built-in.
+ * For loaded modules all functions marked __init and all data
+ * marked __initdata will be discarded when the module has been initialized.
+ * Likewise for modules used built-in the sections marked __exit
+ * are discarded because __exit marked function are supposed to be called
+ * only when a module is unloaded which never happens for built-in modules.
+ * The check_sec_ref() function traverses all relocation records
+ * to find all references to a section that reference a section that will
+ * be discarded and warns about it.
+ **/
+static void check_sec_ref(const char *modname, struct elf_info *elf)
+{
+ int i;
+ Elf_Shdr *sechdrs = elf->sechdrs;
+
+ /* Walk through all sections */
+ for (i = 0; i < elf->num_sections; i++) {
+ check_section(modname, elf, &elf->sechdrs[i]);
+ /* We want to process only relocation sections and not .init */
+ if (sechdrs[i].sh_type == SHT_RELA)
+ section_rela(modname, elf, &elf->sechdrs[i]);
+ else if (sechdrs[i].sh_type == SHT_REL)
+ section_rel(modname, elf, &elf->sechdrs[i]);
+ }
+}
+
+static char *remove_dot(char *s)
+{
+ size_t n = strcspn(s, ".");
+
+ if (n && s[n]) {
+ size_t m = strspn(s + n + 1, "0123456789");
+ if (m && (s[n + m + 1] == '.' || s[n + m + 1] == 0))
+ s[n] = 0;
+ }
+ return s;
+}
+
+/*
+ * The CRCs are recorded in .*.cmd files in the form of:
+ * #SYMVER <name> <crc>
+ */
+static void extract_crcs_for_object(const char *object, struct module *mod)
+{
+ char cmd_file[PATH_MAX];
+ char *buf, *p;
+ const char *base;
+ int dirlen, ret;
+
+ base = strrchr(object, '/');
+ if (base) {
+ base++;
+ dirlen = base - object;
+ } else {
+ dirlen = 0;
+ base = object;
+ }
+
+ ret = snprintf(cmd_file, sizeof(cmd_file), "%.*s.%s.cmd",
+ dirlen, object, base);
+ if (ret >= sizeof(cmd_file)) {
+ error("%s: too long path was truncated\n", cmd_file);
+ return;
+ }
+
+ buf = read_text_file(cmd_file);
+ p = buf;
+
+ while ((p = strstr(p, "\n#SYMVER "))) {
+ char *name;
+ size_t namelen;
+ unsigned int crc;
+ struct symbol *sym;
+
+ name = p + strlen("\n#SYMVER ");
+
+ p = strchr(name, ' ');
+ if (!p)
+ break;
+
+ namelen = p - name;
+ p++;
+
+ if (!isdigit(*p))
+ continue; /* skip this line */
+
+ crc = strtoul(p, &p, 0);
+ if (*p != '\n')
+ continue; /* skip this line */
+
+ name[namelen] = '\0';
+
+ /*
+ * sym_find_with_module() may return NULL here.
+ * It typically occurs when CONFIG_TRIM_UNUSED_KSYMS=y.
+ * Since commit e1327a127703, genksyms calculates CRCs of all
+ * symbols, including trimmed ones. Ignore orphan CRCs.
+ */
+ sym = sym_find_with_module(name, mod);
+ if (sym)
+ sym_set_crc(sym, crc);
+ }
+
+ free(buf);
+}
+
+/*
+ * The symbol versions (CRC) are recorded in the .*.cmd files.
+ * Parse them to retrieve CRCs for the current module.
+ */
+static void mod_set_crcs(struct module *mod)
+{
+ char objlist[PATH_MAX];
+ char *buf, *p, *obj;
+ int ret;
+
+ if (mod->is_vmlinux) {
+ strcpy(objlist, ".vmlinux.objs");
+ } else {
+ /* objects for a module are listed in the *.mod file. */
+ ret = snprintf(objlist, sizeof(objlist), "%s.mod", mod->name);
+ if (ret >= sizeof(objlist)) {
+ error("%s: too long path was truncated\n", objlist);
+ return;
+ }
+ }
+
+ buf = read_text_file(objlist);
+ p = buf;
+
+ while ((obj = strsep(&p, "\n")) && obj[0])
+ extract_crcs_for_object(obj, mod);
+
+ free(buf);
+}
+
+static void read_symbols(const char *modname)
+{
+ const char *symname;
+ char *version;
+ char *license;
+ char *namespace;
+ struct module *mod;
+ struct elf_info info = { };
+ Elf_Sym *sym;
+
+ if (!parse_elf(&info, modname))
+ return;
+
+ if (!strends(modname, ".o")) {
+ error("%s: filename must be suffixed with .o\n", modname);
+ return;
+ }
+
+ /* strip trailing .o */
+ mod = new_module(modname, strlen(modname) - strlen(".o"));
+
+ if (!mod->is_vmlinux) {
+ license = get_modinfo(&info, "license");
+ if (!license)
+ error("missing MODULE_LICENSE() in %s\n", modname);
+ while (license) {
+ if (!license_is_gpl_compatible(license)) {
+ mod->is_gpl_compatible = false;
+ break;
+ }
+ license = get_next_modinfo(&info, "license", license);
+ }
+
+ namespace = get_modinfo(&info, "import_ns");
+ while (namespace) {
+ add_namespace(&mod->imported_namespaces, namespace);
+ namespace = get_next_modinfo(&info, "import_ns",
+ namespace);
+ }
+ }
+
+ for (sym = info.symtab_start; sym < info.symtab_stop; sym++) {
+ symname = remove_dot(info.strtab + sym->st_name);
+
+ handle_symbol(mod, &info, sym, symname);
+ handle_moddevtable(mod, &info, sym, symname);
+ }
+
+ for (sym = info.symtab_start; sym < info.symtab_stop; sym++) {
+ symname = remove_dot(info.strtab + sym->st_name);
+
+ /* Apply symbol namespaces from __kstrtabns_<symbol> entries. */
+ if (strstarts(symname, "__kstrtabns_"))
+ sym_update_namespace(symname + strlen("__kstrtabns_"),
+ sym_get_data(&info, sym));
+ }
+
+ check_sec_ref(modname, &info);
+
+ if (!mod->is_vmlinux) {
+ version = get_modinfo(&info, "version");
+ if (version || all_versions)
+ get_src_version(mod->name, mod->srcversion,
+ sizeof(mod->srcversion) - 1);
+ }
+
+ parse_elf_finish(&info);
+
+ if (modversions) {
+ /*
+ * Our trick to get versioning for module struct etc. - it's
+ * never passed as an argument to an exported function, so
+ * the automatic versioning doesn't pick it up, but it's really
+ * important anyhow.
+ */
+ sym_add_unresolved("module_layout", mod, false);
+
+ mod_set_crcs(mod);
+ }
+}
+
+static void read_symbols_from_files(const char *filename)
+{
+ FILE *in = stdin;
+ char fname[PATH_MAX];
+
+ in = fopen(filename, "r");
+ if (!in)
+ fatal("Can't open filenames file %s: %m", filename);
+
+ while (fgets(fname, PATH_MAX, in) != NULL) {
+ if (strends(fname, "\n"))
+ fname[strlen(fname)-1] = '\0';
+ read_symbols(fname);
+ }
+
+ fclose(in);
+}
+
+#define SZ 500
+
+/* We first write the generated file into memory using the
+ * following helper, then compare to the file on disk and
+ * only update the later if anything changed */
+
+void __attribute__((format(printf, 2, 3))) buf_printf(struct buffer *buf,
+ const char *fmt, ...)
+{
+ char tmp[SZ];
+ int len;
+ va_list ap;
+
+ va_start(ap, fmt);
+ len = vsnprintf(tmp, SZ, fmt, ap);
+ buf_write(buf, tmp, len);
+ va_end(ap);
+}
+
+void buf_write(struct buffer *buf, const char *s, int len)
+{
+ if (buf->size - buf->pos < len) {
+ buf->size += len + SZ;
+ buf->p = NOFAIL(realloc(buf->p, buf->size));
+ }
+ strncpy(buf->p + buf->pos, s, len);
+ buf->pos += len;
+}
+
+static void check_exports(struct module *mod)
+{
+ struct symbol *s, *exp;
+
+ list_for_each_entry(s, &mod->unresolved_symbols, list) {
+ const char *basename;
+ exp = find_symbol(s->name);
+ if (!exp) {
+ if (!s->weak && nr_unresolved++ < MAX_UNRESOLVED_REPORTS)
+ modpost_log(warn_unresolved ? LOG_WARN : LOG_ERROR,
+ "\"%s\" [%s.ko] undefined!\n",
+ s->name, mod->name);
+ continue;
+ }
+ if (exp->module == mod) {
+ error("\"%s\" [%s.ko] was exported without definition\n",
+ s->name, mod->name);
+ continue;
+ }
+
+ s->module = exp->module;
+ s->crc_valid = exp->crc_valid;
+ s->crc = exp->crc;
+
+ basename = strrchr(mod->name, '/');
+ if (basename)
+ basename++;
+ else
+ basename = mod->name;
+
+ if (exp->namespace &&
+ !contains_namespace(&mod->imported_namespaces, exp->namespace)) {
+ modpost_log(allow_missing_ns_imports ? LOG_WARN : LOG_ERROR,
+ "module %s uses symbol %s from namespace %s, but does not import it.\n",
+ basename, exp->name, exp->namespace);
+ add_namespace(&mod->missing_namespaces, exp->namespace);
+ }
+
+ if (!mod->is_gpl_compatible && exp->is_gpl_only)
+ error("GPL-incompatible module %s.ko uses GPL-only symbol '%s'\n",
+ basename, exp->name);
+ }
+}
+
+static void check_modname_len(struct module *mod)
+{
+ const char *mod_name;
+
+ mod_name = strrchr(mod->name, '/');
+ if (mod_name == NULL)
+ mod_name = mod->name;
+ else
+ mod_name++;
+ if (strlen(mod_name) >= MODULE_NAME_LEN)
+ error("module name is too long [%s.ko]\n", mod->name);
+}
+
+/**
+ * Header for the generated file
+ **/
+static void add_header(struct buffer *b, struct module *mod)
+{
+ buf_printf(b, "#include <linux/module.h>\n");
+ /*
+ * Include build-salt.h after module.h in order to
+ * inherit the definitions.
+ */
+ buf_printf(b, "#define INCLUDE_VERMAGIC\n");
+ buf_printf(b, "#include <linux/build-salt.h>\n");
+ buf_printf(b, "#include <linux/elfnote-lto.h>\n");
+ buf_printf(b, "#include <linux/export-internal.h>\n");
+ buf_printf(b, "#include <linux/vermagic.h>\n");
+ buf_printf(b, "#include <linux/compiler.h>\n");
+ buf_printf(b, "\n");
+ buf_printf(b, "#ifdef CONFIG_UNWINDER_ORC\n");
+ buf_printf(b, "#include <asm/orc_header.h>\n");
+ buf_printf(b, "ORC_HEADER;\n");
+ buf_printf(b, "#endif\n");
+ buf_printf(b, "\n");
+ buf_printf(b, "BUILD_SALT;\n");
+ buf_printf(b, "BUILD_LTO_INFO;\n");
+ buf_printf(b, "\n");
+ buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n");
+ buf_printf(b, "MODULE_INFO(name, KBUILD_MODNAME);\n");
+ buf_printf(b, "\n");
+ buf_printf(b, "__visible struct module __this_module\n");
+ buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n");
+ buf_printf(b, "\t.name = KBUILD_MODNAME,\n");
+ if (mod->has_init)
+ buf_printf(b, "\t.init = init_module,\n");
+ if (mod->has_cleanup)
+ buf_printf(b, "#ifdef CONFIG_MODULE_UNLOAD\n"
+ "\t.exit = cleanup_module,\n"
+ "#endif\n");
+ buf_printf(b, "\t.arch = MODULE_ARCH_INIT,\n");
+ buf_printf(b, "};\n");
+
+ if (!external_module)
+ buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n");
+
+ buf_printf(b,
+ "\n"
+ "#ifdef CONFIG_RETPOLINE\n"
+ "MODULE_INFO(retpoline, \"Y\");\n"
+ "#endif\n");
+
+ if (strstarts(mod->name, "drivers/staging"))
+ buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n");
+
+ if (strstarts(mod->name, "tools/testing"))
+ buf_printf(b, "\nMODULE_INFO(test, \"Y\");\n");
+}
+
+static void add_exported_symbols(struct buffer *buf, struct module *mod)
+{
+ struct symbol *sym;
+
+ if (!modversions)
+ return;
+
+ /* record CRCs for exported symbols */
+ buf_printf(buf, "\n");
+ list_for_each_entry(sym, &mod->exported_symbols, list) {
+ if (!sym->crc_valid)
+ warn("EXPORT symbol \"%s\" [%s%s] version generation failed, symbol will not be versioned.\n"
+ "Is \"%s\" prototyped in <asm/asm-prototypes.h>?\n",
+ sym->name, mod->name, mod->is_vmlinux ? "" : ".ko",
+ sym->name);
+
+ buf_printf(buf, "SYMBOL_CRC(%s, 0x%08x, \"%s\");\n",
+ sym->name, sym->crc, sym->is_gpl_only ? "_gpl" : "");
+ }
+}
+
+/**
+ * Record CRCs for unresolved symbols
+ **/
+static void add_versions(struct buffer *b, struct module *mod)
+{
+ struct symbol *s;
+
+ if (!modversions)
+ return;
+
+ buf_printf(b, "\n");
+ buf_printf(b, "static const struct modversion_info ____versions[]\n");
+ buf_printf(b, "__used __section(\"__versions\") = {\n");
+
+ list_for_each_entry(s, &mod->unresolved_symbols, list) {
+ if (!s->module)
+ continue;
+ if (!s->crc_valid) {
+ warn("\"%s\" [%s.ko] has no CRC!\n",
+ s->name, mod->name);
+ continue;
+ }
+ if (strlen(s->name) >= MODULE_NAME_LEN) {
+ error("too long symbol \"%s\" [%s.ko]\n",
+ s->name, mod->name);
+ break;
+ }
+ buf_printf(b, "\t{ %#8x, \"%s\" },\n",
+ s->crc, s->name);
+ }
+
+ buf_printf(b, "};\n");
+}
+
+static void add_depends(struct buffer *b, struct module *mod)
+{
+ struct symbol *s;
+ int first = 1;
+
+ /* Clear ->seen flag of modules that own symbols needed by this. */
+ list_for_each_entry(s, &mod->unresolved_symbols, list) {
+ if (s->module)
+ s->module->seen = s->module->is_vmlinux;
+ }
+
+ buf_printf(b, "\n");
+ buf_printf(b, "MODULE_INFO(depends, \"");
+ list_for_each_entry(s, &mod->unresolved_symbols, list) {
+ const char *p;
+ if (!s->module)
+ continue;
+
+ if (s->module->seen)
+ continue;
+
+ s->module->seen = true;
+ p = strrchr(s->module->name, '/');
+ if (p)
+ p++;
+ else
+ p = s->module->name;
+ buf_printf(b, "%s%s", first ? "" : ",", p);
+ first = 0;
+ }
+ buf_printf(b, "\");\n");
+}
+
+static void add_srcversion(struct buffer *b, struct module *mod)
+{
+ if (mod->srcversion[0]) {
+ buf_printf(b, "\n");
+ buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n",
+ mod->srcversion);
+ }
+}
+
+static void write_buf(struct buffer *b, const char *fname)
+{
+ FILE *file;
+
+ if (error_occurred)
+ return;
+
+ file = fopen(fname, "w");
+ if (!file) {
+ perror(fname);
+ exit(1);
+ }
+ if (fwrite(b->p, 1, b->pos, file) != b->pos) {
+ perror(fname);
+ exit(1);
+ }
+ if (fclose(file) != 0) {
+ perror(fname);
+ exit(1);
+ }
+}
+
+static void write_if_changed(struct buffer *b, const char *fname)
+{
+ char *tmp;
+ FILE *file;
+ struct stat st;
+
+ file = fopen(fname, "r");
+ if (!file)
+ goto write;
+
+ if (fstat(fileno(file), &st) < 0)
+ goto close_write;
+
+ if (st.st_size != b->pos)
+ goto close_write;
+
+ tmp = NOFAIL(malloc(b->pos));
+ if (fread(tmp, 1, b->pos, file) != b->pos)
+ goto free_write;
+
+ if (memcmp(tmp, b->p, b->pos) != 0)
+ goto free_write;
+
+ free(tmp);
+ fclose(file);
+ return;
+
+ free_write:
+ free(tmp);
+ close_write:
+ fclose(file);
+ write:
+ write_buf(b, fname);
+}
+
+static void write_vmlinux_export_c_file(struct module *mod)
+{
+ struct buffer buf = { };
+
+ buf_printf(&buf,
+ "#include <linux/export-internal.h>\n");
+
+ add_exported_symbols(&buf, mod);
+ write_if_changed(&buf, ".vmlinux.export.c");
+ free(buf.p);
+}
+
+/* do sanity checks, and generate *.mod.c file */
+static void write_mod_c_file(struct module *mod)
+{
+ struct buffer buf = { };
+ char fname[PATH_MAX];
+ int ret;
+
+ check_modname_len(mod);
+ check_exports(mod);
+
+ add_header(&buf, mod);
+ add_exported_symbols(&buf, mod);
+ add_versions(&buf, mod);
+ add_depends(&buf, mod);
+ add_moddevtable(&buf, mod);
+ add_srcversion(&buf, mod);
+
+ ret = snprintf(fname, sizeof(fname), "%s.mod.c", mod->name);
+ if (ret >= sizeof(fname)) {
+ error("%s: too long path was truncated\n", fname);
+ goto free;
+ }
+
+ write_if_changed(&buf, fname);
+
+free:
+ free(buf.p);
+}
+
+/* parse Module.symvers file. line format:
+ * 0x12345678<tab>symbol<tab>module<tab>export<tab>namespace
+ **/
+static void read_dump(const char *fname)
+{
+ char *buf, *pos, *line;
+
+ buf = read_text_file(fname);
+ if (!buf)
+ /* No symbol versions, silently ignore */
+ return;
+
+ pos = buf;
+
+ while ((line = get_line(&pos))) {
+ char *symname, *namespace, *modname, *d, *export;
+ unsigned int crc;
+ struct module *mod;
+ struct symbol *s;
+ bool gpl_only;
+
+ if (!(symname = strchr(line, '\t')))
+ goto fail;
+ *symname++ = '\0';
+ if (!(modname = strchr(symname, '\t')))
+ goto fail;
+ *modname++ = '\0';
+ if (!(export = strchr(modname, '\t')))
+ goto fail;
+ *export++ = '\0';
+ if (!(namespace = strchr(export, '\t')))
+ goto fail;
+ *namespace++ = '\0';
+
+ crc = strtoul(line, &d, 16);
+ if (*symname == '\0' || *modname == '\0' || *d != '\0')
+ goto fail;
+
+ if (!strcmp(export, "EXPORT_SYMBOL_GPL")) {
+ gpl_only = true;
+ } else if (!strcmp(export, "EXPORT_SYMBOL")) {
+ gpl_only = false;
+ } else {
+ error("%s: unknown license %s. skip", symname, export);
+ continue;
+ }
+
+ mod = find_module(modname);
+ if (!mod) {
+ mod = new_module(modname, strlen(modname));
+ mod->from_dump = true;
+ }
+ s = sym_add_exported(symname, mod, gpl_only);
+ sym_set_crc(s, crc);
+ sym_update_namespace(symname, namespace);
+ }
+ free(buf);
+ return;
+fail:
+ free(buf);
+ fatal("parse error in symbol dump file\n");
+}
+
+static void write_dump(const char *fname)
+{
+ struct buffer buf = { };
+ struct module *mod;
+ struct symbol *sym;
+
+ list_for_each_entry(mod, &modules, list) {
+ if (mod->from_dump)
+ continue;
+ list_for_each_entry(sym, &mod->exported_symbols, list) {
+ buf_printf(&buf, "0x%08x\t%s\t%s\tEXPORT_SYMBOL%s\t%s\n",
+ sym->crc, sym->name, mod->name,
+ sym->is_gpl_only ? "_GPL" : "",
+ sym->namespace ?: "");
+ }
+ }
+ write_buf(&buf, fname);
+ free(buf.p);
+}
+
+static void write_namespace_deps_files(const char *fname)
+{
+ struct module *mod;
+ struct namespace_list *ns;
+ struct buffer ns_deps_buf = {};
+
+ list_for_each_entry(mod, &modules, list) {
+
+ if (mod->from_dump || list_empty(&mod->missing_namespaces))
+ continue;
+
+ buf_printf(&ns_deps_buf, "%s.ko:", mod->name);
+
+ list_for_each_entry(ns, &mod->missing_namespaces, list)
+ buf_printf(&ns_deps_buf, " %s", ns->namespace);
+
+ buf_printf(&ns_deps_buf, "\n");
+ }
+
+ write_if_changed(&ns_deps_buf, fname);
+ free(ns_deps_buf.p);
+}
+
+struct dump_list {
+ struct list_head list;
+ const char *file;
+};
+
+int main(int argc, char **argv)
+{
+ struct module *mod;
+ char *missing_namespace_deps = NULL;
+ char *dump_write = NULL, *files_source = NULL;
+ int opt;
+ LIST_HEAD(dump_lists);
+ struct dump_list *dl, *dl2;
+
+ while ((opt = getopt(argc, argv, "ei:mnT:o:awENd:")) != -1) {
+ switch (opt) {
+ case 'e':
+ external_module = true;
+ break;
+ case 'i':
+ dl = NOFAIL(malloc(sizeof(*dl)));
+ dl->file = optarg;
+ list_add_tail(&dl->list, &dump_lists);
+ break;
+ case 'm':
+ modversions = true;
+ break;
+ case 'n':
+ ignore_missing_files = true;
+ break;
+ case 'o':
+ dump_write = optarg;
+ break;
+ case 'a':
+ all_versions = true;
+ break;
+ case 'T':
+ files_source = optarg;
+ break;
+ case 'w':
+ warn_unresolved = true;
+ break;
+ case 'E':
+ sec_mismatch_warn_only = false;
+ break;
+ case 'N':
+ allow_missing_ns_imports = true;
+ break;
+ case 'd':
+ missing_namespace_deps = optarg;
+ break;
+ default:
+ exit(1);
+ }
+ }
+
+ list_for_each_entry_safe(dl, dl2, &dump_lists, list) {
+ read_dump(dl->file);
+ list_del(&dl->list);
+ free(dl);
+ }
+
+ while (optind < argc)
+ read_symbols(argv[optind++]);
+
+ if (files_source)
+ read_symbols_from_files(files_source);
+
+ list_for_each_entry(mod, &modules, list) {
+ if (mod->from_dump)
+ continue;
+
+ if (mod->is_vmlinux)
+ write_vmlinux_export_c_file(mod);
+ else
+ write_mod_c_file(mod);
+ }
+
+ if (missing_namespace_deps)
+ write_namespace_deps_files(missing_namespace_deps);
+
+ if (dump_write)
+ write_dump(dump_write);
+ if (sec_mismatch_count && !sec_mismatch_warn_only)
+ error("Section mismatches detected.\n"
+ "Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them.\n");
+
+ if (nr_unresolved > MAX_UNRESOLVED_REPORTS)
+ warn("suppressed %u unresolved symbol warnings because there were too many)\n",
+ nr_unresolved - MAX_UNRESOLVED_REPORTS);
+
+ return error_occurred ? 1 : 0;
+}
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/mod/sumversion.c
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/mod/sumversion.c (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/scripts/mod/sumversion.c (revision 151)
@@ -0,0 +1,410 @@
+#include <netinet/in.h>
+#ifdef __sun__
+#include <inttypes.h>
+#else
+#include <stdint.h>
+#endif
+#include <ctype.h>
+#include <errno.h>
+#include <string.h>
+#include <linux/limits.h>
+#include "modpost.h"
+
+/*
+ * Stolen form Cryptographic API.
+ *
+ * MD4 Message Digest Algorithm (RFC1320).
+ *
+ * Implementation derived from Andrew Tridgell and Steve French's
+ * CIFS MD4 implementation, and the cryptoapi implementation
+ * originally based on the public domain implementation written
+ * by Colin Plumb in 1993.
+ *
+ * Copyright (c) Andrew Tridgell 1997-1998.
+ * Modified by Steve French (sfrench@us.ibm.com) 2002
+ * Copyright (c) Cryptoapi developers.
+ * Copyright (c) 2002 David S. Miller (davem@redhat.com)
+ * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#define MD4_DIGEST_SIZE 16
+#define MD4_HMAC_BLOCK_SIZE 64
+#define MD4_BLOCK_WORDS 16
+#define MD4_HASH_WORDS 4
+
+struct md4_ctx {
+ uint32_t hash[MD4_HASH_WORDS];
+ uint32_t block[MD4_BLOCK_WORDS];
+ uint64_t byte_count;
+};
+
+static inline uint32_t lshift(uint32_t x, unsigned int s)
+{
+ x &= 0xFFFFFFFF;
+ return ((x << s) & 0xFFFFFFFF) | (x >> (32 - s));
+}
+
+static inline uint32_t F(uint32_t x, uint32_t y, uint32_t z)
+{
+ return (x & y) | ((~x) & z);
+}
+
+static inline uint32_t G(uint32_t x, uint32_t y, uint32_t z)
+{
+ return (x & y) | (x & z) | (y & z);
+}
+
+static inline uint32_t H(uint32_t x, uint32_t y, uint32_t z)
+{
+ return x ^ y ^ z;
+}
+
+#define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s))
+#define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (uint32_t)0x5A827999,s))
+#define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (uint32_t)0x6ED9EBA1,s))
+
+/* XXX: this stuff can be optimized */
+static inline void le32_to_cpu_array(uint32_t *buf, unsigned int words)
+{
+ while (words--) {
+ *buf = ntohl(*buf);
+ buf++;
+ }
+}
+
+static inline void cpu_to_le32_array(uint32_t *buf, unsigned int words)
+{
+ while (words--) {
+ *buf = htonl(*buf);
+ buf++;
+ }
+}
+
+static void md4_transform(uint32_t *hash, uint32_t const *in)
+{
+ uint32_t a, b, c, d;
+
+ a = hash[0];
+ b = hash[1];
+ c = hash[2];
+ d = hash[3];
+
+ ROUND1(a, b, c, d, in[0], 3);
+ ROUND1(d, a, b, c, in[1], 7);
+ ROUND1(c, d, a, b, in[2], 11);
+ ROUND1(b, c, d, a, in[3], 19);
+ ROUND1(a, b, c, d, in[4], 3);
+ ROUND1(d, a, b, c, in[5], 7);
+ ROUND1(c, d, a, b, in[6], 11);
+ ROUND1(b, c, d, a, in[7], 19);
+ ROUND1(a, b, c, d, in[8], 3);
+ ROUND1(d, a, b, c, in[9], 7);
+ ROUND1(c, d, a, b, in[10], 11);
+ ROUND1(b, c, d, a, in[11], 19);
+ ROUND1(a, b, c, d, in[12], 3);
+ ROUND1(d, a, b, c, in[13], 7);
+ ROUND1(c, d, a, b, in[14], 11);
+ ROUND1(b, c, d, a, in[15], 19);
+
+ ROUND2(a, b, c, d,in[ 0], 3);
+ ROUND2(d, a, b, c, in[4], 5);
+ ROUND2(c, d, a, b, in[8], 9);
+ ROUND2(b, c, d, a, in[12], 13);
+ ROUND2(a, b, c, d, in[1], 3);
+ ROUND2(d, a, b, c, in[5], 5);
+ ROUND2(c, d, a, b, in[9], 9);
+ ROUND2(b, c, d, a, in[13], 13);
+ ROUND2(a, b, c, d, in[2], 3);
+ ROUND2(d, a, b, c, in[6], 5);
+ ROUND2(c, d, a, b, in[10], 9);
+ ROUND2(b, c, d, a, in[14], 13);
+ ROUND2(a, b, c, d, in[3], 3);
+ ROUND2(d, a, b, c, in[7], 5);
+ ROUND2(c, d, a, b, in[11], 9);
+ ROUND2(b, c, d, a, in[15], 13);
+
+ ROUND3(a, b, c, d,in[ 0], 3);
+ ROUND3(d, a, b, c, in[8], 9);
+ ROUND3(c, d, a, b, in[4], 11);
+ ROUND3(b, c, d, a, in[12], 15);
+ ROUND3(a, b, c, d, in[2], 3);
+ ROUND3(d, a, b, c, in[10], 9);
+ ROUND3(c, d, a, b, in[6], 11);
+ ROUND3(b, c, d, a, in[14], 15);
+ ROUND3(a, b, c, d, in[1], 3);
+ ROUND3(d, a, b, c, in[9], 9);
+ ROUND3(c, d, a, b, in[5], 11);
+ ROUND3(b, c, d, a, in[13], 15);
+ ROUND3(a, b, c, d, in[3], 3);
+ ROUND3(d, a, b, c, in[11], 9);
+ ROUND3(c, d, a, b, in[7], 11);
+ ROUND3(b, c, d, a, in[15], 15);
+
+ hash[0] += a;
+ hash[1] += b;
+ hash[2] += c;
+ hash[3] += d;
+}
+
+static inline void md4_transform_helper(struct md4_ctx *ctx)
+{
+ le32_to_cpu_array(ctx->block, ARRAY_SIZE(ctx->block));
+ md4_transform(ctx->hash, ctx->block);
+}
+
+static void md4_init(struct md4_ctx *mctx)
+{
+ mctx->hash[0] = 0x67452301;
+ mctx->hash[1] = 0xefcdab89;
+ mctx->hash[2] = 0x98badcfe;
+ mctx->hash[3] = 0x10325476;
+ mctx->byte_count = 0;
+}
+
+static void md4_update(struct md4_ctx *mctx,
+ const unsigned char *data, unsigned int len)
+{
+ const uint32_t avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
+
+ mctx->byte_count += len;
+
+ if (avail > len) {
+ memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
+ data, len);
+ return;
+ }
+
+ memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
+ data, avail);
+
+ md4_transform_helper(mctx);
+ data += avail;
+ len -= avail;
+
+ while (len >= sizeof(mctx->block)) {
+ memcpy(mctx->block, data, sizeof(mctx->block));
+ md4_transform_helper(mctx);
+ data += sizeof(mctx->block);
+ len -= sizeof(mctx->block);
+ }
+
+ memcpy(mctx->block, data, len);
+}
+
+static void md4_final_ascii(struct md4_ctx *mctx, char *out, unsigned int len)
+{
+ const unsigned int offset = mctx->byte_count & 0x3f;
+ char *p = (char *)mctx->block + offset;
+ int padding = 56 - (offset + 1);
+
+ *p++ = 0x80;
+ if (padding < 0) {
+ memset(p, 0x00, padding + sizeof (uint64_t));
+ md4_transform_helper(mctx);
+ p = (char *)mctx->block;
+ padding = 56;
+ }
+
+ memset(p, 0, padding);
+ mctx->block[14] = mctx->byte_count << 3;
+ mctx->block[15] = mctx->byte_count >> 29;
+ le32_to_cpu_array(mctx->block, (sizeof(mctx->block) -
+ sizeof(uint64_t)) / sizeof(uint32_t));
+ md4_transform(mctx->hash, mctx->block);
+ cpu_to_le32_array(mctx->hash, ARRAY_SIZE(mctx->hash));
+
+ snprintf(out, len, "%08X%08X%08X%08X",
+ mctx->hash[0], mctx->hash[1], mctx->hash[2], mctx->hash[3]);
+}
+
+static inline void add_char(unsigned char c, struct md4_ctx *md)
+{
+ md4_update(md, &c, 1);
+}
+
+static int parse_string(const char *file, unsigned long len,
+ struct md4_ctx *md)
+{
+ unsigned long i;
+
+ add_char(file[0], md);
+ for (i = 1; i < len; i++) {
+ add_char(file[i], md);
+ if (file[i] == '"' && file[i-1] != '\\')
+ break;
+ }
+ return i;
+}
+
+static int parse_comment(const char *file, unsigned long len)
+{
+ unsigned long i;
+
+ for (i = 2; i < len; i++) {
+ if (file[i-1] == '*' && file[i] == '/')
+ break;
+ }
+ return i;
+}
+
+/* FIXME: Handle .s files differently (eg. # starts comments) --RR */
+static int parse_file(const char *fname, struct md4_ctx *md)
+{
+ char *file;
+ unsigned long i, len;
+
+ file = read_text_file(fname);
+ len = strlen(file);
+
+ for (i = 0; i < len; i++) {
+ /* Collapse and ignore \ and CR. */
+ if (file[i] == '\\' && (i+1 < len) && file[i+1] == '\n') {
+ i++;
+ continue;
+ }
+
+ /* Ignore whitespace */
+ if (isspace(file[i]))
+ continue;
+
+ /* Handle strings as whole units */
+ if (file[i] == '"') {
+ i += parse_string(file+i, len - i, md);
+ continue;
+ }
+
+ /* Comments: ignore */
+ if (file[i] == '/' && file[i+1] == '*') {
+ i += parse_comment(file+i, len - i);
+ continue;
+ }
+
+ add_char(file[i], md);
+ }
+ free(file);
+ return 1;
+}
+/* Check whether the file is a static library or not */
+static bool is_static_library(const char *objfile)
+{
+ int len = strlen(objfile);
+
+ return objfile[len - 2] == '.' && objfile[len - 1] == 'a';
+}
+
+/* We have dir/file.o. Open dir/.file.o.cmd, look for source_ and deps_ line
+ * to figure out source files. */
+static int parse_source_files(const char *objfile, struct md4_ctx *md)
+{
+ char *cmd, *file, *line, *dir, *pos;
+ const char *base;
+ int dirlen, ret = 0, check_files = 0;
+
+ cmd = NOFAIL(malloc(strlen(objfile) + sizeof("..cmd")));
+
+ base = strrchr(objfile, '/');
+ if (base) {
+ base++;
+ dirlen = base - objfile;
+ sprintf(cmd, "%.*s.%s.cmd", dirlen, objfile, base);
+ } else {
+ dirlen = 0;
+ sprintf(cmd, ".%s.cmd", objfile);
+ }
+ dir = NOFAIL(malloc(dirlen + 1));
+ strncpy(dir, objfile, dirlen);
+ dir[dirlen] = '\0';
+
+ file = read_text_file(cmd);
+
+ pos = file;
+
+ /* Sum all files in the same dir or subdirs. */
+ while ((line = get_line(&pos))) {
+ char* p = line;
+
+ if (strncmp(line, "source_", sizeof("source_")-1) == 0) {
+ p = strrchr(line, ' ');
+ if (!p) {
+ warn("malformed line: %s\n", line);
+ goto out_file;
+ }
+ p++;
+ if (!parse_file(p, md)) {
+ warn("could not open %s: %s\n",
+ p, strerror(errno));
+ goto out_file;
+ }
+ continue;
+ }
+ if (strncmp(line, "deps_", sizeof("deps_")-1) == 0) {
+ check_files = 1;
+ continue;
+ }
+ if (!check_files)
+ continue;
+
+ /* Continue until line does not end with '\' */
+ if ( *(p + strlen(p)-1) != '\\')
+ break;
+ /* Terminate line at first space, to get rid of final ' \' */
+ while (*p) {
+ if (isspace(*p)) {
+ *p = '\0';
+ break;
+ }
+ p++;
+ }
+
+ /* Check if this file is in same dir as objfile */
+ if ((strstr(line, dir)+strlen(dir)-1) == strrchr(line, '/')) {
+ if (!parse_file(line, md)) {
+ warn("could not open %s: %s\n",
+ line, strerror(errno));
+ goto out_file;
+ }
+
+ }
+
+ }
+
+ /* Everyone parsed OK */
+ ret = 1;
+out_file:
+ free(file);
+ free(dir);
+ free(cmd);
+ return ret;
+}
+
+/* Calc and record src checksum. */
+void get_src_version(const char *modname, char sum[], unsigned sumlen)
+{
+ char *buf;
+ struct md4_ctx md;
+ char *fname;
+ char filelist[PATH_MAX + 1];
+
+ /* objects for a module are listed in the first line of *.mod file. */
+ snprintf(filelist, sizeof(filelist), "%s.mod", modname);
+
+ buf = read_text_file(filelist);
+
+ md4_init(&md);
+ while ((fname = strsep(&buf, "\n"))) {
+ if (!*fname)
+ continue;
+ if (!(is_static_library(fname)) &&
+ !parse_source_files(fname, &md))
+ goto free;
+ }
+
+ md4_final_ascii(&md, sum, sumlen);
+free:
+ free(buf);
+}
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/tools/build/fixdep.c
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/tools/build/fixdep.c (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/tools/build/fixdep.c (revision 151)
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * "Optimize" a list of dependencies as spit out by gcc -MD
+ * for the build framework.
+ *
+ * Original author:
+ * Copyright 2002 by Kai Germaschewski <kai.germaschewski@gmx.de>
+ *
+ * This code has been borrowed from kbuild's fixdep (scripts/basic/fixdep.c),
+ * Please check it for detailed explanation. This fixdep borow only the
+ * base transformation of dependecies without the CONFIG mangle.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <linux/limits.h>
+
+char *target;
+char *depfile;
+char *cmdline;
+
+static void usage(void)
+{
+ fprintf(stderr, "Usage: fixdep <depfile> <target> <cmdline>\n");
+ exit(1);
+}
+
+/*
+ * Print out the commandline prefixed with cmd_<target filename> :=
+ */
+static void print_cmdline(void)
+{
+ printf("cmd_%s := %s\n\n", target, cmdline);
+}
+
+/*
+ * Important: The below generated source_foo.o and deps_foo.o variable
+ * assignments are parsed not only by make, but also by the rather simple
+ * parser in scripts/mod/sumversion.c.
+ */
+static void parse_dep_file(void *map, size_t len)
+{
+ char *m = map;
+ char *end = m + len;
+ char *p;
+ char s[PATH_MAX];
+ int is_target, has_target = 0;
+ int saw_any_target = 0;
+ int is_first_dep = 0;
+
+ while (m < end) {
+ /* Skip any "white space" */
+ while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
+ m++;
+ /* Find next "white space" */
+ p = m;
+ while (p < end && *p != ' ' && *p != '\\' && *p != '\n')
+ p++;
+ /* Is the token we found a target name? */
+ is_target = (*(p-1) == ':');
+ /* Don't write any target names into the dependency file */
+ if (is_target) {
+ /* The /next/ file is the first dependency */
+ is_first_dep = 1;
+ has_target = 1;
+ } else if (has_target) {
+ /* Save this token/filename */
+ memcpy(s, m, p-m);
+ s[p - m] = 0;
+
+ /*
+ * Do not list the source file as dependency,
+ * so that kbuild is not confused if a .c file
+ * is rewritten into .S or vice versa. Storing
+ * it in source_* is needed for modpost to
+ * compute srcversions.
+ */
+ if (is_first_dep) {
+ /*
+ * If processing the concatenation of
+ * multiple dependency files, only
+ * process the first target name, which
+ * will be the original source name,
+ * and ignore any other target names,
+ * which will be intermediate temporary
+ * files.
+ */
+ if (!saw_any_target) {
+ saw_any_target = 1;
+ printf("source_%s := %s\n\n",
+ target, s);
+ printf("deps_%s := \\\n",
+ target);
+ }
+ is_first_dep = 0;
+ } else
+ printf(" %s \\\n", s);
+ }
+ /*
+ * Start searching for next token immediately after the first
+ * "whitespace" character that follows this token.
+ */
+ m = p + 1;
+ }
+
+ if (!saw_any_target) {
+ fprintf(stderr, "fixdep: parse error; no targets found\n");
+ exit(1);
+ }
+
+ printf("\n%s: $(deps_%s)\n\n", target, target);
+ printf("$(deps_%s):\n", target);
+}
+
+static void print_deps(void)
+{
+ struct stat st;
+ int fd;
+ void *map;
+
+ fd = open(depfile, O_RDONLY);
+ if (fd < 0) {
+ fprintf(stderr, "fixdep: error opening depfile: ");
+ perror(depfile);
+ exit(2);
+ }
+ if (fstat(fd, &st) < 0) {
+ fprintf(stderr, "fixdep: error fstat'ing depfile: ");
+ perror(depfile);
+ exit(2);
+ }
+ if (st.st_size == 0) {
+ fprintf(stderr, "fixdep: %s is empty\n", depfile);
+ close(fd);
+ return;
+ }
+ map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
+ if ((long) map == -1) {
+ perror("fixdep: mmap");
+ close(fd);
+ return;
+ }
+
+ parse_dep_file(map, st.st_size);
+
+ munmap(map, st.st_size);
+
+ close(fd);
+}
+
+int main(int argc, char **argv)
+{
+ if (argc != 4)
+ usage();
+
+ depfile = argv[1];
+ target = argv[2];
+ cmdline = argv[3];
+
+ print_cmdline();
+ print_deps();
+
+ return 0;
+}
Index: v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/usr/gen_init_cpio.c
===================================================================
--- v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/usr/gen_init_cpio.c (nonexistent)
+++ v6.x/create-6.3.10-host-limits-patch/linux-6.3.10-new/usr/gen_init_cpio.c (revision 151)
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <string.h>
+#include <unistd.h>
+#include <time.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <ctype.h>
+#include <linux/limits.h>
+
+/*
+ * Original work by Jeff Garzik
+ *
+ * External file lists, symlink, pipe and fifo support by Thayne Harbaugh
+ * Hard link support by Luciano Rocha
+ */
+
+#define xstr(s) #s
+#define str(s) xstr(s)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+static unsigned int offset;
+static unsigned int ino = 721;
+static time_t default_mtime;
+static bool do_csum = false;
+
+struct file_handler {
+ const char *type;
+ int (*handler)(const char *line);
+};
+
+static void push_string(const char *name)
+{
+ unsigned int name_len = strlen(name) + 1;
+
+ fputs(name, stdout);
+ putchar(0);
+ offset += name_len;
+}
+
+static void push_pad (void)
+{
+ while (offset & 3) {
+ putchar(0);
+ offset++;
+ }
+}
+
+static void push_rest(const char *name)
+{
+ unsigned int name_len = strlen(name) + 1;
+ unsigned int tmp_ofs;
+
+ fputs(name, stdout);
+ putchar(0);
+ offset += name_len;
+
+ tmp_ofs = name_len + 110;
+ while (tmp_ofs & 3) {
+ putchar(0);
+ offset++;
+ tmp_ofs++;
+ }
+}
+
+static void push_hdr(const char *s)
+{
+ fputs(s, stdout);
+ offset += 110;
+}
+
+static void cpio_trailer(void)
+{
+ char s[256];
+ const char name[] = "TRAILER!!!";
+
+ sprintf(s, "%s%08X%08X%08lX%08lX%08X%08lX"
+ "%08X%08X%08X%08X%08X%08X%08X",
+ do_csum ? "070702" : "070701", /* magic */
+ 0, /* ino */
+ 0, /* mode */
+ (long) 0, /* uid */
+ (long) 0, /* gid */
+ 1, /* nlink */
+ (long) 0, /* mtime */
+ 0, /* filesize */
+ 0, /* major */
+ 0, /* minor */
+ 0, /* rmajor */
+ 0, /* rminor */
+ (unsigned)strlen(name)+1, /* namesize */
+ 0); /* chksum */
+ push_hdr(s);
+ push_rest(name);
+
+ while (offset % 512) {
+ putchar(0);
+ offset++;
+ }
+}
+
+static int cpio_mkslink(const char *name, const char *target,
+ unsigned int mode, uid_t uid, gid_t gid)
+{
+ char s[256];
+
+ if (name[0] == '/')
+ name++;
+ sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
+ "%08X%08X%08X%08X%08X%08X%08X",
+ do_csum ? "070702" : "070701", /* magic */
+ ino++, /* ino */
+ S_IFLNK | mode, /* mode */
+ (long) uid, /* uid */
+ (long) gid, /* gid */
+ 1, /* nlink */
+ (long) default_mtime, /* mtime */
+ (unsigned)strlen(target)+1, /* filesize */
+ 3, /* major */
+ 1, /* minor */
+ 0, /* rmajor */
+ 0, /* rminor */
+ (unsigned)strlen(name) + 1,/* namesize */
+ 0); /* chksum */
+ push_hdr(s);
+ push_string(name);
+ push_pad();
+ push_string(target);
+ push_pad();
+ return 0;
+}
+
+static int cpio_mkslink_line(const char *line)
+{
+ char name[PATH_MAX + 1];
+ char target[PATH_MAX + 1];
+ unsigned int mode;
+ int uid;
+ int gid;
+ int rc = -1;
+
+ if (5 != sscanf(line, "%" str(PATH_MAX) "s %" str(PATH_MAX) "s %o %d %d", name, target, &mode, &uid, &gid)) {
+ fprintf(stderr, "Unrecognized dir format '%s'", line);
+ goto fail;
+ }
+ rc = cpio_mkslink(name, target, mode, uid, gid);
+ fail:
+ return rc;
+}
+
+static int cpio_mkgeneric(const char *name, unsigned int mode,
+ uid_t uid, gid_t gid)
+{
+ char s[256];
+
+ if (name[0] == '/')
+ name++;
+ sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
+ "%08X%08X%08X%08X%08X%08X%08X",
+ do_csum ? "070702" : "070701", /* magic */
+ ino++, /* ino */
+ mode, /* mode */
+ (long) uid, /* uid */
+ (long) gid, /* gid */
+ 2, /* nlink */
+ (long) default_mtime, /* mtime */
+ 0, /* filesize */
+ 3, /* major */
+ 1, /* minor */
+ 0, /* rmajor */
+ 0, /* rminor */
+ (unsigned)strlen(name) + 1,/* namesize */
+ 0); /* chksum */
+ push_hdr(s);
+ push_rest(name);
+ return 0;
+}
+
+enum generic_types {
+ GT_DIR,
+ GT_PIPE,
+ GT_SOCK
+};
+
+struct generic_type {
+ const char *type;
+ mode_t mode;
+};
+
+static const struct generic_type generic_type_table[] = {
+ [GT_DIR] = {
+ .type = "dir",
+ .mode = S_IFDIR
+ },
+ [GT_PIPE] = {
+ .type = "pipe",
+ .mode = S_IFIFO
+ },
+ [GT_SOCK] = {
+ .type = "sock",
+ .mode = S_IFSOCK
+ }
+};
+
+static int cpio_mkgeneric_line(const char *line, enum generic_types gt)
+{
+ char name[PATH_MAX + 1];
+ unsigned int mode;
+ int uid;
+ int gid;
+ int rc = -1;
+
+ if (4 != sscanf(line, "%" str(PATH_MAX) "s %o %d %d", name, &mode, &uid, &gid)) {
+ fprintf(stderr, "Unrecognized %s format '%s'",
+ line, generic_type_table[gt].type);
+ goto fail;
+ }
+ mode |= generic_type_table[gt].mode;
+ rc = cpio_mkgeneric(name, mode, uid, gid);
+ fail:
+ return rc;
+}
+
+static int cpio_mkdir_line(const char *line)
+{
+ return cpio_mkgeneric_line(line, GT_DIR);
+}
+
+static int cpio_mkpipe_line(const char *line)
+{
+ return cpio_mkgeneric_line(line, GT_PIPE);
+}
+
+static int cpio_mksock_line(const char *line)
+{
+ return cpio_mkgeneric_line(line, GT_SOCK);
+}
+
+static int cpio_mknod(const char *name, unsigned int mode,
+ uid_t uid, gid_t gid, char dev_type,
+ unsigned int maj, unsigned int min)
+{
+ char s[256];
+
+ if (dev_type == 'b')
+ mode |= S_IFBLK;
+ else
+ mode |= S_IFCHR;
+
+ if (name[0] == '/')
+ name++;
+ sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
+ "%08X%08X%08X%08X%08X%08X%08X",
+ do_csum ? "070702" : "070701", /* magic */
+ ino++, /* ino */
+ mode, /* mode */
+ (long) uid, /* uid */
+ (long) gid, /* gid */
+ 1, /* nlink */
+ (long) default_mtime, /* mtime */
+ 0, /* filesize */
+ 3, /* major */
+ 1, /* minor */
+ maj, /* rmajor */
+ min, /* rminor */
+ (unsigned)strlen(name) + 1,/* namesize */
+ 0); /* chksum */
+ push_hdr(s);
+ push_rest(name);
+ return 0;
+}
+
+static int cpio_mknod_line(const char *line)
+{
+ char name[PATH_MAX + 1];
+ unsigned int mode;
+ int uid;
+ int gid;
+ char dev_type;
+ unsigned int maj;
+ unsigned int min;
+ int rc = -1;
+
+ if (7 != sscanf(line, "%" str(PATH_MAX) "s %o %d %d %c %u %u",
+ name, &mode, &uid, &gid, &dev_type, &maj, &min)) {
+ fprintf(stderr, "Unrecognized nod format '%s'", line);
+ goto fail;
+ }
+ rc = cpio_mknod(name, mode, uid, gid, dev_type, maj, min);
+ fail:
+ return rc;
+}
+
+static int cpio_mkfile_csum(int fd, unsigned long size, uint32_t *csum)
+{
+ while (size) {
+ unsigned char filebuf[65536];
+ ssize_t this_read;
+ size_t i, this_size = MIN(size, sizeof(filebuf));
+
+ this_read = read(fd, filebuf, this_size);
+ if (this_read <= 0 || this_read > this_size)
+ return -1;
+
+ for (i = 0; i < this_read; i++)
+ *csum += filebuf[i];
+
+ size -= this_read;
+ }
+ /* seek back to the start for data segment I/O */
+ if (lseek(fd, 0, SEEK_SET) < 0)
+ return -1;
+
+ return 0;
+}
+
+static int cpio_mkfile(const char *name, const char *location,
+ unsigned int mode, uid_t uid, gid_t gid,
+ unsigned int nlinks)
+{
+ char s[256];
+ struct stat buf;
+ unsigned long size;
+ int file;
+ int retval;
+ int rc = -1;
+ int namesize;
+ unsigned int i;
+ uint32_t csum = 0;
+
+ mode |= S_IFREG;
+
+ file = open (location, O_RDONLY);
+ if (file < 0) {
+ fprintf (stderr, "File %s could not be opened for reading\n", location);
+ goto error;
+ }
+
+ retval = fstat(file, &buf);
+ if (retval) {
+ fprintf(stderr, "File %s could not be stat()'ed\n", location);
+ goto error;
+ }
+
+ if (buf.st_mtime > 0xffffffff) {
+ fprintf(stderr, "%s: Timestamp exceeds maximum cpio timestamp, clipping.\n",
+ location);
+ buf.st_mtime = 0xffffffff;
+ }
+
+ if (buf.st_mtime < 0) {
+ fprintf(stderr, "%s: Timestamp negative, clipping.\n",
+ location);
+ buf.st_mtime = 0;
+ }
+
+ if (buf.st_size > 0xffffffff) {
+ fprintf(stderr, "%s: Size exceeds maximum cpio file size\n",
+ location);
+ goto error;
+ }
+
+ if (do_csum && cpio_mkfile_csum(file, buf.st_size, &csum) < 0) {
+ fprintf(stderr, "Failed to checksum file %s\n", location);
+ goto error;
+ }
+
+ size = 0;
+ for (i = 1; i <= nlinks; i++) {
+ /* data goes on last link */
+ if (i == nlinks)
+ size = buf.st_size;
+
+ if (name[0] == '/')
+ name++;
+ namesize = strlen(name) + 1;
+ sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
+ "%08lX%08X%08X%08X%08X%08X%08X",
+ do_csum ? "070702" : "070701", /* magic */
+ ino, /* ino */
+ mode, /* mode */
+ (long) uid, /* uid */
+ (long) gid, /* gid */
+ nlinks, /* nlink */
+ (long) buf.st_mtime, /* mtime */
+ size, /* filesize */
+ 3, /* major */
+ 1, /* minor */
+ 0, /* rmajor */
+ 0, /* rminor */
+ namesize, /* namesize */
+ size ? csum : 0); /* chksum */
+ push_hdr(s);
+ push_string(name);
+ push_pad();
+
+ while (size) {
+ unsigned char filebuf[65536];
+ ssize_t this_read;
+ size_t this_size = MIN(size, sizeof(filebuf));
+
+ this_read = read(file, filebuf, this_size);
+ if (this_read <= 0 || this_read > this_size) {
+ fprintf(stderr, "Can not read %s file\n", location);
+ goto error;
+ }
+
+ if (fwrite(filebuf, this_read, 1, stdout) != 1) {
+ fprintf(stderr, "writing filebuf failed\n");
+ goto error;
+ }
+ offset += this_read;
+ size -= this_read;
+ }
+ push_pad();
+
+ name += namesize;
+ }
+ ino++;
+ rc = 0;
+
+error:
+ if (file >= 0)
+ close(file);
+ return rc;
+}
+
+static char *cpio_replace_env(char *new_location)
+{
+ char expanded[PATH_MAX + 1];
+ char *start, *end, *var;
+
+ while ((start = strstr(new_location, "${")) &&
+ (end = strchr(start + 2, '}'))) {
+ *start = *end = 0;
+ var = getenv(start + 2);
+ snprintf(expanded, sizeof expanded, "%s%s%s",
+ new_location, var ? var : "", end + 1);
+ strcpy(new_location, expanded);
+ }
+
+ return new_location;
+}
+
+static int cpio_mkfile_line(const char *line)
+{
+ char name[PATH_MAX + 1];
+ char *dname = NULL; /* malloc'ed buffer for hard links */
+ char location[PATH_MAX + 1];
+ unsigned int mode;
+ int uid;
+ int gid;
+ int nlinks = 1;
+ int end = 0, dname_len = 0;
+ int rc = -1;
+
+ if (5 > sscanf(line, "%" str(PATH_MAX) "s %" str(PATH_MAX)
+ "s %o %d %d %n",
+ name, location, &mode, &uid, &gid, &end)) {
+ fprintf(stderr, "Unrecognized file format '%s'", line);
+ goto fail;
+ }
+ if (end && isgraph(line[end])) {
+ int len;
+ int nend;
+
+ dname = malloc(strlen(line));
+ if (!dname) {
+ fprintf (stderr, "out of memory (%d)\n", dname_len);
+ goto fail;
+ }
+
+ dname_len = strlen(name) + 1;
+ memcpy(dname, name, dname_len);
+
+ do {
+ nend = 0;
+ if (sscanf(line + end, "%" str(PATH_MAX) "s %n",
+ name, &nend) < 1)
+ break;
+ len = strlen(name) + 1;
+ memcpy(dname + dname_len, name, len);
+ dname_len += len;
+ nlinks++;
+ end += nend;
+ } while (isgraph(line[end]));
+ } else {
+ dname = name;
+ }
+ rc = cpio_mkfile(dname, cpio_replace_env(location),
+ mode, uid, gid, nlinks);
+ fail:
+ if (dname_len) free(dname);
+ return rc;
+}
+
+static void usage(const char *prog)
+{
+ fprintf(stderr, "Usage:\n"
+ "\t%s [-t <timestamp>] [-c] <cpio_list>\n"
+ "\n"
+ "<cpio_list> is a file containing newline separated entries that\n"
+ "describe the files to be included in the initramfs archive:\n"
+ "\n"
+ "# a comment\n"
+ "file <name> <location> <mode> <uid> <gid> [<hard links>]\n"
+ "dir <name> <mode> <uid> <gid>\n"
+ "nod <name> <mode> <uid> <gid> <dev_type> <maj> <min>\n"
+ "slink <name> <target> <mode> <uid> <gid>\n"
+ "pipe <name> <mode> <uid> <gid>\n"
+ "sock <name> <mode> <uid> <gid>\n"
+ "\n"
+ "<name> name of the file/dir/nod/etc in the archive\n"
+ "<location> location of the file in the current filesystem\n"
+ " expands shell variables quoted with ${}\n"
+ "<target> link target\n"
+ "<mode> mode/permissions of the file\n"
+ "<uid> user id (0=root)\n"
+ "<gid> group id (0=root)\n"
+ "<dev_type> device type (b=block, c=character)\n"
+ "<maj> major number of nod\n"
+ "<min> minor number of nod\n"
+ "<hard links> space separated list of other links to file\n"
+ "\n"
+ "example:\n"
+ "# A simple initramfs\n"
+ "dir /dev 0755 0 0\n"
+ "nod /dev/console 0600 0 0 c 5 1\n"
+ "dir /root 0700 0 0\n"
+ "dir /sbin 0755 0 0\n"
+ "file /sbin/kinit /usr/src/klibc/kinit/kinit 0755 0 0\n"
+ "\n"
+ "<timestamp> is time in seconds since Epoch that will be used\n"
+ "as mtime for symlinks, special files and directories. The default\n"
+ "is to use the current time for these entries.\n"
+ "-c: calculate and store 32-bit checksums for file data.\n",
+ prog);
+}
+
+static const struct file_handler file_handler_table[] = {
+ {
+ .type = "file",
+ .handler = cpio_mkfile_line,
+ }, {
+ .type = "nod",
+ .handler = cpio_mknod_line,
+ }, {
+ .type = "dir",
+ .handler = cpio_mkdir_line,
+ }, {
+ .type = "slink",
+ .handler = cpio_mkslink_line,
+ }, {
+ .type = "pipe",
+ .handler = cpio_mkpipe_line,
+ }, {
+ .type = "sock",
+ .handler = cpio_mksock_line,
+ }, {
+ .type = NULL,
+ .handler = NULL,
+ }
+};
+
+#define LINE_SIZE (2 * PATH_MAX + 50)
+
+int main (int argc, char *argv[])
+{
+ FILE *cpio_list;
+ char line[LINE_SIZE];
+ char *args, *type;
+ int ec = 0;
+ int line_nr = 0;
+ const char *filename;
+
+ default_mtime = time(NULL);
+ while (1) {
+ int opt = getopt(argc, argv, "t:ch");
+ char *invalid;
+
+ if (opt == -1)
+ break;
+ switch (opt) {
+ case 't':
+ default_mtime = strtol(optarg, &invalid, 10);
+ if (!*optarg || *invalid) {
+ fprintf(stderr, "Invalid timestamp: %s\n",
+ optarg);
+ usage(argv[0]);
+ exit(1);
+ }
+ break;
+ case 'c':
+ do_csum = true;
+ break;
+ case 'h':
+ case '?':
+ usage(argv[0]);
+ exit(opt == 'h' ? 0 : 1);
+ }
+ }
+
+ /*
+ * Timestamps after 2106-02-07 06:28:15 UTC have an ascii hex time_t
+ * representation that exceeds 8 chars and breaks the cpio header
+ * specification. Negative timestamps similarly exceed 8 chars.
+ */
+ if (default_mtime > 0xffffffff || default_mtime < 0) {
+ fprintf(stderr, "ERROR: Timestamp out of range for cpio format\n");
+ exit(1);
+ }
+
+ if (argc - optind != 1) {
+ usage(argv[0]);
+ exit(1);
+ }
+ filename = argv[optind];
+ if (!strcmp(filename, "-"))
+ cpio_list = stdin;
+ else if (!(cpio_list = fopen(filename, "r"))) {
+ fprintf(stderr, "ERROR: unable to open '%s': %s\n\n",
+ filename, strerror(errno));
+ usage(argv[0]);
+ exit(1);
+ }
+
+ while (fgets(line, LINE_SIZE, cpio_list)) {
+ int type_idx;
+ size_t slen = strlen(line);
+
+ line_nr++;
+
+ if ('#' == *line) {
+ /* comment - skip to next line */
+ continue;
+ }
+
+ if (! (type = strtok(line, " \t"))) {
+ fprintf(stderr,
+ "ERROR: incorrect format, could not locate file type line %d: '%s'\n",
+ line_nr, line);
+ ec = -1;
+ break;
+ }
+
+ if ('\n' == *type) {
+ /* a blank line */
+ continue;
+ }
+
+ if (slen == strlen(type)) {
+ /* must be an empty line */
+ continue;
+ }
+
+ if (! (args = strtok(NULL, "\n"))) {
+ fprintf(stderr,
+ "ERROR: incorrect format, newline required line %d: '%s'\n",
+ line_nr, line);
+ ec = -1;
+ }
+
+ for (type_idx = 0; file_handler_table[type_idx].type; type_idx++) {
+ int rc;
+ if (! strcmp(line, file_handler_table[type_idx].type)) {
+ if ((rc = file_handler_table[type_idx].handler(args))) {
+ ec = rc;
+ fprintf(stderr, " line %d\n", line_nr);
+ }
+ break;
+ }
+ }
+
+ if (NULL == file_handler_table[type_idx].type) {
+ fprintf(stderr, "unknown file type line %d: '%s'\n",
+ line_nr, line);
+ }
+ }
+ if (ec == 0)
+ cpio_trailer();
+
+ exit(ec);
+}
Index: v6.x/create-6.3.10-leez-p710-spi-patch/create.patch.sh
===================================================================
--- v6.x/create-6.3.10-leez-p710-spi-patch/create.patch.sh (nonexistent)
+++ v6.x/create-6.3.10-leez-p710-spi-patch/create.patch.sh (revision 151)
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+VERSION=6.3.10
+
+tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
+mv linux-$VERSION linux-$VERSION-orig
+
+cp -rf ./linux-$VERSION-new ./linux-$VERSION
+
+diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-leez-p710-spi.patch
+
+mv linux-$VERSION-leez-p710-spi.patch ../patches
+
+rm -rf ./linux-$VERSION
+rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.3.10-leez-p710-spi-patch/create.patch.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-leez-p710-spi-patch/file.list
===================================================================
--- v6.x/create-6.3.10-leez-p710-spi-patch/file.list (nonexistent)
+++ v6.x/create-6.3.10-leez-p710-spi-patch/file.list (revision 151)
@@ -0,0 +1 @@
+linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
Index: v6.x/create-6.3.10-leez-p710-spi-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
===================================================================
--- v6.x/create-6.3.10-leez-p710-spi-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts (nonexistent)
+++ v6.x/create-6.3.10-leez-p710-spi-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts (revision 151)
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Andy Yan <andy.yan@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Leez RK3399 P710";
+ compatible = "leez,p710", "rockchip,rk3399";
+
+ aliases {
+ mmc0 = &sdio0;
+ mmc1 = &sdmmc;
+ mmc2 = &sdhci;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ dc5v_adp: dc5v-adp {
+ compatible = "regulator-fixed";
+ regulator-name = "dc5v_adapter";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc3v3_lan: vcc3v3-lan {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host0: vcc5v0_host1: vcc5v0-host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host3: vcc5v0-host3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host3";
+ enable-active-high;
+ gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host3_en>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc5v_adp>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc3v3_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_hdmi: LDO_REG2 {
+ regulator-name = "vcc1v8_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8: LDO_REG3 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG4 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcc0v9_hdmi: LDO_REG7 {
+ regulator-name = "vcc0v9_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_pin>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_pin>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc1v8_dvp>;
+ audio-supply = <&vcc_1v8>;
+ sdmmc-supply = <&vccio_sd>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+ bt {
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vsel1_pin: vsel1-pin {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_pin: vsel2-pin {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host3_en: vcc5v0-host3-en {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins =
+ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+
+ vref-supply = <&vcc_1v8>;
+};
+
+&sdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host0>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host1>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ spiflash: flash@0 {
+ compatible = "winbond,w25q256", "jedec,spi-nor";
+ reg = <0>;
+ /* May run faster once verified: */
+ spi-max-frequency = <1000000>; // 1MHz
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spi-flash@0 {
+ reg = <0x0 0x2000000>; // 32MiB (Full flash)
+ label = "spi-flash";
+ };
+ };
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/create.patch.sh
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/create.patch.sh (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/create.patch.sh (revision 151)
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+VERSION=6.3.10
+
+tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
+mv linux-$VERSION linux-$VERSION-orig
+
+cp -rf ./linux-$VERSION-new ./linux-$VERSION
+
+diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-orange-pi5.patch
+
+mv linux-$VERSION-orange-pi5.patch ../patches
+
+rm -rf ./linux-$VERSION
+rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/create.patch.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/file.list
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/file.list (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/file.list (revision 151)
@@ -0,0 +1,6 @@
+linux-6.3.10/arch/arm64/boot/dts/rockchip/Makefile
+linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
+linux-6.3.10/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+linux-6.3.10/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
+linux-6.3.10/include/dt-bindings/soc/rockchip,boot-mode.h
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/Makefile
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/Makefile (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/Makefile (revision 151)
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi (revision 151)
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "rk3588-linux.dtsi"
+
+&CPU_SLEEP {
+ status = "disabled";
+};
+
+&cluster0_opp_table {
+ /delete-node/ opp-408000000;
+ /delete-node/ opp-600000000;
+ /delete-node/ opp-816000000;
+ /delete-node/ opp-1008000000;
+};
+
+&cluster1_opp_table {
+ /delete-node/ opp-408000000;
+ /delete-node/ opp-600000000;
+ /delete-node/ opp-816000000;
+ /delete-node/ opp-1008000000;
+ /delete-node/ opp-2256000000;
+ /delete-node/ opp-2304000000;
+ /delete-node/ opp-2352000000;
+ /delete-node/ opp-2400000000;
+};
+
+&cluster2_opp_table {
+ /delete-node/ opp-408000000;
+ /delete-node/ opp-600000000;
+ /delete-node/ opp-816000000;
+ /delete-node/ opp-1008000000;
+ /delete-node/ opp-2256000000;
+ /delete-node/ opp-2304000000;
+ /delete-node/ opp-2352000000;
+ /delete-node/ opp-2400000000;
+};
+
+&dfi {
+ status = "disabled";
+};
+
+&dmc {
+ status = "disabled";
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi (revision 151)
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdhci;
+ mmc2 = &sdio;
+ };
+
+ //chosen: chosen {
+ // bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait";
+ //};
+
+ cspmu: cspmu@fd10c000 {
+ compatible = "rockchip,cspmu";
+ reg = <0x0 0xfd10c000 0x0 0x1000>,
+ <0x0 0xfd10d000 0x0 0x1000>,
+ <0x0 0xfd10e000 0x0 0x1000>,
+ <0x0 0xfd10f000 0x0 0x1000>,
+ <0x0 0xfd12c000 0x0 0x1000>,
+ <0x0 0xfd12d000 0x0 0x1000>,
+ <0x0 0xfd12e000 0x0 0x1000>,
+ <0x0 0xfd12f000 0x0 0x1000>;
+ };
+
+ debug: debug@fd104000 {
+ compatible = "rockchip,debug";
+ reg = <0x0 0xfd104000 0x0 0x1000>,
+ <0x0 0xfd105000 0x0 0x1000>,
+ <0x0 0xfd106000 0x0 0x1000>,
+ <0x0 0xfd107000 0x0 0x1000>,
+ <0x0 0xfd124000 0x0 0x1000>,
+ <0x0 0xfd125000 0x0 0x1000>,
+ <0x0 0xfd126000 0x0 0x1000>,
+ <0x0 0xfd127000 0x0 0x1000>;
+ };
+
+ fiq_debugger: fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ rockchip,serial-id = <2>;
+ rockchip,wake-irq = <0>;
+ /* If enable uart uses irq instead of fiq */
+ rockchip,irq-mode-enable = <1>;
+ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
+ interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+ };
+
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ //status = "disabled";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 (8 * 0x100000)>;
+ linux,cma-default;
+ };
+
+ drm_logo: drm-logo@0 {
+ compatible = "rockchip,drm-logo";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+
+ drm_cubic_lut: drm-cubic-lut@0 {
+ compatible = "rockchip,drm-cubic-lut";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+
+ ramoops: ramoops@110000 {
+ compatible = "ramoops";
+ reg = <0x0 0x110000 0x0 0xf0000>;
+ record-size = <0x20000>;
+ console-size = <0x80000>;
+ ftrace-size = <0x00000>;
+ pmsg-size = <0x50000>;
+ };
+ };
+};
+
+&display_subsystem {
+ memory-region = <&drm_logo>;
+ memory-region-names = "drm-logo";
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "disabled";
+ center-supply = <&vdd_ddr_s0>;
+ mem-supply = <&vdd_log_s0>;
+};
+
+&rng {
+ status = "okay";
+};
+
+&rockchip_suspend {
+
+ rockchip,sleep-mode-config = <
+ (0
+ | RKPM_SLP_ARMOFF_DDRPD
+ | RKPM_SLP_PMU_PMUALIVE_32K
+ | RKPM_SLP_PMU_DIS_OSC
+ | RKPM_SLP_32K_EXT
+ | RKPM_SLP_PMU_DBG
+ )
+ >;
+};
+
+&vdd_log_s0 {
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi (revision 151)
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+&csi2_dphy0_hw {
+ status = "disabled";
+};
+
+&csi2_dphy0 {
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_ucam0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ov13850_out2>;
+ data-lanes = <1 2>;
+ };
+
+ mipi_in_ucam1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ov13855_out2>;
+ data-lanes = <1 2>;
+ };
+
+ mipi_in_ucam2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&gc5035_out>;
+ data-lanes = <1 2>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ csidphy0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi2_csi2_input>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+
+ vm149c_p1: vm149c-p1@c {
+ compatible = "silicon touch,vm149c";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "back";
+ };
+
+ ov13850_1: ov13850-1@10 {
+ compatible = "ovti,ov13850";
+ status = "disabled";
+ reg = <0x10>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim1_camera3_clk>;
+ reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CMK-CT0116";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&vm149c_p1>;
+ port {
+ ov13850_out2: endpoint {
+ remote-endpoint = <&mipi_in_ucam0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ dw9714_p1: dw9714-p1@c {
+ compatible = "dongwoon,dw9714";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <0>;
+ rockchip,vcm-start-current = <10>;
+ rockchip,vcm-rated-current = <85>;
+ rockchip,vcm-step-mode = <5>;
+ rockchip,camera-module-facing = "back";
+ };
+
+ ov13855_1: ov13855-1@36 {
+ compatible = "ovti,ov13855";
+ status = "disabled";
+ reg = <0x36>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim1_camera3_clk>;
+ reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CMK-OT2016-FV1";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&dw9714_p1>;
+ port {
+ ov13855_out2: endpoint {
+ remote-endpoint = <&mipi_in_ucam1>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ gc5035: gc5035@37 {
+ compatible = "galaxycore,gc5035";
+ status = "okay";
+ reg = <0x37>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim1_camera3_clk>;
+
+ //reset pin control by hardware,used this pin switch to mipi input
+ //0->FRONT camera, 1->REAR camera
+ reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "front";
+ rockchip,camera-module-name = "XHG-RKX11F-V5";
+ rockchip,camera-module-lens-name = "HR232H65";
+ port {
+ gc5035_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam2>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&mipi2_csi2 {
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi2_csi2_input: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csidphy0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi2_csi2_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&cif_mipi_in2>;
+ };
+ };
+ };
+};
+
+&rkcif_mipi_lvds2 {
+ status = "disabled";
+ port {
+ cif_mipi_in2: endpoint {
+ remote-endpoint = <&mipi2_csi2_output>;
+ };
+ };
+};
+
+&rkcif_mipi_lvds2_sditf {
+ status = "disabled";
+ port {
+ mipi2_lvds_sditf: endpoint {
+ remote-endpoint = <&isp0_vir1>;
+ };
+ };
+};
+
+&rkisp0_vir1 {
+ status = "disabled";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ isp0_vir1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi2_lvds_sditf>;
+ };
+ };
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-camera1.dtsi
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-lcd.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-lcd.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus-lcd.dtsi (revision 151)
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&dsi1 {
+ status = "disabled";
+};
+
+&dsi1_panel {
+ status = "disabled";
+ reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rst_gpio>;
+};
+
+&dsi1_in_vp2 {
+ status = "disabled";
+};
+
+&dsi1_in_vp3 {
+ status = "disabled";
+};
+
+&route_dsi1 {
+ status = "disabled";
+ connect = <&vp3_out_dsi1>;
+};
+
+&i2c7 {
+ status = "okay";
+
+ gt9xx_0: touchscreen@14 {
+ compatible = "goodix,gt9271";
+ reg = <0x14>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio2 RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ touchscreen-inverted-x;
+ //touchscreen-inverted-y;
+ touchscreen-swapped-x-y;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ status = "okay";
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts (revision 151)
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-orangepi-5-plus.dtsi"
+#include "rk3588-linux.dtsi"
+#include "rk3588-orangepi-5-plus-lcd.dtsi"
+#include "rk3588-orangepi-5-plus-camera1.dtsi"
+
+/ {
+ model = "RK3588 OPi 5 Plus";
+ compatible = "rockchip,rk3588-orangepi-5-plus", "rockchip,rk3588";
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_rgb>;
+ status = "okay";
+
+ blue_led@1 {
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ label = "blue_led";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+
+ green_led@2 {
+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+ label = "green_led";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ pwms = <&pwm3 0 50000 0>;
+ cooling-levels = <0 50 100 150 200 255>;
+ rockchip,temp-trips = <
+ 50000 1
+ 55000 2
+ 60000 3
+ 65000 4
+ 70000 5
+ >;
+
+ status = "okay";
+ };
+};
+
+&sdhci {
+ status = "okay";
+};
+
+&mipi_dcphy0 {
+ status = "okay";
+};
+
+&mipi_dcphy1 {
+ status = "okay";
+};
+
+&rkcif {
+ status = "okay";
+};
+
+&rkcif_mmu {
+ status = "okay";
+};
+
+&rkisp0 {
+ status = "okay";
+};
+
+&isp0_mmu {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* Fan */
+&pwm3 {
+ status = "okay";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m1_pins>;
+};
+
+/* watchdog */
+&wdt {
+ status = "okay";
+};
+
+&sfc {
+ status = "okay";
+ max-freq = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim1_pins>;
+
+ spi_flash: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ loader@0 {
+ label = "loader";
+ reg = <0x0 0x1000000>;
+ };
+ };
+ };
+};
+
+&pwm15 {
+ compatible = "rockchip,remotectl-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm15m1_pins>;
+ remote_pwm_id = <3>;
+ handle_cpu_id = <1>;
+ remote_support_psci = <0>;
+ status = "okay";
+
+ ir_key1 {
+ rockchip,usercode = <0xfb04>;
+ rockchip,key_table =
+ <0xa3 KEY_ENTER>,
+ <0xe4 388>,
+ <0xf5 KEY_BACK>,
+ <0xbb KEY_UP>,
+ <0xe2 KEY_DOWN>,
+ <0xe3 KEY_LEFT>,
+ <0xb7 KEY_RIGHT>,
+ <0xe0 KEY_HOME>,
+ <0xba KEY_VOLUMEUP>,
+ <0xda KEY_VOLUMEUP>,
+ <0xe6 KEY_VOLUMEDOWN>,
+ <0xdb KEY_VOLUMEDOWN>,
+ <0xbc KEY_SEARCH>,
+ <0xb2 KEY_POWER>,
+ <0xe5 KEY_POWER>,
+ <0xde KEY_POWER>,
+ <0xdc KEY_MUTE>,
+ <0xa2 KEY_MENU>,
+ <0xec KEY_1>,
+ <0xef KEY_2>,
+ <0xee KEY_3>,
+ <0xf0 KEY_4>,
+ <0xf3 KEY_5>,
+ <0xf2 KEY_6>,
+ <0xf4 KEY_7>,
+ <0xf7 KEY_8>,
+ <0xf6 KEY_9>,
+ <0xb8 KEY_0>;
+ };
+};
+
+&pinctrl {
+ leds_gpio {
+ leds_rgb: leds-rgb {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+/*** 40 pins ***/
+&i2c2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m0_xfer>;
+};
+
+&can0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0m0_pins>;
+ assigned-clocks = <&cru CLK_CAN0>;
+ assigned-clock-rates = <200000000>;
+};
+
+&can1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1m0_pins>;
+ assigned-clocks = <&cru CLK_CAN1>;
+ assigned-clock-rates = <200000000>;
+};
+
+&pwm0 {
+ status = "disabled";
+};
+
+&pwm1 {
+ status = "disabled";
+};
+
+&pwm14 {
+ status = "disabled";
+};
+
+&spi0 {
+ status = "disabled";
+ assigned-clocks = <&cru CLK_SPI0>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+};
+
+&uart3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m1_xfer>;
+};
+
+&uart4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m2_xfer>;
+};
+
+&i2c2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m4_xfer>;
+};
+
+&i2c4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m3_xfer>;
+};
+
+&i2c5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m3_xfer>;
+};
+
+&i2c8 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8m2_xfer>;
+};
+
+&uart1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m1_xfer>;
+};
+
+&uart6 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m1_xfer>;
+};
+
+&uart7 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7m2_xfer>;
+};
+
+&uart8 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m1_xfer>;
+};
+
+&pwm10 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm10m0_pins>;
+};
+
+&pwm11 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm11m0_pins>;
+};
+
+&pwm12 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm12m0_pins>;
+};
+
+&pwm13 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m2_pins>;
+ //pinctrl-0 = <&pwm13m0_pins>;
+};
+
+&spi4 {
+ status = "disabled";
+ assigned-clocks = <&cru CLK_SPI4>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+};
+/*** 40 pins ***/
+
+&hdmirx_ctrler {
+ status = "disabled";
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dtsi (revision 151)
@@ -0,0 +1,770 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "dt-bindings/usb/pd.h"
+#include "rk3588.dtsi"
+#include "rk3588-orangepi.dtsi"
+#include "rk3588-rk806-single.dtsi"
+
+/ {
+ /* If hdmirx node is disabled, delete the reserved-memory node here. */
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Reserve 128MB memory for hdmirx-controller@fdee0000 */
+ cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>;
+ linux,cma-default;
+ };
+ };
+
+ hdmiin_dc: hdmiin-dc {
+ compatible = "rockchip,dummy-codec";
+ #sound-dai-cells = <0>;
+ };
+
+ es8388_sound: es8388-sound {
+ status = "okay";
+ compatible = "rockchip,multicodecs-card";
+ rockchip,card-name = "rockchip,es8388";
+ hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ io-channels = <&saradc 3>;
+ io-channel-names = "adc-detect";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+ spk-con-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ hp-con-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ rockchip,format = "i2s";
+ rockchip,mclk-fs = <256>;
+ rockchip,cpu = <&i2s0_8ch>;
+ rockchip,codec = <&es8388>;
+ rockchip,audio-routing =
+ "Headphone", "LOUT1",
+ "Headphone", "ROUT1",
+ "Speaker", "LOUT2",
+ "Speaker", "ROUT2",
+ "Headphone", "Headphone Power",
+ "Headphone", "Headphone Power",
+ "Speaker", "Speaker Power",
+ "Speaker", "Speaker Power",
+ "LINPUT1", "Main Mic",
+ "LINPUT2", "Main Mic",
+ "RINPUT1", "Headset Mic",
+ "RINPUT2", "Headset Mic";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ play-pause-key {
+ label = "playpause";
+ linux,code = <KEY_PLAYPAUSE>;
+ press-threshold-microvolt = <2000>;
+ };
+ };
+
+ hdmiin-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,hdmiin";
+ simple-audio-card,bitclock-master = <&dailink0_master>;
+ simple-audio-card,frame-master = <&dailink0_master>;
+ status = "okay";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s7_8ch>;
+ };
+ dailink0_master: simple-audio-card,codec {
+ sound-dai = <&hdmiin_dc>;
+ };
+ };
+
+ pcie20_avdd0v85: pcie20-avdd0v85 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd0v85";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ pcie20_avdd1v8: pcie20-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd1v8";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ pcie30_avdd0v75: pcie30-avdd0v75 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v75";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ rk_headset: rk-headset {
+ status = "disabled";
+ compatible = "rockchip_headset";
+ headset_gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ io-channels = <&saradc 3>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_usb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_usb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ };
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_pcie_eth: vcc3v3-pcie-eth {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie_eth";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-low;
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_mipicsi0: vcc-mipicsi0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_mipicsi0";
+ enable-active-high;
+ };
+
+ vcc_mipicsi1: vcc-mipicsi1-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_mipicsi1";
+ enable-active-high;
+ };
+
+ vcc_mipidcphy0: vcc-mipidcphy0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_mipicsi1";
+ enable-active-high;
+ };
+
+ wireless_bluetooth: wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
+ pinctrl-1 = <&uart9_gpios>;
+ BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ wireless_wlan: wireless-wlan {
+ compatible = "wlan-platdata";
+ wifi_chip_type = "ap6275p";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_irq>;
+ WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ wifi_disable: wifi-diable-gpio-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "wifi_disable";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&backlight {
+ pwms = <&pwm2 0 25000 0>;
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&dp0 {
+ status = "okay";
+};
+
+&dp0_in_vp0 {
+ status = "disabled";
+};
+
+&dp0_in_vp1 {
+ status = "disabled";
+};
+
+&dp0_in_vp2 {
+ status = "okay";
+};
+
+&dp0_sound{
+ status = "okay";
+};
+
+&spdif_tx2{
+ status = "okay";
+};
+
+/*
+ * mipi_dcphy0 needs to be enabled
+ * when dsi0 is enabled
+ */
+&dsi0 {
+ status = "disabled";
+};
+
+&dsi0_in_vp2 {
+ status = "disabled";
+};
+
+&dsi0_in_vp3 {
+ status = "disabled";
+};
+
+&dsi0_panel {
+ status = "disabled";
+};
+
+/*
+ * mipi_dcphy1 needs to be enabled
+ * when dsi1 is enabled
+ */
+&dsi1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipi_te1>;
+};
+
+&dsi1_in_vp2 {
+ status = "disabled";
+};
+
+&dsi1_in_vp3 {
+ status = "disabled";
+};
+
+&dsi1_panel {
+ status = "disabled";
+};
+
+&gmac0 {
+ status = "disabled";
+};
+
+&hdmi0 {
+ status = "okay";
+ enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ cec-enable = "true";
+};
+
+&hdmi0_in_vp0 {
+ status = "okay";
+};
+
+&hdmi0_in_vp1 {
+ status = "disabled";
+};
+
+&hdmi0_in_vp2 {
+ status = "disabled";
+};
+
+&hdmi0_sound {
+ status = "okay";
+};
+
+&hdmi1 {
+ status = "okay";
+ enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+ cec-enable = "true";
+};
+
+&hdmi1_in_vp0 {
+ status = "disabled";
+};
+
+&hdmi1_in_vp1 {
+ status = "okay";
+};
+
+&hdmi1_in_vp2 {
+ status = "disabled";
+};
+
+&hdmi1_sound {
+ status = "okay";
+};
+
+/* Should work with at least 128MB cma reserved above. */
+&hdmirx_ctrler {
+ status = "disabled";
+
+ /* Effective level used to trigger HPD: 0-low, 1-high */
+ hpd-trigger-level = <1>;
+ hdmirx-det-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>;
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&hdptxphy_hdmi1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+
+ vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
+ compatible = "rockchip,rk8603";
+ reg = <0x43>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m0_xfer>;
+
+ usbc0: fusb302@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus5v0_typec>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_role_sw: endpoint@0 {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+ };
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ altmodes {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ altmode@0 {
+ reg = <0>;
+ svid = <0xff01>;
+ vdo = <0xffffffff>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_orien_sw: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m2_xfer>;
+
+ vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_npu_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ es8388: es8388@11 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+ compatible = "everest,es8388", "everest,es8323";
+ reg = <0x11>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_mclk>;
+ };
+};
+
+&i2s5_8ch {
+ status = "okay";
+};
+
+&i2s6_8ch {
+ status = "okay";
+};
+
+&i2s7_8ch {
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&mipi_dcphy0 {
+ status = "disabled";
+};
+
+&mipi_dcphy1 {
+ status = "disabled";
+};
+
+//phy1
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ rockchip,skip-scan-in-resume;
+ status = "okay";
+};
+
+//phy2
+&pcie2x1l1 {
+ reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+//phy0
+&pcie2x1l2 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie30phy {
+ rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ hdmi {
+ hdmirx_det: hdmirx-det {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ lcd {
+ lcd_rst_gpio: lcd-rst-gpio {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart9_gpios: uart9-gpios {
+ rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reset_gpio: bt-reset-gpio {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_gpio: bt-wake-gpio {
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_irq_gpio: bt-irq-gpio {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wireless-wlan {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwr: sdmmc_pwr {
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2m2_pins>;
+ status = "okay";
+};
+
+&sata0 {
+ status = "disabled";
+};
+
+&u2phy1_otg {
+ phy-supply = <&vcc5v0_host>;
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+};
+
+&uart9 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
+};
+
+&usbdp_phy0 {
+ orientation-switch;
+ svid = <0xff01>;
+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+ };
+};
+
+&usbdp_phy1 {
+ rockchip,dp-lane-mux = <2 3>;
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+ usb-role-switch;
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_0_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
+};
+
+&usbhost3_0 {
+ status = "disabled";
+};
+
+&usbhost_dwc3_0 {
+ status = "disabled";
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-orangepi.dtsi (revision 151)
@@ -0,0 +1,651 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/input/rk-input.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
+#include <dt-bindings/display/rockchip_vop.h>
+#include <dt-bindings/sensor-dev.h>
+
+/ {
+ adc_keys: adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ vol-up-key {
+ label = "volume up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ vol-down-key {
+ label = "volume down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ menu-key {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ back-key {
+ label = "back";
+ linux,code = <KEY_BACK>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <
+ 0 20 20 21 21 22 22 23
+ 23 24 24 25 25 26 26 27
+ 27 28 28 29 29 30 30 31
+ 31 32 32 33 33 34 34 35
+ 35 36 36 37 37 38 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255
+ >;
+ default-brightness-level = <200>;
+ };
+
+ dp0_sound: dp0-sound {
+ status = "disabled";
+ compatible = "rockchip,hdmi";
+ rockchip,card-name= "rockchip,dp0";
+ rockchip,mclk-fs = <512>;
+ rockchip,cpu = <&spdif_tx2>;
+ rockchip,codec = <&dp0 1>;
+ rockchip,jack-det;
+ };
+
+ dp1_sound: dp1-sound {
+ status = "disabled";
+ compatible = "rockchip,hdmi";
+ rockchip,card-name= "rockchip,dp1";
+ rockchip,mclk-fs = <512>;
+ rockchip,cpu = <&spdif_tx5>;
+ rockchip,codec = <&dp1 1>;
+ rockchip,jack-det;
+ };
+
+ hdmi0_sound: hdmi0-sound {
+ status = "disabled";
+ compatible = "rockchip,hdmi";
+ rockchip,mclk-fs = <128>;
+ rockchip,card-name = "rockchip-hdmi0";
+ rockchip,cpu = <&i2s5_8ch>;
+ rockchip,codec = <&hdmi0>;
+ rockchip,jack-det;
+ };
+
+ hdmi1_sound: hdmi1-sound {
+ status = "disabled";
+ compatible = "rockchip,hdmi";
+ rockchip,mclk-fs = <128>;
+ rockchip,card-name = "rockchip-hdmi1";
+ rockchip,cpu = <&i2s6_8ch>;
+ rockchip,codec = <&hdmi1>;
+ rockchip,jack-det;
+ };
+
+ spdif_tx1_dc: spdif-tx1-dc {
+ status = "disabled";
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ spdif_tx1_sound: spdif-tx1-sound {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rockchip,spdif-tx1";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif_tx1>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&spdif_tx1_dc>;
+ };
+ };
+
+ test-power {
+ status = "disabled";
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ spi2: spi@feb20000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb20000 0x0 0x1000>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 15>, <&dmac1 16>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <2>;
+ status = "okay";
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ enable-active-low;
+ };
+};
+
+&av1d_mmu {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "disabled";
+ //rockchip,lane-rate = <1000>;
+ dsi0_panel: panel@0 {
+ status = "disabled";
+ compatible = "innolux,afj101-ba2131";
+ reg = <0>;
+ backlight = <&backlight>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_in_dsi: endpoint {
+ remote-endpoint = <&dsi_out_panel>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi_out_panel: endpoint {
+ remote-endpoint = <&panel_in_dsi>;
+ };
+ };
+ };
+};
+
+&dsi1 {
+ status = "disabled";
+ //rockchip,lane-rate = <1000>;
+ dsi1_panel: panel@0 {
+ status = "disabled";
+ compatible = "innolux,afj101-ba2131";
+ reg = <0>;
+ backlight = <&backlight>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_in_dsi1: endpoint {
+ remote-endpoint = <&dsi1_out_panel>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi1_out_panel: endpoint {
+ remote-endpoint = <&panel_in_dsi1>;
+ };
+ };
+ };
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ mem-supply = <&vdd_gpu_mem_s0>;
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+};
+
+&iep {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&jpegd {
+ status = "okay";
+};
+
+&jpegd_mmu {
+ status = "okay";
+};
+
+&jpege_ccu {
+ status = "okay";
+};
+&jpege0 {
+ status = "okay";
+};
+
+&jpege0_mmu {
+ status = "okay";
+};
+
+&jpege1 {
+ status = "okay";
+};
+
+&jpege1_mmu {
+ status = "okay";
+};
+
+&jpege2 {
+ status = "okay";
+};
+
+&jpege2_mmu {
+ status = "okay";
+};
+
+&jpege3 {
+ status = "okay";
+};
+
+&jpege3_mmu {
+ status = "okay";
+};
+
+&mpp_srv {
+ status = "okay";
+};
+
+&rga3_core0 {
+ status = "okay";
+};
+
+&rga3_0_mmu {
+ status = "okay";
+};
+
+&rga3_core1 {
+ status = "okay";
+};
+
+&rga3_1_mmu {
+ status = "okay";
+};
+
+&rga2 {
+ status = "okay";
+};
+
+&rknpu {
+ rknpu-supply = <&vdd_npu_s0>;
+ mem-supply = <&vdd_npu_mem_s0>;
+ status = "okay";
+};
+
+&rknpu_mmu {
+ status = "okay";
+};
+
+&rkvdec_ccu {
+ status = "okay";
+};
+
+&rkvdec0 {
+ status = "okay";
+};
+
+&rkvdec0_mmu {
+ status = "okay";
+};
+
+&rkvdec1 {
+ status = "okay";
+};
+
+&rkvdec1_mmu {
+ status = "okay";
+};
+
+&rkvenc_ccu {
+ status = "okay";
+};
+
+&rkvenc0 {
+ status = "okay";
+};
+
+&rkvenc0_mmu {
+ status = "okay";
+};
+
+&rkvenc1 {
+ status = "okay";
+};
+
+&rkvenc1_mmu {
+ status = "okay";
+};
+
+&rockchip_suspend {
+ status = "okay";
+ rockchip,sleep-debug-en = <1>;
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc_1v8_s0>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "disabled";
+};
+
+&sdmmc {
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_sd_s0>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ rockchip,typec-vbus-det;
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&usbdp_phy0_dp {
+ status = "okay";
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usbdp_phy1_dp {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbhost3_0 {
+ status = "okay";
+};
+
+&usbhost_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+};
+
+&vdpu {
+ status = "okay";
+};
+
+&vdpu_mmu {
+ status = "okay";
+};
+
+&vepu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+ disable-win-move;
+ assigned-clocks = <&cru ACLK_VOP>;
+ assigned-clock-rates = <800000000>;
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+/* vp0 & vp1 splice for 8K output */
+&vp0 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART0>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER0>;
+};
+
+&vp1 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART1>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER1>;
+};
+
+&vp2 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART2>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER2>;
+};
+
+&vp3 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART3>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER3>;
+};
+
+&display_subsystem {
+ clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
+ clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi (revision 151)
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/display/rockchip_vop.h>
+
+/ {
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <
+ 0 20 20 21 21 22 22 23
+ 23 24 24 25 25 26 26 27
+ 27 28 28 29 29 30 30 31
+ 31 32 32 33 33 34 34 35
+ 35 36 36 37 37 38 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255
+ >;
+ default-brightness-level = <200>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_ddr_s0>;
+ mem-supply = <&vdd_log_s0>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ mem-supply = <&vdd_gpu_mem_s0>;
+ status = "okay";
+};
+
+&gpu_opp_table {
+ /delete-node/ opp-198000000;
+ /delete-node/ opp-297000000;
+ /delete-node/ opp-396000000;
+ /delete-node/ opp-594000000;
+};
+
+&iep {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&jpegd {
+ status = "okay";
+};
+
+&jpegd_mmu {
+ status = "okay";
+};
+
+&jpege_ccu {
+ status = "okay";
+};
+
+&jpege0 {
+ status = "okay";
+};
+
+&jpege0_mmu {
+ status = "okay";
+};
+
+&jpege1 {
+ status = "okay";
+};
+
+&jpege1_mmu {
+ status = "okay";
+};
+
+&jpege2 {
+ status = "okay";
+};
+
+&jpege2_mmu {
+ status = "okay";
+};
+
+&jpege3 {
+ status = "okay";
+};
+
+&jpege3_mmu {
+ status = "okay";
+};
+
+&mpp_srv {
+ status = "okay";
+};
+
+&rga2 {
+ status = "okay";
+};
+
+&rga3_core0 {
+ status = "okay";
+};
+
+&rga3_0_mmu {
+ status = "okay";
+};
+
+&rga3_core1 {
+ status = "okay";
+};
+
+&rga3_1_mmu {
+ status = "okay";
+};
+
+&rknpu {
+ rknpu-supply = <&vdd_npu_s0>;
+ mem-supply = <&vdd_npu_mem_s0>;
+ status = "okay";
+};
+
+&rknpu_mmu {
+ status = "okay";
+};
+
+&rkvdec_ccu {
+ status = "okay";
+};
+
+&rkvdec0 {
+ status = "okay";
+};
+
+&rkvdec0_mmu {
+ status = "okay";
+};
+
+&rkvdec1 {
+ status = "okay";
+};
+
+&rkvdec1_mmu {
+ status = "okay";
+};
+
+&rkvenc_ccu {
+ status = "okay";
+};
+
+&rkvenc0 {
+ status = "okay";
+};
+
+&rkvenc0_mmu {
+ status = "okay";
+};
+
+&rkvenc1 {
+ status = "okay";
+};
+
+&rkvenc1_mmu {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc_1v8_s0>;
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&usbdp_phy0_dp {
+ status = "okay";
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usbdp_phy1_dp {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbhost3_0 {
+ status = "okay";
+};
+
+&usbhost_dwc3_0 {
+ status = "okay";
+};
+
+&vdpu {
+ status = "okay";
+};
+
+&vdpu_mmu {
+ status = "okay";
+};
+
+&vepu {
+ status = "okay";
+};
+
+&vop {
+ disable-win-move;
+ assigned-clocks = <&cru DCLK_VOP0_SRC>,
+ <&cru DCLK_VOP1_SRC>,
+ <&cru DCLK_VOP2_SRC>,
+ <&cru DCLK_VOP3>;
+ assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi (revision 151)
@@ -0,0 +1,782 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+
+ rk806master: rk806master@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default", "pmic-power-off";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-1 = <&rk806_dvs1_pwrdn>;
+
+ /* 2800mv-3500mv */
+ low_voltage_threshold = <3000>;
+ /* 2700mv-3400mv */
+ shutdown_voltage_threshold = <2700>;
+ /* 140 160 */
+ shutdown_temperture_threshold = <160>;
+ hotdie_temperture_threshold = <115>;
+
+ /* 0: restart PMU;
+ * 1: reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode;
+ * 2: Reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode,
+ * and simultaneously pull down the RESETB PIN for 5mS before releasing
+ */
+ pmic-reset-func = <1>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc5v0_sys>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ pwrkey {
+ status = "okay";
+ };
+
+ pinctrl_rk806: pinctrl_rk806 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: rk806_dvs1_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: rk806_dvs1_slp {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: rk806_dvs1_rst {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_null: rk806_dvs2_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_slp: rk806_dvs2_slp {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: rk806_dvs2_rst {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: rk806_dvs2_dvs {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: rk806_dvs2_gpio {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_null: rk806_dvs3_null {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_slp: rk806_dvs3_slp {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: rk806_dvs3_rst {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: rk806_dvs3_dvs {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: rk806_dvs3_gpio {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+ };
+
+ regulators {
+ vdd_gpu_s0: DCDC_REG1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu_mem_s0: DCDC_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+ regulator-name = "vdd_gpu_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_mem_s0: DCDC_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: DCDC_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vdd_vdenc_mem_s0: DCDC_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd2_ddr_s3: DCDC_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: DCDC_REG10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+
+ avcc_1v8_s0: PLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd1_1v8_ddr_s3: PLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd1_1v8_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_codec_s0: PLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avcc_1v8_codec_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s3: PLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: PLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_1v8_s3: PLDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: NLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd2l_0v9_ddr_s3: NLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd2l_0v9_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_0v75_hdmi_edp_s0: NLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+ regulator-name = "vdd_0v75_hdmi_edp_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v75_s0: NLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: NLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ rk806slave: rk806slave@1 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x01>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
+
+ /* 0: restart PMU;
+ * 1: reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode;
+ * 2: Reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode,
+ * and simultaneously pull down the RESETB PIN for 5mS before releasing
+ */
+ pmic-reset-func = <1>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ pwrkey {
+ status = "disabled";
+ };
+
+ pinctrl_slave_rk806: pinctrl_slave_rk806 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_slave_dvs1_null: rk806_slave_dvs1_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs1_slp: rk806_slave_dvs1_slp {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs1_rst: rk806_slave_dvs1_rst {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs2_null: rk806_slave_dvs2_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs2_slp: rk806_slave_dvs2_slp {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs2_rst: rk806_slave_dvs2_rst {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_slave_dvs3_null: rk806_slave_dvs3_null {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs3_slp: rk806_slave_dvs3_slp {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs3_rst: rk806_slave_dvs3_rst {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+ };
+
+ regulators {
+ vdd_cpu_big1_s0: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big0_s0: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_mem_s0: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big1_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+
+ vdd_cpu_big0_mem_s0: DCDC_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big0_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: DCDC_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_mem_s0: DCDC_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddq_ddr_s0: DCDC_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: DCDC_REG10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_cam_s0: PLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd1v8_ddr_pll_s0: PLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd1v8_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_1v8_pll_s0: PLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_1v8_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_sd_s0: PLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_2v8_cam_s0: PLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_2v8_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: PLDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_pll_s0: NLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_0v75_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_pll_s0: NLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v85_s0: NLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_cam_s0: NLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_1v2_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_s0: NLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi (revision 151)
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
+
+ rk806single: rk806single@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default", "pmic-power-off";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-1 = <&rk806_dvs1_pwrdn>;
+
+ /* 2800mv-3500mv */
+ low_voltage_threshold = <3000>;
+ /* 2700mv-3400mv */
+ shutdown_voltage_threshold = <2700>;
+ /* 140 160 */
+ shutdown_temperture_threshold = <160>;
+ hotdie_temperture_threshold = <115>;
+
+ /* 0: restart PMU;
+ * 1: reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode;
+ * 2: Reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode,
+ * and simultaneously pull down the RESETB PIN for 5mS before releasing
+ */
+ pmic-reset-func = <1>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ pwrkey {
+ status = "okay";
+ };
+
+ pinctrl_rk806: pinctrl_rk806 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: rk806_dvs1_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: rk806_dvs1_slp {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: rk806_dvs1_rst {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_null: rk806_dvs2_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_slp: rk806_dvs2_slp {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: rk806_dvs2_rst {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: rk806_dvs2_dvs {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: rk806_dvs2_gpio {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_null: rk806_dvs3_null {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_slp: rk806_dvs3_slp {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: rk806_dvs3_rst {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: rk806_dvs3_dvs {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: rk806_dvs3_gpio {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: DCDC_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: DCDC_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: DCDC_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: DCDC_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: DCDC_REG10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: PLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: PLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: PLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: PLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: PLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: PLDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: NLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: NLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: NLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+ regulator-name = "avdd_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: NLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: NLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588-vccio3-pinctrl.dtsi (revision 151)
@@ -0,0 +1,516 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ clk32k {
+ /omit-if-no-ref/
+ clk32k_out1: clk32k-out1 {
+ rockchip,pins =
+ /* clk32k_out1 */
+ <2 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ };
+
+ eth0 {
+ /omit-if-no-ref/
+ eth0_pins: eth0-pins {
+ rockchip,pins =
+ /* eth0_refclko_25m */
+ <2 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspim1_pins: fspim1-pins {
+ rockchip,pins =
+ /* fspi_clk_m1 */
+ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_cs0n_m1 */
+ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d0_m1 */
+ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d1_m1 */
+ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d2_m1 */
+ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d3_m1 */
+ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim1_cs1: fspim1-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n_m1 */
+ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+
+ gmac0 {
+ /omit-if-no-ref/
+ gmac0_miim: gmac0-miim {
+ rockchip,pins =
+ /* gmac0_mdc */
+ <4 RK_PC4 1 &pcfg_pull_none>,
+ /* gmac0_mdio */
+ <4 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_clkinout: gmac0-clkinout {
+ rockchip,pins =
+ /* gmac0_mclkinout */
+ <4 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rx_bus2: gmac0-rx-bus2 {
+ rockchip,pins =
+ /* gmac0_rxd0 */
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ /* gmac0_rxd1 */
+ <2 RK_PC2 1 &pcfg_pull_none>,
+ /* gmac0_rxdv_crs */
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_tx_bus2: gmac0-tx-bus2 {
+ rockchip,pins =
+ /* gmac0_txd0 */
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ /* gmac0_txd1 */
+ <2 RK_PB7 1 &pcfg_pull_none>,
+ /* gmac0_txen */
+ <2 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_clk: gmac0-rgmii-clk {
+ rockchip,pins =
+ /* gmac0_rxclk */
+ <2 RK_PB0 1 &pcfg_pull_none>,
+ /* gmac0_txclk */
+ <2 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_bus: gmac0-rgmii-bus {
+ rockchip,pins =
+ /* gmac0_rxd2 */
+ <2 RK_PA6 1 &pcfg_pull_none>,
+ /* gmac0_rxd3 */
+ <2 RK_PA7 1 &pcfg_pull_none>,
+ /* gmac0_txd2 */
+ <2 RK_PB1 1 &pcfg_pull_none>,
+ /* gmac0_txd3 */
+ <2 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_ppsclk: gmac0-ppsclk {
+ rockchip,pins =
+ /* gmac0_ppsclk */
+ <2 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_ppstring: gmac0-ppstring {
+ rockchip,pins =
+ /* gmac0_ppstring */
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_ptp_refclk: gmac0-ptp-refclk {
+ rockchip,pins =
+ /* gmac0_ptp_refclk */
+ <2 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_txer: gmac0-txer {
+ rockchip,pins =
+ /* gmac0_txer */
+ <4 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ };
+
+ hdmi {
+ /omit-if-no-ref/
+ hdmim0_tx1_cec: hdmim0-tx1-cec {
+ rockchip,pins =
+ /* hdmim0_tx1_cec */
+ <2 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx1_scl: hdmim0-tx1-scl {
+ rockchip,pins =
+ /* hdmim0_tx1_scl */
+ <2 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx1_sda: hdmim0-tx1-sda {
+ rockchip,pins =
+ /* hdmim0_tx1_sda */
+ <2 RK_PB4 4 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <4 RK_PC5 9 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <4 RK_PC6 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <2 RK_PC1 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <2 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m3_xfer: i2c3m3-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m3 */
+ <2 RK_PB2 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m3 */
+ <2 RK_PB3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <2 RK_PB5 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m1 */
+ <2 RK_PB4 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m4_xfer: i2c5m4-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m4 */
+ <2 RK_PB6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m4 */
+ <2 RK_PB7 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m2_xfer: i2c6m2-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m2 */
+ <2 RK_PC3 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m2 */
+ <2 RK_PC2 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7m1_xfer: i2c7m1-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m1 */
+ <4 RK_PC3 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m1 */
+ <4 RK_PC4 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c8 {
+ /omit-if-no-ref/
+ i2c8m1_xfer: i2c8m1-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m1 */
+ <2 RK_PB0 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m1 */
+ <2 RK_PB1 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m0_lrck: i2s2m0-lrck {
+ rockchip,pins =
+ /* i2s2m0_lrck */
+ <2 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2m0_mclk */
+ <2 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins =
+ /* i2s2m0_sclk */
+ <2 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2m0_sdi */
+ <2 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2m0_sdo */
+ <4 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m2_pins: pwm2m2-pins {
+ rockchip,pins =
+ /* pwm2_m2 */
+ <4 RK_PC2 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <4 RK_PC3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m2_pins: pwm5m2-pins {
+ rockchip,pins =
+ /* pwm5_m2 */
+ <4 RK_PC4 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m2_pins: pwm6m2-pins {
+ rockchip,pins =
+ /* pwm6_m2 */
+ <4 RK_PC5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m3_pins: pwm7m3-pins {
+ rockchip,pins =
+ /* pwm7_ir_m3 */
+ <4 RK_PC6 11 &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ /omit-if-no-ref/
+ sdiom0_pins: sdiom0-pins {
+ rockchip,pins =
+ /* sdio_clk_m0 */
+ <2 RK_PB3 2 &pcfg_pull_none>,
+ /* sdio_cmd_m0 */
+ <2 RK_PB2 2 &pcfg_pull_up>,
+ /* sdio_d0_m0 */
+ <2 RK_PA6 2 &pcfg_pull_up>,
+ /* sdio_d1_m0 */
+ <2 RK_PA7 2 &pcfg_pull_up>,
+ /* sdio_d2_m0 */
+ <2 RK_PB0 2 &pcfg_pull_up>,
+ /* sdio_d3_m0 */
+ <2 RK_PB1 2 &pcfg_pull_up>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clk_m0 */
+ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_miso_m0 */
+ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosi_m0 */
+ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs0: spi1m0-cs0 {
+ rockchip,pins =
+ /* spi1_cs0_m0 */
+ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs1: spi1m0-cs1 {
+ rockchip,pins =
+ /* spi1_cs1_m0 */
+ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m0_pins: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clk_m0 */
+ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_miso_m0 */
+ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosi_m0 */
+ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs0: spi3m0-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m0 */
+ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs1: spi3m0-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m0 */
+ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <2 RK_PB6 10 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <2 RK_PB7 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <2 RK_PC1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <2 RK_PC0 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <2 RK_PA6 10 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <2 RK_PA7 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <2 RK_PB1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <2 RK_PB0 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <2 RK_PB4 10 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <2 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <4 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <4 RK_PC2 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rx_m0 */
+ <2 RK_PC4 10 &pcfg_pull_up>,
+ /* uart9_tx_m0 */
+ <2 RK_PC2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <4 RK_PC5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <4 RK_PC4 10 &pcfg_pull_none>;
+ };
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588.dtsi (revision 151)
@@ -0,0 +1,966 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/phy/phy-snps-pcie3.h>
+#include "rk3588s.dtsi"
+#include "rk3588-vccio3-pinctrl.dtsi"
+
+/ {
+ aliases {
+ csi2dphy3 = &csi2_dphy3;
+ csi2dphy4 = &csi2_dphy4;
+ csi2dphy5 = &csi2_dphy5;
+ dp0 = &dp0;
+ dp1 = &dp1;
+ edp0 = &edp0;
+ edp1 = &edp1;
+ ethernet0 = &gmac0;
+ hdptx0 = &hdptxphy0;
+ hdptx1 = &hdptxphy1;
+ hdptxhdmi0 = &hdptxphy_hdmi0;
+ hdptxhdmi1 = &hdptxphy_hdmi1;
+ hdmi0 = &hdmi0;
+ hdmi1 = &hdmi1;
+ rkcif_mipi_lvds4= &rkcif_mipi_lvds4;
+ rkcif_mipi_lvds5= &rkcif_mipi_lvds5;
+ usbdp0 = &usbdp_phy0;
+ usbdp1 = &usbdp_phy1;
+ };
+
+ /* dphy1 full mode */
+ csi2_dphy3: csi2-dphy3 {
+ compatible = "rockchip,rk3568-csi2-dphy";
+ rockchip,hw = <&csi2_dphy1_hw>;
+ status = "disabled";
+ };
+
+ /* dphy1 split mode 01 */
+ csi2_dphy4: csi2-dphy4 {
+ compatible = "rockchip,rk3568-csi2-dphy";
+ rockchip,hw = <&csi2_dphy1_hw>;
+ status = "disabled";
+ };
+
+ /* dphy1 split mode 23 */
+ csi2_dphy5: csi2-dphy5 {
+ compatible = "rockchip,rk3568-csi2-dphy";
+ rockchip,hw = <&csi2_dphy1_hw>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds4>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds4>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds4>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds4>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds5: rkcif-mipi-lvds5 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds5_sditf: rkcif-mipi-lvds5-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds5>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds5_sditf_vir1: rkcif-mipi-lvds5-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds5>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds5_sditf_vir2: rkcif-mipi-lvds5-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds5>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds5_sditf_vir3: rkcif-mipi-lvds5-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds5>;
+ status = "disabled";
+ };
+
+ usbdrd3_1: usbdrd3_1 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref", "suspend", "bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_1: usb@fc400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ reset-names = "usb3-otg";
+ dr_mode = "host";
+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
+ };
+ };
+
+ pcie30_phy_grf: syscon@fd5b8000 {
+ compatible = "rockchip,pcie30-phy-grf", "syscon";
+ reg = <0x0 0xfd5b8000 0x0 0x10000>;
+ };
+
+ pipe_phy1_grf: syscon@fd5c0000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c0000 0x0 0x100>;
+ };
+
+ usbdpphy1_grf: syscon@fd5cc000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2-phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ rockchip,usbctrl-grf = <&usb_grf>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ hdptxphy1_grf: syscon@fd5e4000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e4000 0x0 0x100>;
+ };
+
+ mipi4_csi2: mipi4-csi2@fdd50000 {
+ compatible = "rockchip,rk3588-mipi-csi2";
+ reg = <0x0 0xfdd50000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSI_HOST_4>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSI_HOST_4>, <&cru SRST_CSIHOST4_VICAP>;
+ reset-names = "srst_csihost_p", "srst_csihost_vicap";
+ status = "disabled";
+ };
+
+ mipi5_csi2: mipi5-csi2@fdd60000 {
+ compatible = "rockchip,rk3588-mipi-csi2";
+ reg = <0x0 0xfdd60000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSI_HOST_5>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSI_HOST_5>, <&cru SRST_CSIHOST5_VICAP>;
+ reset-names = "srst_csihost_p", "srst_csihost_vicap";
+ status = "disabled";
+ };
+
+ spdif_tx5: spdif-tx@fddb8000 {
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xfddb8000 0x0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac1 22>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
+ assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ power-domains = <&power RK3588_PD_VO0>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s8_8ch: i2s@fddc8000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddc8000 0x0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
+ clock-names = "mclk_tx", "hclk";
+ assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 22>;
+ dma-names = "tx";
+ power-domains = <&power RK3588_PD_VO0>;
+ resets = <&cru SRST_M_I2S8_8CH_TX>;
+ reset-names = "tx-m";
+ rockchip,playback-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_tx4: spdif-tx@fdde8000 {
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xfdde8000 0x0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac1 8>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
+ assigned-clocks = <&cru CLK_SPDIF4_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ power-domains = <&power RK3588_PD_VO1>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s6_8ch: i2s@fddf4000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddf4000 0x0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 4>;
+ dma-names = "tx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S6_8CH_TX>;
+ reset-names = "tx-m";
+ rockchip,always-on;
+ rockchip,hdmi-path;
+ rockchip,playback-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s7_8ch: i2s@fddf8000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddf8000 0x0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 21>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S7_8CH_RX>;
+ reset-names = "rx-m";
+ rockchip,capture-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s10_8ch: i2s@fde00000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfde00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 24>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S10_8CH_RX>;
+ reset-names = "rx-m";
+ rockchip,capture-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_rx1: spdif-rx@fde10000 {
+ compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
+ reg = <0x0 0xfde10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>;
+ clock-names = "mclk", "hclk";
+ assigned-clocks = <&cru MCLK_SPDIFRX1>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac0 22>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_SPDIFRX1>;
+ reset-names = "spdifrx-m";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_rx2: spdif-rx@fde18000 {
+ compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
+ reg = <0x0 0xfde18000 0x0 0x1000>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>;
+ clock-names = "mclk", "hclk";
+ assigned-clocks = <&cru MCLK_SPDIFRX2>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac0 23>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_SPDIFRX2>;
+ reset-names = "spdifrx-m";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ dp1: dp@fde60000 {
+ compatible = "rockchip,rk3588-dp";
+ reg = <0x0 0xfde60000 0x0 0x4000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>,
+ <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_SPDIF5_DP1>,
+ <&hclk_vo0>;
+ clock-names = "apb", "aux", "i2s", "spdif", "hclk";
+ assigned-clocks = <&cru CLK_AUX16M_1>;
+ assigned-clock-rates = <16000000>;
+ resets = <&cru SRST_DP1>;
+ phys = <&usbdp_phy1_dp>;
+ power-domains = <&power RK3588_PD_VO0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp1_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp1_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_dp1>;
+ status = "disabled";
+ };
+
+ dp1_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_dp1>;
+ status = "disabled";
+ };
+
+ dp1_in_vp2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp2_out_dp1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ hdmi1: hdmi@fdea0000 {
+ compatible = "rockchip,rk3588-dw-hdmi";
+ reg = <0x0 0xfdea0000 0x0 0x20000>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMITX1>,
+ <&cru CLK_HDMIHDP1>,
+ <&cru CLK_HDMITX1_EARC>,
+ <&cru CLK_HDMITX1_REF>,
+ <&cru MCLK_I2S6_8CH_TX>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&hclk_vo1>,
+ <&hdptxphy_hdmi_clk1>;
+ clock-names = "pclk",
+ "hpd",
+ "earc",
+ "hdmitx_ref",
+ "aud",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "hclk_vo1",
+ "link_clk";
+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
+ reset-names = "ref", "hdp";
+ power-domains = <&power RK3588_PD_VO1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ reg-io-width = <4>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1_grf = <&vo1_grf>;
+ phys = <&hdptxphy_hdmi1>;
+ phy-names = "hdmi";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi1_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi1_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_hdmi1>;
+ status = "disabled";
+ };
+
+ hdmi1_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_hdmi1>;
+ status = "disabled";
+ };
+
+ hdmi1_in_vp2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp2_out_hdmi1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ edp1: edp@fded0000 {
+ compatible = "rockchip,rk3588-edp";
+ reg = <0x0 0xfded0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>,
+ <&cru CLK_EDP1_200M>, <&hclk_vo1>;
+ clock-names = "dp", "pclk", "spdif", "hclk";
+ resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
+ reset-names = "dp", "apb";
+ phys = <&hdptxphy1>;
+ phy-names = "dp";
+ power-domains = <&power RK3588_PD_VO1>;
+ rockchip,grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp1_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp1_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_edp1>;
+ status = "disabled";
+ };
+
+ edp1_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_edp1>;
+ status = "disabled";
+ };
+
+ edp1_in_vp2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp2_out_edp1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ hdmirx_ctrler: hdmirx-controller@fdee0000 {
+ compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler";
+ reg = <0x0 0xfdee0000 0x0 0x6000>;
+ reg-names = "hdmirx_regs";
+ power-domains = <&power RK3588_PD_VO1>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1_grf = <&vo1_grf>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cec", "hdmi", "dma";
+ clocks = <&cru ACLK_HDMIRX>,
+ <&cru CLK_HDMIRX_AUD>,
+ <&cru CLK_CR_PARA>,
+ <&cru PCLK_HDMIRX>,
+ <&cru CLK_HDMIRX_REF>,
+ <&cru PCLK_S_HDMIRX>,
+ <&hclk_vo1>;
+ clock-names = "aclk",
+ "audio",
+ "cr_para",
+ "pclk",
+ "ref",
+ "hclk_s_hdmirx",
+ "hclk_vo1";
+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
+ reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu";
+ pinctrl-0 = <&hdmim1_rx>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ pcie3x4: pcie@fe150000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0x0f>;
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+ <0 0 0 2 &pcie3x4_intc 1>,
+ <0 0 0 3 &pcie3x4_intc 2>,
+ <0 0 0 4 &pcie3x4_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ num-viewport = <8>;
+ max-link-speed = <3>;
+ msi-map = <0x0000 &its1 0x0000 0x1000>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
+ 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
+ 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000
+ 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe150000 0x0 0x10000>,
+ <0xa 0x40000000 0x0 0x400000>;
+ reg-names = "pcie-apb", "pcie-dbi";
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+
+ pcie3x4_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie3x2: pcie@fe160000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x10 0x1f>;
+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+ <0 0 0 2 &pcie3x2_intc 1>,
+ <0 0 0 3 &pcie3x2_intc 2>,
+ <0 0 0 4 &pcie3x2_intc 3>;
+ linux,pci-domain = <1>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ num-viewport = <8>;
+ max-link-speed = <3>;
+ msi-map = <0x1000 &its1 0x1000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000
+ 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000
+ 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000
+ 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+ reg = <0x0 0xfe160000 0x0 0x10000>,
+ <0xa 0x40400000 0x0 0x400000>;
+ reg-names = "pcie-apb", "pcie-dbi";
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+
+ pcie3x2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie2x1l0: pcie@fe170000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
+ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
+ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
+ <0 0 0 2 &pcie2x1l0_intc 1>,
+ <0 0 0 3 &pcie2x1l0_intc 2>,
+ <0 0 0 4 &pcie2x1l0_intc 3>;
+ linux,pci-domain = <2>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ msi-map = <0x2000 &its0 0x2000 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy1_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
+ 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
+ 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000
+ 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0xfe170000 0x0 0x10000>,
+ <0xa 0x40800000 0x0 0x400000>;
+ reg-names = "pcie-apb", "pcie-dbi";
+ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+
+ pcie2x1l0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ gmac0: ethernet@fe1b0000 {
+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe1b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&sys_grf>;
+ rockchip,php_grf = <&php_grf>;
+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
+ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
+ <&cru CLK_GMAC0_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ resets = <&cru SRST_A_GMAC0>;
+ reset-names = "stmmaceth";
+ power-domains = <&power RK3588_PD_GMAC>;
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+ };
+
+ sata1: sata@fe220000 {
+ compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe220000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy1_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ status = "disabled";
+ };
+
+ hdptxphy1: phy@fed70000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed70000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+ clock-names = "ref", "apb";
+ resets = <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>,
+ <&cru SRST_HDPTX1_CMN>, <&cru SRST_HDPTX1_LANE>;
+ reset-names = "apb", "init", "cmn", "lane";
+ rockchip,grf = <&hdptxphy1_grf>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hdptxphy_hdmi1: hdmiphy@fed70000 {
+ compatible = "rockchip,rk3588-hdptx-phy-hdmi";
+ reg = <0x0 0xfed70000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+ clock-names = "ref", "apb";
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
+ <&cru SRST_HDPTX1_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy1_grf>;
+ #phy-cells = <0>;
+ status = "disabled";
+
+ hdptxphy_hdmi_clk1: clk-port {
+ #clock-cells = <0>;
+ status = "okay";
+ };
+ };
+
+
+ usbdp_phy1: phy@fed90000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed90000 0x0 0x10000>;
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
+ <&cru PCLK_USBDPPHY1>,
+ <&u2phy1>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+ <&cru SRST_P_USBDPPHY1>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ status = "disabled";
+
+ usbdp_phy1_dp: dp-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbdp_phy1_u3: u3-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 {
+ compatible = "rockchip,rk3588-csi2-dphy-hw";
+ reg = <0x0 0xfedc8000 0x0 0x8000>;
+ clocks = <&cru PCLK_CSIPHY1>;
+ clock-names = "pclk";
+ resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>;
+ reset-names = "srst_csiphy1", "srst_p_csiphy1";
+ rockchip,grf = <&mipidphy1_grf>;
+ rockchip,sys_grf = <&sys_grf>;
+ status = "disabled";
+ };
+
+ combphy1_ps: phy@fee10000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee10000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "refclk", "apbclk", "phpclk";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
+ status = "disabled";
+ };
+
+ pcie30phy: phy@fee80000 {
+ compatible = "rockchip,rk3588-pcie3-phy";
+ reg = <0x0 0xfee80000 0x0 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+ clock-names = "pclk";
+ resets = <&cru SRST_PCIE30_PHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ status = "disabled";
+ };
+
+};
+
+&display_subsystem {
+ route {
+ route_dp1: route-dp1 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp1_out_dp1>;
+ };
+
+ route_hdmi1: route-hdmi1 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp1_out_hdmi1>;
+ };
+ };
+};
+
+&vp0 {
+ vp0_out_dp1: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dp1_in_vp0>;
+ };
+
+ vp0_out_edp1: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&edp1_in_vp0>;
+ };
+
+ vp0_out_hdmi1: endpoint@5 {
+ reg = <5>;
+ remote-endpoint = <&hdmi1_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_dp1: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dp1_in_vp1>;
+ };
+
+ vp1_out_edp1: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&edp1_in_vp1>;
+ };
+
+ vp1_out_hdmi1: endpoint@5 {
+ reg = <5>;
+ remote-endpoint = <&hdmi1_in_vp1>;
+ };
+};
+
+&vp2 {
+ vp2_out_dp1: endpoint@5 {
+ reg = <5>;
+ remote-endpoint = <&dp1_in_vp2>;
+ };
+
+ vp2_out_edp1: endpoint@6 {
+ reg = <6>;
+ remote-endpoint = <&edp1_in_vp2>;
+ };
+
+ vp2_out_hdmi1: endpoint@7 {
+ reg = <7>;
+ remote-endpoint = <&hdmi1_in_vp2>;
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588m.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588m.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588m.dtsi (revision 151)
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "rk3588.dtsi"
+
+&cluster0_opp_table {
+ /delete-node/ opp-1800000000;
+
+ opp-1704000000 {
+ opp-supported-hw = <0x02 0xffff>;
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <900000 900000 950000>,
+ <900000 900000 950000>;
+ opp-microvolt-L1 = <887500 887500 950000>,
+ <887500 887500 950000>;
+ opp-microvolt-L2 = <875000 875000 950000>,
+ <875000 875000 950000>;
+ opp-microvolt-L3 = <862500 862500 950000>,
+ <862500 862500 950000>;
+ opp-microvolt-L4 = <850000 850000 950000>,
+ <850000 850000 950000>;
+ opp-microvolt-L5 = <837500 837500 950000>,
+ <837500 837500 950000>;
+ opp-microvolt-L6 = <825000 825000 950000>,
+ <825000 825000 950000>;
+ clock-latency-ns = <40000>;
+ };
+};
+
+&cluster1_opp_table {
+ /delete-node/ opp-2208000000;
+ /delete-node/ opp-2256000000;
+ /delete-node/ opp-2304000000;
+ /delete-node/ opp-2352000000;
+ /delete-node/ opp-2400000000;
+};
+
+&cluster2_opp_table {
+ /delete-node/ opp-2208000000;
+ /delete-node/ opp-2256000000;
+ /delete-node/ opp-2304000000;
+ /delete-node/ opp-2352000000;
+ /delete-node/ opp-2400000000;
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi (revision 151)
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+&csi2_dphy0_hw {
+ status = "disabled";
+};
+
+&csi2_dphy0 {
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_ucam0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ov13850_out2>;
+ data-lanes = <1 2>;
+ };
+
+ mipi_in_ucam1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ov13855_out2>;
+ data-lanes = <1 2>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ csidphy0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi2_csi2_input>;
+ };
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7m0_xfer>;
+
+ vm149c_p1: vm149c-p1@c {
+ compatible = "silicon touch,vm149c";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "back";
+ };
+
+ ov13850_1: ov13850-1@10 {
+ compatible = "ovti,ov13850";
+ status = "disabled";
+ reg = <0x10>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim0_camera3_clk>;
+ reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CMK-CT0116";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&vm149c_p1>;
+ port {
+ ov13850_out2: endpoint {
+ remote-endpoint = <&mipi_in_ucam0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ dw9714_p1: dw9714-p1@c {
+ compatible = "dongwoon,dw9714";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <0>;
+ rockchip,vcm-start-current = <10>;
+ rockchip,vcm-rated-current = <85>;
+ rockchip,vcm-step-mode = <5>;
+ rockchip,camera-module-facing = "back";
+ };
+
+ ov13855_1: ov13855-1@36 {
+ compatible = "ovti,ov13855";
+ status = "disabled";
+ reg = <0x36>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim0_camera3_clk>;
+ reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CMK-OT2016-FV1";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&dw9714_p1>;
+ port {
+ ov13855_out2: endpoint {
+ remote-endpoint = <&mipi_in_ucam1>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&mipi2_csi2 {
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi2_csi2_input: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csidphy0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi2_csi2_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&cif_mipi_in2>;
+ };
+ };
+ };
+};
+
+&rkcif_mipi_lvds2 {
+ status = "disabled";
+ port {
+ cif_mipi_in2: endpoint {
+ remote-endpoint = <&mipi2_csi2_output>;
+ };
+ };
+};
+
+&rkcif_mipi_lvds2_sditf {
+ status = "disabled";
+ port {
+ mipi2_lvds_sditf: endpoint {
+ remote-endpoint = <&isp0_vir1>;
+ };
+ };
+};
+
+&rkisp0_vir1 {
+ status = "disabled";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ isp0_vir1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi2_lvds_sditf>;
+ };
+ };
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera1.dtsi
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi (revision 151)
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+&csi2_dcphy0 {
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_cam0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ov13850_out>;
+ data-lanes = <1 2>;
+ };
+
+ mipi_in_cam1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ov13855_out>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csidcphy0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi0_csi2_input>;
+ };
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7m0_xfer>;
+
+ vm149c_p2: vm149c-p2@c {
+ compatible = "silicon touch,vm149c";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "back";
+ };
+
+ ov13850_2: ov13850-2@10 {
+ compatible = "ovti,ov13850";
+ status = "disabled";
+ reg = <0x10>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
+ clock-names = "xvclk";
+ power-domains = <&power RK3588_PD_VI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim0_camera4_clk>;
+ rockchip,grf = <&sys_grf>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CMK-CT0116";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&vm149c_p2>;
+ port {
+ ov13850_out: endpoint {
+ remote-endpoint = <&mipi_in_cam0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ dw9714_p2: dw9714-p2@c {
+ compatible = "dongwoon,dw9714";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <0>;
+ rockchip,vcm-start-current = <10>;
+ rockchip,vcm-rated-current = <85>;
+ rockchip,vcm-step-mode = <5>;
+ rockchip,camera-module-facing = "back";
+ };
+
+ ov13855_2: ov13855-2@36 {
+ compatible = "ovti,ov13855";
+ status = "disabled";
+ reg = <0x36>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
+ clock-names = "xvclk";
+ power-domains = <&power RK3588_PD_VI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim0_camera4_clk>;
+ rockchip,grf = <&sys_grf>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <0>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CMK-OT2016-FV1";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&dw9714_p2>;
+ port {
+ ov13855_out: endpoint {
+ remote-endpoint = <&mipi_in_cam1>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&mipi0_csi2 {
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi0_csi2_input: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csidcphy0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi0_csi2_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&cif_mipi_in0>;
+ };
+ };
+ };
+};
+
+&rkcif_mipi_lvds {
+ status = "disabled";
+
+ port {
+ cif_mipi_in0: endpoint {
+ remote-endpoint = <&mipi0_csi2_output>;
+ };
+ };
+};
+
+&rkcif_mipi_lvds_sditf {
+ status = "disabled";
+
+ port {
+ mipi_lvds_sditf: endpoint {
+ remote-endpoint = <&isp1_in1>;
+ };
+ };
+};
+
+&rkisp0_vir0 {
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ isp1_in1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_sditf>;
+ };
+ };
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera2.dtsi
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi (revision 151)
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+&csi2_dcphy1 {
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_dcphy0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ov13850_out1>;
+ data-lanes = <1 2>;
+ };
+
+ mipi_in_dcphy1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ov13855_out1>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csidcphy1_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi1_csi2_input>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vm149cp1: vm149c@c {
+ compatible = "silicon touch,vm149c";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "front";
+ };
+
+ ov13850_3: ov13850@10 {
+ compatible = "ovti,ov13850";
+ status = "disabled";
+ reg = <0x10>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim0_camera4_clk>;
+ rockchip,grf = <&sys_grf>;
+ reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "front";
+ rockchip,camera-module-name = "CMK-CT0116";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&vm149cp1>;
+ port {
+ ov13850_out1: endpoint {
+ remote-endpoint = <&mipi_in_dcphy0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ dw9714: dw9714@c {
+ compatible = "dongwoon,dw9714";
+ status = "disabled";
+ reg = <0x0c>;
+ rockchip,camera-module-index = <0>;
+ rockchip,vcm-start-current = <10>;
+ rockchip,vcm-rated-current = <85>;
+ rockchip,vcm-step-mode = <5>;
+ rockchip,camera-module-facing = "front";
+ };
+
+ ov13855_3: ov13855@36 {
+ compatible = "ovti,ov13855";
+ status = "disabled";
+ reg = <0x36>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim0_camera4_clk>;
+ rockchip,grf = <&sys_grf>;
+ reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "front";
+ rockchip,camera-module-name = "CMK-OT2016-FV1";
+ rockchip,camera-module-lens-name = "default";
+ lens-focus = <&dw9714>;
+ port {
+ ov13855_out1: endpoint {
+ remote-endpoint = <&mipi_in_dcphy1>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&mipi1_csi2 {
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi1_csi2_input: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csidcphy1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi1_csi2_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&cif_mipi_in1>;
+ };
+ };
+ };
+};
+
+&rkcif_mipi_lvds1 {
+ status = "disabled";
+
+ port {
+ cif_mipi_in1: endpoint {
+ remote-endpoint = <&mipi1_csi2_output>;
+ };
+ };
+};
+
+&rkcif_mipi_lvds1_sditf {
+ status = "disabled";
+
+ port {
+ mipi1_lvds_sditf: endpoint {
+ remote-endpoint = <&isp1_in0>;
+ };
+ };
+};
+
+&rkisp1_vir0 {
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ isp1_in0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi1_lvds_sditf>;
+ };
+ };
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-camera3.dtsi
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-lcd.dtsi (revision 151)
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&dsi0 {
+ status = "disabled";
+};
+
+&dsi0_panel {
+ status = "disabled";
+ reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd0_rst_gpio>;
+};
+
+&dsi0_in_vp2 {
+ status = "disabled";
+};
+
+&dsi0_in_vp3 {
+ status = "disabled";
+};
+
+&route_dsi0 {
+ status = "disabled";
+ connect = <&vp3_out_dsi0>;
+};
+
+&mipi_dcphy0 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7m0_xfer>;
+
+ gt9xx_1: touchscreen@14 {
+ compatible = "goodix,gt9271";
+ reg = <0x14>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+ touchscreen-inverted-x;
+ //touchscreen-inverted-y;
+ touchscreen-swapped-x-y;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ status = "okay";
+ };
+};
+
+
+
+&dsi1 {
+ status = "disabled";
+};
+
+&dsi1_panel {
+ status = "disabled";
+ reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd1_rst_gpio>;
+};
+
+&dsi1_in_vp2 {
+ status = "disabled";
+};
+
+&dsi1_in_vp3 {
+ status = "disabled";
+};
+
+&route_dsi1 {
+ status = "disabled";
+ connect = <&vp3_out_dsi1>;
+};
+
+&mipi_dcphy1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ gt9xx_0: touchscreen@14 {
+ compatible = "goodix,gt9271";
+ reg = <0x14>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio1 RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ touchscreen-inverted-x;
+ //touchscreen-inverted-y;
+ touchscreen-swapped-x-y;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ status = "okay";
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts (revision 151)
@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588s-orangepi-5.dtsi"
+#include "rk3588-linux.dtsi"
+#include "rk3588s-orangepi-5-lcd.dtsi"
+
+#include "rk3588s-orangepi-5-camera1.dtsi"
+#include "rk3588s-orangepi-5-camera2.dtsi"
+#include "rk3588s-orangepi-5-camera3.dtsi"
+
+/ {
+ model = "Orange Pi 5";
+ compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
+
+ vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
+ enable-active-low;
+ vin-supply = <&vcc_3v3_s3>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "okay";
+
+ led@1 {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ /* Use rgmii-rxid mode to disable rx delay inside Soc */
+ phy-mode = "rgmii-rxid";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+
+ tx_delay = <0x42>;
+ /* rx_delay = <0x3f>; */
+
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&hdmi0 {
+ enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ cec-enable;
+ status = "okay";
+};
+
+&hdmi0_in_vp0 {
+ status = "okay";
+};
+
+&hdmi0_sound {
+ status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&route_hdmi0{
+ status = "okay";
+};
+
+&i2s5_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ status = "okay";
+ rockchip,i2s-tx-route = <3 2 1 0>;
+ rockchip,i2s-rx-route = <1 3 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclk
+ &i2s1m0_lrck
+ &i2s1m0_sdi1
+ &i2s1m0_sdo3>;
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+
+ vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
+ compatible = "rockchip,rk8603";
+ reg = <0x43>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_npu_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+/*
+ pin3: GPIO1_B7
+ pin5: GPIO1_B6
+*/
+&i2c5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m3_xfer>;
+};
+
+&uart1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m1_xfer>;
+};
+
+&pwm13 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m2_pins>;
+};
+
+/*
+ pin7: GPIO1_C6
+*/
+&pwm15 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm15m2_pins>;
+};
+
+/*
+ pin11: GPIO4_B2
+ pin13: GPIO4_B3
+*/
+&pwm14 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm14m1_pins>;
+};
+
+&can1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1m1_pins>;
+ assigned-clocks = <&cru CLK_CAN1>;
+ assigned-clock-rates = <200000000>;
+};
+
+/*
+ pin15: GPIO0_D4
+ pin12: GPIO0_D5
+*/
+&can2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can2m1_pins>;
+ assigned-clocks = <&cru CLK_CAN2>;
+ assigned-clock-rates = <200000000>;
+};
+
+/*
+ pin19: GPIO1_C1
+ pin21: GPIO1_C0
+ pin23: GPIO1_C2
+ pin24: GPIO1_C4
+*/
+&spi4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
+ assigned-clocks = <&cru CLK_SPI4>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+
+ spi_dev@1 {
+ compatible = "rockchip,spidev";
+ reg = <1>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&i2c3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+};
+
+&uart3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+};
+
+&pwm3 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m2_pins>;
+ //pinctrl-0 = <&pwm3m0_pins>;
+};
+
+/*
+ pin8: GPIO4_A3
+ pin10: GPIO4_A4
+*/
+&uart0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m2_xfer>;
+};
+
+/*
+ pin16: GPIO1_D3
+ pin18: GPIO1_D2
+*/
+&uart4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+};
+
+&i2c1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ //pinctrl-0 = <&i2c1m4_xfer>;
+ pinctrl-0 = <&i2c1m2_xfer>;
+};
+
+&pwm0 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0m1_pins>;
+};
+
+/*
+ pin26: GPIO1_A3
+*/
+&pwm1 {
+ status = "disabled";
+ pinctrl-names = "active";
+ //pinctrl-0 = <&pwm1m2_pins>;
+ pinctrl-0 = <&pwm1m1_pins>;
+};
+
+/* watchdog */
+&wdt {
+ status = "okay";
+};
+
+&sfc {
+ status = "okay";
+ max-freq = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim0_pins>;
+
+ spi_flash: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ loader@0 {
+ label = "loader";
+ reg = <0x0 0x1000000>;
+ };
+ };
+ };
+};
+
+&mipi_dcphy0 {
+ status = "okay";
+};
+
+&mipi_dcphy1 {
+ status = "okay";
+};
+
+&rkcif {
+ status = "okay";
+};
+
+&rkcif_mmu {
+ status = "okay";
+};
+
+&rkisp0 {
+ status = "okay";
+};
+
+&isp0_mmu {
+ status = "okay";
+};
+
+&rkisp1 {
+ status = "okay";
+};
+
+&isp1_mmu {
+ status = "okay";
+};
+
+&sata0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata_reset>;
+ status = "disabled";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
+ rockchip,skip-scan-in-resume;
+ status = "okay";
+};
+
+&pinctrl
+{
+ gpio-func {
+ leds_gpio: leds-gpio {
+ rockchip,pins =
+ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi (revision 151)
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "dt-bindings/usb/pd.h"
+#include "rk3588s.dtsi"
+#include "rk3588s-orangepi.dtsi"
+#include "rk3588-rk806-single.dtsi"
+
+/ {
+ combophy_avdd0v85: combophy-avdd0v85 {
+ compatible = "regulator-fixed";
+ regulator-name = "combophy_avdd0v85";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ combophy_avdd1v8: combophy-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "combophy_avdd1v8";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ es8388_sound: es8388-sound {
+ status = "okay";
+ compatible = "rockchip,multicodecs-card";
+ rockchip,card-name = "rockchip-es8388";
+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ io-channels = <&saradc 3>;
+ io-channel-names = "adc-detect";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+ rockchip,format = "i2s";
+ rockchip,mclk-fs = <256>;
+ rockchip,cpu = <&i2s1_8ch>;
+ rockchip,codec = <&es8388>;
+ rockchip,audio-routing =
+ "Headphone", "LOUT1",
+ "Headphone", "ROUT1",
+ "Headphone", "Headphone Power",
+ "Headphone", "Headphone Power",
+ "LINPUT1", "Main Mic",
+ "LINPUT2", "Main Mic",
+ "RINPUT1", "Headset Mic",
+ "RINPUT2", "Headset Mic";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ play-pause-key {
+ label = "playpause";
+ linux,code = <KEY_PLAYPAUSE>;
+ press-threshold-microvolt = <2000>;
+ };
+ };
+
+ wireless_bluetooth: wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>;
+ pinctrl-1 = <&uart9_gpios>;
+ BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ wireless_wlan: wireless-wlan {
+ compatible = "wlan-platdata";
+ wifi_chip_type = "ap6275p";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
+ WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_usb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ };
+};
+
+&pwm6 {
+ status = "okay";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6m0_pins>;
+};
+
+&pwm2 {
+ status = "okay";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2m0_pins>;
+};
+
+&backlight_1 {
+ pwms = <&pwm6 0 25000 0>;
+ status = "okay";
+};
+
+&backlight {
+ pwms = <&pwm2 0 25000 0>;
+ status = "okay";
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&dp0 {
+ status = "okay";
+};
+
+&dp0_in_vp1 {
+ status = "okay";
+};
+
+&dp0_in_vp2 {
+ status = "disabled";
+};
+
+&dp0_sound{
+ status = "okay";
+};
+
+&spdif_tx2{
+ status = "okay";
+};
+
+&mipi_dcphy0 {
+ status = "okay";
+};
+
+&mipi_dcphy1 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m3_xfer>;
+
+ es8388: es8388@10 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+ compatible = "everest,es8388", "everest,es8323";
+ reg = <0x10>;
+ clocks = <&cru I2S1_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_mclk>;
+ };
+
+ usbc0: fusb302@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus5v0_typec>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_role_sw: endpoint@0 {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+ };
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ altmodes {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ altmode@0 {
+ reg = <0>;
+ svid = <0xff01>;
+ vdo = <0xffffffff>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_orien_sw: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&pcie2x1l1 {
+ status = "disabled";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ rockchip,skip-scan-in-resume;
+ status = "disabled";
+};
+
+&pinctrl {
+ sata {
+ sata_reset:sata-reset{
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ lcd {
+ lcd0_rst_gpio: lcd0-rst-gpio {
+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ lcd1_rst_gpio: lcd1-rst-gpio {
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart9_gpios: uart9-gpios {
+ rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_gpio: bt-gpio {
+ rockchip,pins =
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wireless-wlan {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ wifi_poweren_gpio: wifi-poweren-gpio {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&u2phy0_otg {
+ rockchip,typec-vbus-det;
+ status = "okay";
+};
+
+&uart9 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
+};
+
+&usbdp_phy0 {
+ orientation-switch;
+ svid = <0xff01>;
+ sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+ };
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+ usb-role-switch;
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_0_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&usbhost3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbhost_dwc3_0 {
+ status = "okay";
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts (revision 151)
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588s-orangepi-5.dtsi"
+#include "rk3588-linux.dtsi"
+#include "rk3588s-orangepi-5-lcd.dtsi"
+
+#include "rk3588s-orangepi-5-camera1.dtsi"
+#include "rk3588s-orangepi-5-camera2.dtsi"
+#include "rk3588s-orangepi-5-camera3.dtsi"
+
+/ {
+ model = "Orange Pi 5";
+ compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
+
+ vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
+ enable-active-low;
+ vin-supply = <&vcc_3v3_s3>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "okay";
+
+ led@1 {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ /* Use rgmii-rxid mode to disable rx delay inside Soc */
+ phy-mode = "rgmii-rxid";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+
+ tx_delay = <0x42>;
+ /* rx_delay = <0x3f>; */
+
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&hdmi0 {
+ enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ cec-enable;
+ status = "okay";
+};
+
+&hdmi0_in_vp0 {
+ status = "okay";
+};
+
+&hdmi0_sound {
+ status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&route_hdmi0{
+ status = "okay";
+};
+
+&i2s5_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ status = "okay";
+ rockchip,i2s-tx-route = <3 2 1 0>;
+ rockchip,i2s-rx-route = <1 3 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclk
+ &i2s1m0_lrck
+ &i2s1m0_sdi1
+ &i2s1m0_sdo3>;
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+
+ vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
+ compatible = "rockchip,rk8603";
+ reg = <0x43>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "rk860x-reg";
+ regulator-name = "vdd_npu_s0";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ rockchip,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+/*
+ pin3: GPIO1_B7
+ pin5: GPIO1_B6
+*/
+&i2c5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m3_xfer>;
+};
+
+&uart1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m1_xfer>;
+};
+
+&pwm13 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m2_pins>;
+};
+
+/*
+ pin7: GPIO1_C6
+*/
+&pwm15 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm15m2_pins>;
+};
+
+/*
+ pin11: GPIO4_B2
+ pin13: GPIO4_B3
+*/
+&pwm14 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm14m1_pins>;
+};
+
+&can1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1m1_pins>;
+ assigned-clocks = <&cru CLK_CAN1>;
+ assigned-clock-rates = <200000000>;
+};
+
+/*
+ pin15: GPIO0_D4
+ pin12: GPIO0_D5
+*/
+&can2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can2m1_pins>;
+ assigned-clocks = <&cru CLK_CAN2>;
+ assigned-clock-rates = <200000000>;
+};
+
+/*
+ pin19: GPIO1_C1
+ pin21: GPIO1_C0
+ pin23: GPIO1_C2
+ pin24: GPIO1_C4
+*/
+&spi4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
+ assigned-clocks = <&cru CLK_SPI4>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+
+ spi_dev@1 {
+ compatible = "rockchip,spidev";
+ reg = <1>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&i2c3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+};
+
+&uart3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+};
+
+&pwm3 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m2_pins>;
+ //pinctrl-0 = <&pwm3m0_pins>;
+};
+
+/*
+ pin8: GPIO4_A3
+ pin10: GPIO4_A4
+*/
+&uart0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m2_xfer>;
+};
+
+/*
+ pin16: GPIO1_D3
+ pin18: GPIO1_D2
+*/
+&uart4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+};
+
+&i2c1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ //pinctrl-0 = <&i2c1m4_xfer>;
+ pinctrl-0 = <&i2c1m2_xfer>;
+};
+
+&pwm0 {
+ status = "disabled";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0m1_pins>;
+};
+
+/*
+ pin26: GPIO1_A3
+*/
+&pwm1 {
+ status = "disabled";
+ pinctrl-names = "active";
+ //pinctrl-0 = <&pwm1m2_pins>;
+ pinctrl-0 = <&pwm1m1_pins>;
+};
+
+/* watchdog */
+&wdt {
+ status = "okay";
+};
+
+&sfc {
+ status = "disabled";
+};
+
+&mipi_dcphy0 {
+ status = "okay";
+};
+
+&mipi_dcphy1 {
+ status = "okay";
+};
+
+&rkcif {
+ status = "okay";
+};
+
+&rkcif_mmu {
+ status = "okay";
+};
+
+&rkisp0 {
+ status = "okay";
+};
+
+&isp0_mmu {
+ status = "okay";
+};
+
+&rkisp1 {
+ status = "okay";
+};
+
+&isp1_mmu {
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ rockchip,skip-scan-in-resume;
+ status = "okay";
+};
+
+&wireless_bluetooth {
+ BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&wireless_wlan {
+ WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pinctrl
+{
+ wireless-bluetooth {
+ uart9_gpios: uart9-gpios {
+ rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_gpio: bt-gpio {
+ rockchip,pins =
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-func {
+ leds_gpio: leds-gpio {
+ rockchip,pins =
+ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ status = "okay";
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi (revision 151)
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/input/rk-input.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
+#include <dt-bindings/display/rockchip_vop.h>
+#include <dt-bindings/sensor-dev.h>
+
+/ {
+ adc_keys: adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ vol-up-key {
+ label = "volume up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ vol-down-key {
+ label = "volume down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ menu-key {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ back-key {
+ label = "back";
+ linux,code = <KEY_BACK>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <
+ 0 20 20 21 21 22 22 23
+ 23 24 24 25 25 26 26 27
+ 27 28 28 29 29 30 30 31
+ 31 32 32 33 33 34 34 35
+ 35 36 36 37 37 38 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255
+ >;
+ default-brightness-level = <200>;
+ };
+
+ backlight_1: backlight_1 {
+ compatible = "pwm-backlight";
+ brightness-levels = <
+ 0 20 20 21 21 22 22 23
+ 23 24 24 25 25 26 26 27
+ 27 28 28 29 29 30 30 31
+ 31 32 32 33 33 34 34 35
+ 35 36 36 37 37 38 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255
+ >;
+ default-brightness-level = <200>;
+ };
+
+ dp0_sound: dp0-sound {
+ status = "disabled";
+ compatible = "rockchip,hdmi";
+ rockchip,card-name= "rockchip-dp0";
+ rockchip,mclk-fs = <512>;
+ rockchip,cpu = <&spdif_tx2>;
+ rockchip,codec = <&dp0 1>;
+ rockchip,jack-det;
+ };
+
+ hdmi0_sound: hdmi0-sound {
+ status = "disabled";
+ compatible = "rockchip,hdmi";
+ rockchip,mclk-fs = <128>;
+ rockchip,card-name = "rockchip-hdmi0";
+ rockchip,cpu = <&i2s5_8ch>;
+ rockchip,codec = <&hdmi0>;
+ rockchip,jack-det;
+ };
+
+ spdif_tx1_dc: spdif-tx1-dc {
+ status = "disabled";
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ spdif_tx1_sound: spdif-tx1-sound {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rockchip,spdif-tx1";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif_tx1>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&spdif_tx1_dc>;
+ };
+ };
+
+ test-power {
+ status = "okay";
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+};
+
+&av1d {
+ status = "okay";
+};
+
+&av1d_mmu {
+ status = "okay";
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_mem_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_mem_s0>;
+};
+
+&dsi0 {
+ status = "okay";
+ //rockchip,lane-rate = <1000>;
+ dsi0_panel: panel@0 {
+ status = "okay";
+ compatible = "innolux,afj101-ba2131";
+ reg = <0>;
+ backlight = <&backlight>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_in_dsi: endpoint {
+ remote-endpoint = <&dsi_out_panel>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi_out_panel: endpoint {
+ remote-endpoint = <&panel_in_dsi>;
+ };
+ };
+ };
+
+};
+
+&dsi1 {
+ status = "okay";
+ //rockchip,lane-rate = <1000>;
+ dsi1_panel: panel@0 {
+ status = "okay";
+ compatible = "innolux,afj101-ba2131";
+ reg = <0>;
+ backlight = <&backlight_1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_in_dsi1: endpoint {
+ remote-endpoint = <&dsi1_out_panel>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi1_out_panel: endpoint {
+ remote-endpoint = <&panel_in_dsi1>;
+ };
+ };
+ };
+
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ mem-supply = <&vdd_gpu_mem_s0>;
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+};
+
+&iep {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&jpegd {
+ status = "okay";
+};
+
+&jpegd_mmu {
+ status = "okay";
+};
+
+&jpege_ccu {
+ status = "okay";
+};
+
+&jpege0 {
+ status = "okay";
+};
+
+&jpege0_mmu {
+ status = "okay";
+};
+
+&jpege1 {
+ status = "okay";
+};
+
+&jpege1_mmu {
+ status = "okay";
+};
+
+&jpege2 {
+ status = "okay";
+};
+
+&jpege2_mmu {
+ status = "okay";
+};
+
+&jpege3 {
+ status = "okay";
+};
+
+&jpege3_mmu {
+ status = "okay";
+};
+
+&mpp_srv {
+ status = "okay";
+};
+
+&rga3_core0 {
+ status = "okay";
+};
+
+&rga3_0_mmu {
+ status = "okay";
+};
+
+&rga3_core1 {
+ status = "okay";
+};
+
+&rga3_1_mmu {
+ status = "okay";
+};
+
+&rga2 {
+ status = "okay";
+};
+
+&rknpu {
+ rknpu-supply = <&vdd_npu_s0>;
+ mem-supply = <&vdd_npu_mem_s0>;
+ status = "okay";
+};
+
+&rknpu_mmu {
+ status = "okay";
+};
+
+&rkvdec_ccu {
+ status = "okay";
+};
+
+&rkvdec0 {
+ status = "okay";
+};
+
+&rkvdec0_mmu {
+ status = "okay";
+};
+
+&rkvdec1 {
+ status = "okay";
+};
+
+&rkvdec1_mmu {
+ status = "okay";
+};
+
+&rkvenc_ccu {
+ status = "okay";
+};
+
+&rkvenc0 {
+ status = "okay";
+};
+
+&rkvenc0_mmu {
+ status = "okay";
+};
+
+&rkvenc1 {
+ status = "okay";
+};
+
+&rkvenc1_mmu {
+ status = "okay";
+};
+
+&rockchip_suspend {
+ status = "okay";
+ rockchip,sleep-debug-en = <1>;
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc_1v8_s0>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "disabled";
+};
+
+&sdmmc {
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_sd_s0>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&usbdp_phy0_dp {
+ status = "okay";
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbhost3_0 {
+ status = "okay";
+};
+
+&usbhost_dwc3_0 {
+ status = "okay";
+};
+
+&vdpu {
+ status = "okay";
+};
+
+&vdpu_mmu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+ disable-win-move;
+ assigned-clocks = <&cru ACLK_VOP>;
+ assigned-clock-rates = <800000000>;
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vepu {
+ status = "okay";
+};
+
+/* vp0 & vp1 splice for 8K output */
+&vp0 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART0>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER0>;
+};
+
+&vp1 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART1>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER1>;
+};
+
+&vp2 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART2>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER2>;
+};
+
+&vp3 {
+ cursor-win-id=<ROCKCHIP_VOP2_ESMART3>;
+ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
+ rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER3>;
+};
+
+/* Fix tty terminal out of screen, and most dclk of resolutions was not supported in hdmiphy clock from parent clock by default */
+&display_subsystem {
+ clocks = <&hdptxphy_hdmi_clk0>;
+ clock-names = "hdmi0_phy_pll";
+};
Property changes on: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-orangepi.dtsi
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi (revision 151)
@@ -0,0 +1,3417 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ auddsm {
+ /omit-if-no-ref/
+ auddsm_pins: auddsm-pins {
+ rockchip,pins =
+ /* auddsm_ln */
+ <3 RK_PA1 4 &pcfg_pull_none>,
+ /* auddsm_lp */
+ <3 RK_PA2 4 &pcfg_pull_none>,
+ /* auddsm_rn */
+ <3 RK_PA3 4 &pcfg_pull_none>,
+ /* auddsm_rp */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ bt1120 {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ /* bt1120_clkout */
+ <4 RK_PB0 2 &pcfg_pull_none>,
+ /* bt1120_d0 */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* bt1120_d1 */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* bt1120_d2 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* bt1120_d3 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* bt1120_d4 */
+ <4 RK_PA4 2 &pcfg_pull_none>,
+ /* bt1120_d5 */
+ <4 RK_PA5 2 &pcfg_pull_none>,
+ /* bt1120_d6 */
+ <4 RK_PA6 2 &pcfg_pull_none>,
+ /* bt1120_d7 */
+ <4 RK_PA7 2 &pcfg_pull_none>,
+ /* bt1120_d8 */
+ <4 RK_PB2 2 &pcfg_pull_none>,
+ /* bt1120_d9 */
+ <4 RK_PB3 2 &pcfg_pull_none>,
+ /* bt1120_d10 */
+ <4 RK_PB4 2 &pcfg_pull_none>,
+ /* bt1120_d11 */
+ <4 RK_PB5 2 &pcfg_pull_none>,
+ /* bt1120_d12 */
+ <4 RK_PB6 2 &pcfg_pull_none>,
+ /* bt1120_d13 */
+ <4 RK_PB7 2 &pcfg_pull_none>,
+ /* bt1120_d14 */
+ <4 RK_PC0 2 &pcfg_pull_none>,
+ /* bt1120_d15 */
+ <4 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rx_m0 */
+ <0 RK_PC0 11 &pcfg_pull_none>,
+ /* can0_tx_m0 */
+ <0 RK_PB7 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rx_m1 */
+ <4 RK_PD5 9 &pcfg_pull_none>,
+ /* can0_tx_m1 */
+ <4 RK_PD4 9 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rx_m0 */
+ <3 RK_PB5 9 &pcfg_pull_none>,
+ /* can1_tx_m0 */
+ <3 RK_PB6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rx_m1 */
+ <4 RK_PB2 12 &pcfg_pull_none>,
+ /* can1_tx_m1 */
+ <4 RK_PB3 12 &pcfg_pull_none>;
+ };
+ };
+
+ can2 {
+ /omit-if-no-ref/
+ can2m0_pins: can2m0-pins {
+ rockchip,pins =
+ /* can2_rx_m0 */
+ <3 RK_PC4 9 &pcfg_pull_none>,
+ /* can2_tx_m0 */
+ <3 RK_PC5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can2m1_pins: can2m1-pins {
+ rockchip,pins =
+ /* can2_rx_m1 */
+ <0 RK_PD4 10 &pcfg_pull_none>,
+ /* can2_tx_m1 */
+ <0 RK_PD5 10 &pcfg_pull_none>;
+ };
+ };
+
+ cif {
+ /omit-if-no-ref/
+ cif_clk: cif-clk {
+ rockchip,pins =
+ /* cif_clkout */
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_clk: cif-dvp-clk {
+ rockchip,pins =
+ /* cif_clkin */
+ <4 RK_PB0 1 &pcfg_pull_none>,
+ /* cif_href */
+ <4 RK_PB2 1 &pcfg_pull_none>,
+ /* cif_vsync */
+ <4 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus16: cif-dvp-bus16 {
+ rockchip,pins =
+ /* cif_d8 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* cif_d9 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* cif_d10 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* cif_d11 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* cif_d12 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* cif_d13 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* cif_d14 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* cif_d15 */
+ <3 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus8: cif-dvp-bus8 {
+ rockchip,pins =
+ /* cif_d0 */
+ <4 RK_PA0 1 &pcfg_pull_none>,
+ /* cif_d1 */
+ <4 RK_PA1 1 &pcfg_pull_none>,
+ /* cif_d2 */
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ /* cif_d3 */
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ /* cif_d4 */
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ /* cif_d5 */
+ <4 RK_PA5 1 &pcfg_pull_none>,
+ /* cif_d6 */
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ /* cif_d7 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ clk32k {
+ /omit-if-no-ref/
+ clk32k_in: clk32k-in {
+ rockchip,pins =
+ /* clk32k_in */
+ <0 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clk32k_out0: clk32k-out0 {
+ rockchip,pins =
+ /* clk32k_out0 */
+ <0 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ /omit-if-no-ref/
+ cpu_pins: cpu-pins {
+ rockchip,pins =
+ /* cpu_big0_avs */
+ <0 RK_PD1 2 &pcfg_pull_none>,
+ /* cpu_big1_avs */
+ <0 RK_PD5 2 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych0 {
+ /omit-if-no-ref/
+ ddrphych0_pins: ddrphych0-pins {
+ rockchip,pins =
+ /* ddrphych0_dtb0 */
+ <4 RK_PA0 7 &pcfg_pull_none>,
+ /* ddrphych0_dtb1 */
+ <4 RK_PA1 7 &pcfg_pull_none>,
+ /* ddrphych0_dtb2 */
+ <4 RK_PA2 7 &pcfg_pull_none>,
+ /* ddrphych0_dtb3 */
+ <4 RK_PA3 7 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych1 {
+ /omit-if-no-ref/
+ ddrphych1_pins: ddrphych1-pins {
+ rockchip,pins =
+ /* ddrphych1_dtb0 */
+ <4 RK_PA4 7 &pcfg_pull_none>,
+ /* ddrphych1_dtb1 */
+ <4 RK_PA5 7 &pcfg_pull_none>,
+ /* ddrphych1_dtb2 */
+ <4 RK_PA6 7 &pcfg_pull_none>,
+ /* ddrphych1_dtb3 */
+ <4 RK_PA7 7 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych2 {
+ /omit-if-no-ref/
+ ddrphych2_pins: ddrphych2-pins {
+ rockchip,pins =
+ /* ddrphych2_dtb0 */
+ <4 RK_PB0 7 &pcfg_pull_none>,
+ /* ddrphych2_dtb1 */
+ <4 RK_PB1 7 &pcfg_pull_none>,
+ /* ddrphych2_dtb2 */
+ <4 RK_PB2 7 &pcfg_pull_none>,
+ /* ddrphych2_dtb3 */
+ <4 RK_PB3 7 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych3 {
+ /omit-if-no-ref/
+ ddrphych3_pins: ddrphych3-pins {
+ rockchip,pins =
+ /* ddrphych3_dtb0 */
+ <4 RK_PB4 7 &pcfg_pull_none>,
+ /* ddrphych3_dtb1 */
+ <4 RK_PB5 7 &pcfg_pull_none>,
+ /* ddrphych3_dtb2 */
+ <4 RK_PB6 7 &pcfg_pull_none>,
+ /* ddrphych3_dtb3 */
+ <4 RK_PB7 7 &pcfg_pull_none>;
+ };
+ };
+
+ dp0 {
+ /omit-if-no-ref/
+ dp0m0_pins: dp0m0-pins {
+ rockchip,pins =
+ /* dp0_hpdin_m0 */
+ <4 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp0m1_pins: dp0m1-pins {
+ rockchip,pins =
+ /* dp0_hpdin_m1 */
+ <0 RK_PC4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp0m2_pins: dp0m2-pins {
+ rockchip,pins =
+ /* dp0_hpdin_m2 */
+ <1 RK_PA0 5 &pcfg_pull_none>;
+ };
+ };
+
+ dp1 {
+ /omit-if-no-ref/
+ dp1m0_pins: dp1m0-pins {
+ rockchip,pins =
+ /* dp1_hpdin_m0 */
+ <3 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp1m1_pins: dp1m1-pins {
+ rockchip,pins =
+ /* dp1_hpdin_m1 */
+ <0 RK_PC5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp1m2_pins: dp1m2-pins {
+ rockchip,pins =
+ /* dp1_hpdin_m2 */
+ <1 RK_PA1 5 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <2 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clkout */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_data_strobe: emmc-data-strobe {
+ rockchip,pins =
+ /* emmc_data_strobe */
+ <2 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth1 {
+ /omit-if-no-ref/
+ eth1_pins: eth1-pins {
+ rockchip,pins =
+ /* eth1_refclko_25m */
+ <3 RK_PA6 1 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspim0_pins: fspim0-pins {
+ rockchip,pins =
+ /* fspi_clk_m0 */
+ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_cs0n_m0 */
+ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d0_m0 */
+ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d1_m0 */
+ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d2_m0 */
+ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d3_m0 */
+ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim0_cs1: fspim0-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n_m0 */
+ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim2_pins: fspim2-pins {
+ rockchip,pins =
+ /* fspi_clk_m2 */
+ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_cs0n_m2 */
+ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d0_m2 */
+ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d1_m2 */
+ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d2_m2 */
+ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d3_m2 */
+ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim2_cs1: fspim2-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n_m2 */
+ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+
+ gmac1 {
+ /omit-if-no-ref/
+ gmac1_miim: gmac1-miim {
+ rockchip,pins =
+ /* gmac1_mdc */
+ <3 RK_PC2 1 &pcfg_pull_none>,
+ /* gmac1_mdio */
+ <3 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_clkinout: gmac1-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinout */
+ <3 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_rx_bus2: gmac1-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* gmac1_rxd1 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* gmac1_rxdv_crs */
+ <3 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_tx_bus2: gmac1-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0 */
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ /* gmac1_txd1 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* gmac1_txen */
+ <3 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_rgmii_clk: gmac1-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclk */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* gmac1_txclk */
+ <3 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_rgmii_bus: gmac1-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2 */
+ <3 RK_PA2 1 &pcfg_pull_none>,
+ /* gmac1_rxd3 */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* gmac1_txd2 */
+ <3 RK_PA0 1 &pcfg_pull_none>,
+ /* gmac1_txd3 */
+ <3 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_ppsclk: gmac1-ppsclk {
+ rockchip,pins =
+ /* gmac1_ppsclk */
+ <3 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_ppstrig: gmac1-ppstrig {
+ rockchip,pins =
+ /* gmac1_ppstrig */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
+ rockchip,pins =
+ /* gmac1_ptp_ref_clk */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_txer: gmac1-txer {
+ rockchip,pins =
+ /* gmac1_txer */
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PC5 2 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ /omit-if-no-ref/
+ hdmim0_rx_cec: hdmim0-rx-cec {
+ rockchip,pins =
+ /* hdmim0_rx_cec */
+ <4 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_rx_hpdin: hdmim0-rx-hpdin {
+ rockchip,pins =
+ /* hdmim0_rx_hpdin */
+ <4 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_rx_scl: hdmim0-rx-scl {
+ rockchip,pins =
+ /* hdmim0_rx_scl */
+ <0 RK_PD2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_rx_sda: hdmim0-rx-sda {
+ rockchip,pins =
+ /* hdmim0_rx_sda */
+ <0 RK_PD1 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_cec: hdmim0-tx0-cec {
+ rockchip,pins =
+ /* hdmim0_tx0_cec */
+ <4 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_hpd: hdmim0-tx0-hpd {
+ rockchip,pins =
+ /* hdmim0_tx0_hpd */
+ <1 RK_PA5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_scl: hdmim0-tx0-scl {
+ rockchip,pins =
+ /* hdmim0_tx0_scl */
+ <4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_sda: hdmim0-tx0-sda {
+ rockchip,pins =
+ /* hdmim0_tx0_sda */
+ <4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx1_hpd: hdmim0-tx1-hpd {
+ rockchip,pins =
+ /* hdmim0_tx1_hpd */
+ <1 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx: hdmim1-rx {
+ rockchip,pins =
+ /* hdmim1_rx_cec */
+ <3 RK_PD1 5 &pcfg_pull_none>,
+ /* hdmim1_rx_scl */
+ <3 RK_PD2 5 &pcfg_pull_none_smt>,
+ /* hdmim1_rx_sda */
+ <3 RK_PD3 5 &pcfg_pull_none_smt>,
+ /* hdmim1_rx_hpdin */
+ <3 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_cec: hdmim1-rx-cec {
+ rockchip,pins =
+ /* hdmim1_rx_cec */
+ <3 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_hpdin: hdmim1-rx-hpdin {
+ rockchip,pins =
+ /* hdmim1_rx_hpdin */
+ <3 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_scl: hdmim1-rx-scl {
+ rockchip,pins =
+ /* hdmim1_rx_scl */
+ <3 RK_PD2 5 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_sda: hdmim1-rx-sda {
+ rockchip,pins =
+ /* hdmim1_rx_sda */
+ <3 RK_PD3 5 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_cec: hdmim1-tx0-cec {
+ rockchip,pins =
+ /* hdmim1_tx0_cec */
+ <0 RK_PD1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_hpd: hdmim1-tx0-hpd {
+ rockchip,pins =
+ /* hdmim1_tx0_hpd */
+ <3 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_scl: hdmim1-tx0-scl {
+ rockchip,pins =
+ /* hdmim1_tx0_scl */
+ <0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_sda: hdmim1-tx0-sda {
+ rockchip,pins =
+ /* hdmim1_tx0_sda */
+ <0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_cec: hdmim1-tx1-cec {
+ rockchip,pins =
+ /* hdmim1_tx1_cec */
+ <0 RK_PD2 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_hpd: hdmim1-tx1-hpd {
+ rockchip,pins =
+ /* hdmim1_tx1_hpd */
+ <3 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_scl: hdmim1-tx1-scl {
+ rockchip,pins =
+ /* hdmim1_tx1_scl */
+ <3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_sda: hdmim1-tx1-sda {
+ rockchip,pins =
+ /* hdmim1_tx1_sda */
+ <3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
+ };
+ /omit-if-no-ref/
+ hdmim2_rx_cec: hdmim2-rx-cec {
+ rockchip,pins =
+ /* hdmim2_rx_cec */
+ <1 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_rx_hpdin: hdmim2-rx-hpdin {
+ rockchip,pins =
+ /* hdmim2_rx_hpdin */
+ <1 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_rx_scl: hdmim2-rx-scl {
+ rockchip,pins =
+ /* hdmim2_rx_scl */
+ <1 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_rx_sda: hdmim2-rx-sda {
+ rockchip,pins =
+ /* hdmim2_rx_sda */
+ <1 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx0_scl: hdmim2-tx0-scl {
+ rockchip,pins =
+ /* hdmim2_tx0_scl */
+ <3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx0_sda: hdmim2-tx0-sda {
+ rockchip,pins =
+ /* hdmim2_tx0_sda */
+ <3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx1_cec: hdmim2-tx1-cec {
+ rockchip,pins =
+ /* hdmim2_tx1_cec */
+ <3 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx1_scl: hdmim2-tx1-scl {
+ rockchip,pins =
+ /* hdmim2_tx1_scl */
+ <1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx1_sda: hdmim2-tx1-sda {
+ rockchip,pins =
+ /* hdmim2_tx1_sda */
+ <1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug0: hdmi-debug0 {
+ rockchip,pins =
+ /* hdmi_debug0 */
+ <1 RK_PA7 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug1: hdmi-debug1 {
+ rockchip,pins =
+ /* hdmi_debug1 */
+ <1 RK_PB0 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug2: hdmi-debug2 {
+ rockchip,pins =
+ /* hdmi_debug2 */
+ <1 RK_PB1 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug3: hdmi-debug3 {
+ rockchip,pins =
+ /* hdmi_debug3 */
+ <1 RK_PB2 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug4: hdmi-debug4 {
+ rockchip,pins =
+ /* hdmi_debug4 */
+ <1 RK_PB3 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug5: hdmi-debug5 {
+ rockchip,pins =
+ /* hdmi_debug5 */
+ <1 RK_PB4 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug6: hdmi-debug6 {
+ rockchip,pins =
+ /* hdmi_debug6 */
+ <1 RK_PA0 7 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <0 RK_PB3 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <0 RK_PA6 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m2_xfer: i2c0m2-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m2 */
+ <0 RK_PD1 3 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m2 */
+ <0 RK_PD2 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB5 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB6 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <0 RK_PB0 2 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <0 RK_PB1 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m2_xfer: i2c1m2-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m2 */
+ <0 RK_PD4 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m2 */
+ <0 RK_PD5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m3_xfer: i2c1m3-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m3 */
+ <2 RK_PD4 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m3 */
+ <2 RK_PD5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m4_xfer: i2c1m4-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m4 */
+ <1 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m4 */
+ <1 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PB7 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m2_xfer: i2c2m2-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m2 */
+ <2 RK_PA3 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m2 */
+ <2 RK_PA2 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m3_xfer: i2c2m3-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m3 */
+ <1 RK_PC5 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m3 */
+ <1 RK_PC4 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m4_xfer: i2c2m4-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m4 */
+ <1 RK_PA1 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m4 */
+ <1 RK_PA0 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <1 RK_PC1 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <1 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <3 RK_PB7 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <3 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <4 RK_PA4 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m2 */
+ <4 RK_PA5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m4_xfer: i2c3m4-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m4 */
+ <4 RK_PD0 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m4 */
+ <4 RK_PD1 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PA6 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PA5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m2_xfer: i2c4m2-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m2 */
+ <0 RK_PC5 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m2 */
+ <0 RK_PC4 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m3_xfer: i2c4m3-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m3 */
+ <1 RK_PA3 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m3 */
+ <1 RK_PA2 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m4_xfer: i2c4m4-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m4 */
+ <1 RK_PC7 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m4 */
+ <1 RK_PC6 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <3 RK_PC7 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <3 RK_PD0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <4 RK_PB6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <4 RK_PB7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <4 RK_PA6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m2 */
+ <4 RK_PA7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m3_xfer: i2c5m3-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m3 */
+ <1 RK_PB6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m3 */
+ <1 RK_PB7 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m0_xfer: i2c6m0-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <0 RK_PD0 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m0 */
+ <0 RK_PC7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m1_xfer: i2c6m1-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m1 */
+ <1 RK_PC3 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m1 */
+ <1 RK_PC2 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m3_xfer: i2c6m3-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m3 */
+ <4 RK_PB1 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m3 */
+ <4 RK_PB0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m4_xfer: i2c6m4-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m4 */
+ <3 RK_PA1 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m4 */
+ <3 RK_PA0 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7m0_xfer: i2c7m0-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m0 */
+ <1 RK_PD0 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m0 */
+ <1 RK_PD1 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m2_xfer: i2c7m2-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m2 */
+ <3 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m2 */
+ <3 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m3_xfer: i2c7m3-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m3 */
+ <4 RK_PB2 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m3 */
+ <4 RK_PB3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c8 {
+ /omit-if-no-ref/
+ i2c8m0_xfer: i2c8m0-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m0 */
+ <4 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m0 */
+ <4 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m2_xfer: i2c8m2-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m2 */
+ <1 RK_PD6 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m2 */
+ <1 RK_PD7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m3_xfer: i2c8m3-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m3 */
+ <4 RK_PC0 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m3 */
+ <4 RK_PC1 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m4_xfer: i2c8m4-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m4 */
+ <3 RK_PC2 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m4 */
+ <3 RK_PC3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ /omit-if-no-ref/
+ i2s0_lrck: i2s0-lrck {
+ rockchip,pins =
+ /* i2s0_lrck */
+ <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_mclk: i2s0-mclk {
+ rockchip,pins =
+ /* i2s0_mclk */
+ <1 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sclk: i2s0-sclk {
+ rockchip,pins =
+ /* i2s0_sclk */
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi0: i2s0-sdi0 {
+ rockchip,pins =
+ /* i2s0_sdi0 */
+ <1 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi1: i2s0-sdi1 {
+ rockchip,pins =
+ /* i2s0_sdi1 */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi2: i2s0-sdi2 {
+ rockchip,pins =
+ /* i2s0_sdi2 */
+ <1 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi3: i2s0-sdi3 {
+ rockchip,pins =
+ /* i2s0_sdi3 */
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo0: i2s0-sdo0 {
+ rockchip,pins =
+ /* i2s0_sdo0 */
+ <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo1: i2s0-sdo1 {
+ rockchip,pins =
+ /* i2s0_sdo1 */
+ <1 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo2: i2s0-sdo2 {
+ rockchip,pins =
+ /* i2s0_sdo2 */
+ <1 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo3: i2s0-sdo3 {
+ rockchip,pins =
+ /* i2s0_sdo3 */
+ <1 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1m0_lrck: i2s1m0-lrck {
+ rockchip,pins =
+ /* i2s1m0_lrck */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_mclk: i2s1m0-mclk {
+ rockchip,pins =
+ /* i2s1m0_mclk */
+ <4 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclk: i2s1m0-sclk {
+ rockchip,pins =
+ /* i2s1m0_sclk */
+ <4 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi0: i2s1m0-sdi0 {
+ rockchip,pins =
+ /* i2s1m0_sdi0 */
+ <4 RK_PA5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi1: i2s1m0-sdi1 {
+ rockchip,pins =
+ /* i2s1m0_sdi1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi2: i2s1m0-sdi2 {
+ rockchip,pins =
+ /* i2s1m0_sdi2 */
+ <4 RK_PA7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi3: i2s1m0-sdi3 {
+ rockchip,pins =
+ /* i2s1m0_sdi3 */
+ <4 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo0: i2s1m0-sdo0 {
+ rockchip,pins =
+ /* i2s1m0_sdo0 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo1: i2s1m0-sdo1 {
+ rockchip,pins =
+ /* i2s1m0_sdo1 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo2: i2s1m0-sdo2 {
+ rockchip,pins =
+ /* i2s1m0_sdo2 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo3: i2s1m0-sdo3 {
+ rockchip,pins =
+ /* i2s1m0_sdo3 */
+ <4 RK_PB4 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ i2s1m1_lrck: i2s1m1-lrck {
+ rockchip,pins =
+ /* i2s1m1_lrck */
+ <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_mclk: i2s1m1-mclk {
+ rockchip,pins =
+ /* i2s1m1_mclk */
+ <0 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclk: i2s1m1-sclk {
+ rockchip,pins =
+ /* i2s1m1_sclk */
+ <0 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi0: i2s1m1-sdi0 {
+ rockchip,pins =
+ /* i2s1m1_sdi0 */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi1: i2s1m1-sdi1 {
+ rockchip,pins =
+ /* i2s1m1_sdi1 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi2: i2s1m1-sdi2 {
+ rockchip,pins =
+ /* i2s1m1_sdi2 */
+ <0 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi3: i2s1m1-sdi3 {
+ rockchip,pins =
+ /* i2s1m1_sdi3 */
+ <0 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo0: i2s1m1-sdo0 {
+ rockchip,pins =
+ /* i2s1m1_sdo0 */
+ <0 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo1: i2s1m1-sdo1 {
+ rockchip,pins =
+ /* i2s1m1_sdo1 */
+ <0 RK_PD2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo2: i2s1m1-sdo2 {
+ rockchip,pins =
+ /* i2s1m1_sdo2 */
+ <0 RK_PD4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo3: i2s1m1-sdo3 {
+ rockchip,pins =
+ /* i2s1m1_sdo3 */
+ <0 RK_PD5 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m1_lrck: i2s2m1-lrck {
+ rockchip,pins =
+ /* i2s2m1_lrck */
+ <3 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ /* i2s2m1_mclk */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclk: i2s2m1-sclk {
+ rockchip,pins =
+ /* i2s2m1_sclk */
+ <3 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ /* i2s2m1_sdi */
+ <3 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ /* i2s2m1_sdo */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2s3 {
+ /omit-if-no-ref/
+ i2s3_lrck: i2s3-lrck {
+ rockchip,pins =
+ /* i2s3_lrck */
+ <3 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_mclk: i2s3-mclk {
+ rockchip,pins =
+ /* i2s3_mclk */
+ <3 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_sclk: i2s3-sclk {
+ rockchip,pins =
+ /* i2s3_sclk */
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_sdi: i2s3-sdi {
+ rockchip,pins =
+ /* i2s3_sdi */
+ <3 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_sdo: i2s3-sdo {
+ rockchip,pins =
+ /* i2s3_sdo */
+ <3 RK_PA3 3 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_tck_m0 */
+ <4 RK_PD2 5 &pcfg_pull_none>,
+ /* jtag_tms_m0 */
+ <4 RK_PD3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_tck_m1 */
+ <4 RK_PD0 5 &pcfg_pull_none>,
+ /* jtag_tms_m1 */
+ <4 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm2_pins: jtagm2-pins {
+ rockchip,pins =
+ /* jtag_tck_m2 */
+ <0 RK_PB5 2 &pcfg_pull_none>,
+ /* jtag_tms_m2 */
+ <0 RK_PB6 2 &pcfg_pull_none>;
+ };
+ };
+
+ litcpu {
+ /omit-if-no-ref/
+ litcpu_pins: litcpu-pins {
+ rockchip,pins =
+ /* litcpu_avs */
+ <0 RK_PD3 1 &pcfg_pull_none>;
+ };
+ };
+
+ mcu {
+ /omit-if-no-ref/
+ mcum0_pins: mcum0-pins {
+ rockchip,pins =
+ /* mcu_jtag_tck_m0 */
+ <4 RK_PD4 5 &pcfg_pull_none>,
+ /* mcu_jtag_tms_m0 */
+ <4 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mcum1_pins: mcum1-pins {
+ rockchip,pins =
+ /* mcu_jtag_tck_m1 */
+ <3 RK_PD4 6 &pcfg_pull_none>,
+ /* mcu_jtag_tms_m1 */
+ <3 RK_PD5 6 &pcfg_pull_none>;
+ };
+ };
+
+ mipi {
+ /omit-if-no-ref/
+ mipim0_camera0_clk: mipim0-camera0-clk {
+ rockchip,pins =
+ /* mipim0_camera0_clk */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera1_clk: mipim0-camera1-clk {
+ rockchip,pins =
+ /* mipim0_camera1_clk */
+ <1 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera2_clk: mipim0-camera2-clk {
+ rockchip,pins =
+ /* mipim0_camera2_clk */
+ <1 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera3_clk: mipim0-camera3-clk {
+ rockchip,pins =
+ /* mipim0_camera3_clk */
+ <1 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera4_clk: mipim0-camera4-clk {
+ rockchip,pins =
+ /* mipim0_camera4_clk */
+ <1 RK_PD7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera0_clk: mipim1-camera0-clk {
+ rockchip,pins =
+ /* mipim1_camera0_clk */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera1_clk: mipim1-camera1-clk {
+ rockchip,pins =
+ /* mipim1_camera1_clk */
+ <3 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera2_clk: mipim1-camera2-clk {
+ rockchip,pins =
+ /* mipim1_camera2_clk */
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera3_clk: mipim1-camera3-clk {
+ rockchip,pins =
+ /* mipim1_camera3_clk */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera4_clk: mipim1-camera4-clk {
+ rockchip,pins =
+ /* mipim1_camera4_clk */
+ <3 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipi_te0: mipi-te0 {
+ rockchip,pins =
+ /* mipi_te0 */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipi_te1: mipi-te1 {
+ rockchip,pins =
+ /* mipi_te1 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PC6 2 &pcfg_pull_none>;
+ };
+ };
+
+ pcie20x1 {
+ /omit-if-no-ref/
+ pcie20x1m0_pins: pcie20x1m0-pins {
+ rockchip,pins =
+ /* pcie20x1_2_clkreqn_m0 */
+ <3 RK_PC7 4 &pcfg_pull_none>,
+ /* pcie20x1_2_perstn_m0 */
+ <3 RK_PD1 4 &pcfg_pull_none>,
+ /* pcie20x1_2_waken_m0 */
+ <3 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_pins: pcie20x1m1-pins {
+ rockchip,pins =
+ /* pcie20x1_2_clkreqn_m1 */
+ <4 RK_PB7 4 &pcfg_pull_none>,
+ /* pcie20x1_2_perstn_m1 */
+ <4 RK_PC1 4 &pcfg_pull_none>,
+ /* pcie20x1_2_waken_m1 */
+ <4 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
+ rockchip,pins =
+ /* pcie20x1_2_button_rstn */
+ <4 RK_PB3 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30phy {
+ /omit-if-no-ref/
+ pcie30phy_pins: pcie30phy-pins {
+ rockchip,pins =
+ /* pcie30phy_dtb0 */
+ <1 RK_PC4 4 &pcfg_pull_none>,
+ /* pcie30phy_dtb1 */
+ <1 RK_PD1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x1 {
+ /omit-if-no-ref/
+ pcie30x1m0_pins: pcie30x1m0-pins {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m0 */
+ <0 RK_PC0 12 &pcfg_pull_none>,
+ /* pcie30x1_0_perstn_m0 */
+ <0 RK_PC5 12 &pcfg_pull_none>,
+ /* pcie30x1_0_waken_m0 */
+ <0 RK_PC4 12 &pcfg_pull_none>,
+ /* pcie30x1_1_clkreqn_m0 */
+ <0 RK_PB5 12 &pcfg_pull_none>,
+ /* pcie30x1_1_perstn_m0 */
+ <0 RK_PB7 12 &pcfg_pull_none>,
+ /* pcie30x1_1_waken_m0 */
+ <0 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_pins: pcie30x1m1-pins {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m1 */
+ <4 RK_PA3 4 &pcfg_pull_none>,
+ /* pcie30x1_0_perstn_m1 */
+ <4 RK_PA5 4 &pcfg_pull_none>,
+ /* pcie30x1_0_waken_m1 */
+ <4 RK_PA4 4 &pcfg_pull_none>,
+ /* pcie30x1_1_clkreqn_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie30x1_1_perstn_m1 */
+ <4 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie30x1_1_waken_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_pins: pcie30x1m2-pins {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m2 */
+ <1 RK_PB5 4 &pcfg_pull_none>,
+ /* pcie30x1_0_perstn_m2 */
+ <1 RK_PB4 4 &pcfg_pull_none>,
+ /* pcie30x1_0_waken_m2 */
+ <1 RK_PB3 4 &pcfg_pull_none>,
+ /* pcie30x1_1_clkreqn_m2 */
+ <1 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie30x1_1_perstn_m2 */
+ <1 RK_PA7 4 &pcfg_pull_none>,
+ /* pcie30x1_1_waken_m2 */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
+ rockchip,pins =
+ /* pcie30x1_0_button_rstn */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
+ rockchip,pins =
+ /* pcie30x1_1_button_rstn */
+ <4 RK_PB2 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x2 {
+ /omit-if-no-ref/
+ pcie30x2m0_pins: pcie30x2m0-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m0 */
+ <0 RK_PD1 12 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m0 */
+ <0 RK_PD4 12 &pcfg_pull_none>,
+ /* pcie30x2_waken_m0 */
+ <0 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_pins: pcie30x2m1-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m1 */
+ <4 RK_PA6 4 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m1 */
+ <4 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie30x2_waken_m1 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_pins: pcie30x2m2-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m2 */
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m2 */
+ <3 RK_PD4 4 &pcfg_pull_none>,
+ /* pcie30x2_waken_m2 */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_pins: pcie30x2m3-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m3 */
+ <1 RK_PD7 4 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m3 */
+ <1 RK_PB7 4 &pcfg_pull_none>,
+ /* pcie30x2_waken_m3 */
+ <1 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2_button_rstn: pcie30x2-button-rstn {
+ rockchip,pins =
+ /* pcie30x2_button_rstn */
+ <3 RK_PC1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x4 {
+ /omit-if-no-ref/
+ pcie30x4m0_pins: pcie30x4m0-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m0 */
+ <0 RK_PC6 12 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m0 */
+ <0 RK_PD0 12 &pcfg_pull_none>,
+ /* pcie30x4_waken_m0 */
+ <0 RK_PC7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_pins: pcie30x4m1-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m1 */
+ <4 RK_PB4 4 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m1 */
+ <4 RK_PB6 4 &pcfg_pull_none>,
+ /* pcie30x4_waken_m1 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_pins: pcie30x4m2-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m2 */
+ <3 RK_PC4 4 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m2 */
+ <3 RK_PC6 4 &pcfg_pull_none>,
+ /* pcie30x4_waken_m2 */
+ <3 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_pins: pcie30x4m3-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m3 */
+ <1 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m3 */
+ <1 RK_PB2 4 &pcfg_pull_none>,
+ /* pcie30x4_waken_m3 */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4_button_rstn: pcie30x4-button-rstn {
+ rockchip,pins =
+ /* pcie30x4_button_rstn */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pdm0 {
+ /omit-if-no-ref/
+ pdm0m0_clk: pdm0m0-clk {
+ rockchip,pins =
+ /* pdm0_clk0_m0 */
+ <1 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_clk1: pdm0m0-clk1 {
+ rockchip,pins =
+ /* pdm0m0_clk1 */
+ <1 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi0: pdm0m0-sdi0 {
+ rockchip,pins =
+ /* pdm0m0_sdi0 */
+ <1 RK_PD5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi1: pdm0m0-sdi1 {
+ rockchip,pins =
+ /* pdm0m0_sdi1 */
+ <1 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi2: pdm0m0-sdi2 {
+ rockchip,pins =
+ /* pdm0m0_sdi2 */
+ <1 RK_PD2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi3: pdm0m0-sdi3 {
+ rockchip,pins =
+ /* pdm0m0_sdi3 */
+ <1 RK_PD3 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ pdm0m1_clk: pdm0m1-clk {
+ rockchip,pins =
+ /* pdm0_clk0_m1 */
+ <0 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_clk1: pdm0m1-clk1 {
+ rockchip,pins =
+ /* pdm0m1_clk1 */
+ <0 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi0: pdm0m1-sdi0 {
+ rockchip,pins =
+ /* pdm0m1_sdi0 */
+ <0 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi1: pdm0m1-sdi1 {
+ rockchip,pins =
+ /* pdm0m1_sdi1 */
+ <0 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi2: pdm0m1-sdi2 {
+ rockchip,pins =
+ /* pdm0m1_sdi2 */
+ <0 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi3: pdm0m1-sdi3 {
+ rockchip,pins =
+ /* pdm0m1_sdi3 */
+ <0 RK_PD6 2 &pcfg_pull_none>;
+ };
+ };
+
+ pdm1 {
+ /omit-if-no-ref/
+ pdm1m0_clk: pdm1m0-clk {
+ rockchip,pins =
+ /* pdm1_clk0_m0 */
+ <4 RK_PD5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_clk1: pdm1m0-clk1 {
+ rockchip,pins =
+ /* pdm1m0_clk1 */
+ <4 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi0: pdm1m0-sdi0 {
+ rockchip,pins =
+ /* pdm1m0_sdi0 */
+ <4 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi1: pdm1m0-sdi1 {
+ rockchip,pins =
+ /* pdm1m0_sdi1 */
+ <4 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi2: pdm1m0-sdi2 {
+ rockchip,pins =
+ /* pdm1m0_sdi2 */
+ <4 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi3: pdm1m0-sdi3 {
+ rockchip,pins =
+ /* pdm1m0_sdi3 */
+ <4 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ pdm1m1_clk: pdm1m1-clk {
+ rockchip,pins =
+ /* pdm1_clk0_m1 */
+ <1 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_clk1: pdm1m1-clk1 {
+ rockchip,pins =
+ /* pdm1m1_clk1 */
+ <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi0: pdm1m1-sdi0 {
+ rockchip,pins =
+ /* pdm1m1_sdi0 */
+ <1 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi1: pdm1m1-sdi1 {
+ rockchip,pins =
+ /* pdm1m1_sdi1 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi2: pdm1m1-sdi2 {
+ rockchip,pins =
+ /* pdm1m1_sdi2 */
+ <1 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi3: pdm1m1-sdi3 {
+ rockchip,pins =
+ /* pdm1m1_sdi3 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ /omit-if-no-ref/
+ pmic_pins: pmic-pins {
+ rockchip,pins =
+ /* pmic_int_l */
+ <0 RK_PA7 0 &pcfg_pull_up>,
+ /* pmic_sleep1 */
+ <0 RK_PA2 1 &pcfg_pull_down>,
+ /* pmic_sleep2 */
+ <0 RK_PA3 1 &pcfg_pull_none>,
+ /* pmic_sleep3 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* pmic_sleep4 */
+ <0 RK_PC2 1 &pcfg_pull_none>,
+ /* pmic_sleep5 */
+ <0 RK_PC3 1 &pcfg_pull_none>,
+ /* pmic_sleep6 */
+ <0 RK_PD6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <0 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <0 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PD2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_pins: pwm0m2-pins {
+ rockchip,pins =
+ /* pwm0_m2 */
+ <1 RK_PA2 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <0 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PD3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_pins: pwm1m2-pins {
+ rockchip,pins =
+ /* pwm1_m2 */
+ <1 RK_PA3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <0 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <3 RK_PB1 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_ir_m0 */
+ <0 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_ir_m1 */
+ <3 RK_PB2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m2_pins: pwm3m2-pins {
+ rockchip,pins =
+ /* pwm3_ir_m2 */
+ <1 RK_PC2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m3_pins: pwm3m3-pins {
+ rockchip,pins =
+ /* pwm3_ir_m3 */
+ <1 RK_PA7 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <0 RK_PC5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <0 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <0 RK_PC6 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <0 RK_PC7 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <4 RK_PC1 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_ir_m0 */
+ <0 RK_PD0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_ir_m1 */
+ <4 RK_PD4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m2_pins: pwm7m2-pins {
+ rockchip,pins =
+ /* pwm7_ir_m2 */
+ <1 RK_PC3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm8 {
+ /omit-if-no-ref/
+ pwm8m0_pins: pwm8m0-pins {
+ rockchip,pins =
+ /* pwm8_m0 */
+ <3 RK_PA7 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m1_pins: pwm8m1-pins {
+ rockchip,pins =
+ /* pwm8_m1 */
+ <4 RK_PD0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m2_pins: pwm8m2-pins {
+ rockchip,pins =
+ /* pwm8_m2 */
+ <3 RK_PD0 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm9 {
+ /omit-if-no-ref/
+ pwm9m0_pins: pwm9m0-pins {
+ rockchip,pins =
+ /* pwm9_m0 */
+ <3 RK_PB0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m1_pins: pwm9m1-pins {
+ rockchip,pins =
+ /* pwm9_m1 */
+ <4 RK_PD1 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m2_pins: pwm9m2-pins {
+ rockchip,pins =
+ /* pwm9_m2 */
+ <3 RK_PD1 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm10 {
+ /omit-if-no-ref/
+ pwm10m0_pins: pwm10m0-pins {
+ rockchip,pins =
+ /* pwm10_m0 */
+ <3 RK_PA0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m1_pins: pwm10m1-pins {
+ rockchip,pins =
+ /* pwm10_m1 */
+ <4 RK_PD3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m2_pins: pwm10m2-pins {
+ rockchip,pins =
+ /* pwm10_m2 */
+ <3 RK_PD3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm11 {
+ /omit-if-no-ref/
+ pwm11m0_pins: pwm11m0-pins {
+ rockchip,pins =
+ /* pwm11_ir_m0 */
+ <3 RK_PA1 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m1_pins: pwm11m1-pins {
+ rockchip,pins =
+ /* pwm11_ir_m1 */
+ <4 RK_PB4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m2_pins: pwm11m2-pins {
+ rockchip,pins =
+ /* pwm11_ir_m2 */
+ <1 RK_PC4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m3_pins: pwm11m3-pins {
+ rockchip,pins =
+ /* pwm11_ir_m3 */
+ <3 RK_PD5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm12 {
+ /omit-if-no-ref/
+ pwm12m0_pins: pwm12m0-pins {
+ rockchip,pins =
+ /* pwm12_m0 */
+ <3 RK_PB5 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm12m1_pins: pwm12m1-pins {
+ rockchip,pins =
+ /* pwm12_m1 */
+ <4 RK_PB5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm13 {
+ /omit-if-no-ref/
+ pwm13m0_pins: pwm13m0-pins {
+ rockchip,pins =
+ /* pwm13_m0 */
+ <3 RK_PB6 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m1_pins: pwm13m1-pins {
+ rockchip,pins =
+ /* pwm13_m1 */
+ <4 RK_PB6 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m2_pins: pwm13m2-pins {
+ rockchip,pins =
+ /* pwm13_m2 */
+ <1 RK_PB7 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm14 {
+ /omit-if-no-ref/
+ pwm14m0_pins: pwm14m0-pins {
+ rockchip,pins =
+ /* pwm14_m0 */
+ <3 RK_PC2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m1_pins: pwm14m1-pins {
+ rockchip,pins =
+ /* pwm14_m1 */
+ <4 RK_PB2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m2_pins: pwm14m2-pins {
+ rockchip,pins =
+ /* pwm14_m2 */
+ <1 RK_PD6 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm15 {
+ /omit-if-no-ref/
+ pwm15m0_pins: pwm15m0-pins {
+ rockchip,pins =
+ /* pwm15_ir_m0 */
+ <3 RK_PC3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m1_pins: pwm15m1-pins {
+ rockchip,pins =
+ /* pwm15_ir_m1 */
+ <4 RK_PB3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m2_pins: pwm15m2-pins {
+ rockchip,pins =
+ /* pwm15_ir_m2 */
+ <1 RK_PC6 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m3_pins: pwm15m3-pins {
+ rockchip,pins =
+ /* pwm15_ir_m3 */
+ <1 RK_PD7 11 &pcfg_pull_none>;
+ };
+ };
+
+ refclk {
+ /omit-if-no-ref/
+ refclk_pins: refclk-pins {
+ rockchip,pins =
+ /* refclk_out */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ sata {
+ /omit-if-no-ref/
+ sata_pins: sata-pins {
+ rockchip,pins =
+ /* sata_cp_pod */
+ <0 RK_PC6 13 &pcfg_pull_none>,
+ /* sata_cpdet */
+ <0 RK_PD4 13 &pcfg_pull_none>,
+ /* sata_mp_switch */
+ <0 RK_PD5 13 &pcfg_pull_none>;
+ };
+ };
+
+ sata0 {
+ /omit-if-no-ref/
+ sata0m0_pins: sata0m0-pins {
+ rockchip,pins =
+ /* sata0_act_led_m0 */
+ <4 RK_PB6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata0m1_pins: sata0m1-pins {
+ rockchip,pins =
+ /* sata0_act_led_m1 */
+ <1 RK_PB3 6 &pcfg_pull_none>;
+ };
+ };
+
+ sata1 {
+ /omit-if-no-ref/
+ sata1m0_pins: sata1m0-pins {
+ rockchip,pins =
+ /* sata1_act_led_m0 */
+ <4 RK_PB5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata1m1_pins: sata1m1-pins {
+ rockchip,pins =
+ /* sata1_act_led_m1 */
+ <1 RK_PA1 6 &pcfg_pull_none>;
+ };
+ };
+
+ sata2 {
+ /omit-if-no-ref/
+ sata2m0_pins: sata2m0-pins {
+ rockchip,pins =
+ /* sata2_act_led_m0 */
+ <4 RK_PB1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata2m1_pins: sata2m1-pins {
+ rockchip,pins =
+ /* sata2_act_led_m1 */
+ <1 RK_PB7 6 &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ /omit-if-no-ref/
+ sdiom1_pins: sdiom1-pins {
+ rockchip,pins =
+ /* sdio_clk_m1 */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* sdio_cmd_m1 */
+ <3 RK_PA4 2 &pcfg_pull_up>,
+ /* sdio_d0_m1 */
+ <3 RK_PA0 2 &pcfg_pull_up>,
+ /* sdio_d1_m1 */
+ <3 RK_PA1 2 &pcfg_pull_up>,
+ /* sdio_d2_m1 */
+ <3 RK_PA2 2 &pcfg_pull_up>,
+ /* sdio_d3_m1 */
+ <3 RK_PA3 2 &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ /omit-if-no-ref/
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ /* sdmmc_d0 */
+ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d1 */
+ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d2 */
+ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d3 */
+ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ /* sdmmc_clk */
+ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ /* sdmmc_cmd */
+ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_det: sdmmc-det {
+ rockchip,pins =
+ /* sdmmc_det */
+ <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ /* sdmmc_pwren */
+ <0 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif0 {
+ /omit-if-no-ref/
+ spdif0m0_tx: spdif0m0-tx {
+ rockchip,pins =
+ /* spdif0m0_tx */
+ <1 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdif0m1_tx: spdif0m1-tx {
+ rockchip,pins =
+ /* spdif0m1_tx */
+ <4 RK_PB4 6 &pcfg_pull_none>;
+ };
+ };
+
+ spdif1 {
+ /omit-if-no-ref/
+ spdif1m0_tx: spdif1m0-tx {
+ rockchip,pins =
+ /* spdif1m0_tx */
+ <1 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdif1m1_tx: spdif1m1-tx {
+ rockchip,pins =
+ /* spdif1m1_tx */
+ <4 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdif1m2_tx: spdif1m2-tx {
+ rockchip,pins =
+ /* spdif1m2_tx */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <0 RK_PC6 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_miso_m0 */
+ <0 RK_PC7 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_mosi_m0 */
+ <0 RK_PC0 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m0 */
+ <0 RK_PD1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m0 */
+ <0 RK_PB7 8 &pcfg_pull_up_drv_level_6>;
+ };
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clk_m1 */
+ <4 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_miso_m1 */
+ <4 RK_PA0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_mosi_m1 */
+ <4 RK_PA1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m1 */
+ <4 RK_PB2 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs1: spi0m1-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m1 */
+ <4 RK_PB1 8 &pcfg_pull_up_drv_level_6>;
+ };
+ /omit-if-no-ref/
+ spi0m2_pins: spi0m2-pins {
+ rockchip,pins =
+ /* spi0_clk_m2 */
+ <1 RK_PB3 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_miso_m2 */
+ <1 RK_PB1 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_mosi_m2 */
+ <1 RK_PB2 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_cs0: spi0m2-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m2 */
+ <1 RK_PB4 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_cs1: spi0m2-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m2 */
+ <1 RK_PB5 8 &pcfg_pull_up_drv_level_6>;
+ };
+ /omit-if-no-ref/
+ spi0m3_pins: spi0m3-pins {
+ rockchip,pins =
+ /* spi0_clk_m3 */
+ <3 RK_PD3 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_miso_m3 */
+ <3 RK_PD1 8 &pcfg_pull_up_drv_level_6>,
+ /* spi0_mosi_m3 */
+ <3 RK_PD2 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m3_cs0: spi0m3-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m3 */
+ <3 RK_PD4 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi0m3_cs1: spi0m3-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m3 */
+ <3 RK_PD5 8 &pcfg_pull_up_drv_level_6>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clk_m1 */
+ <3 RK_PC1 8 &pcfg_pull_up_drv_level_6>,
+ /* spi1_miso_m1 */
+ <3 RK_PC0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi1_mosi_m1 */
+ <3 RK_PB7 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs0: spi1m1-cs0 {
+ rockchip,pins =
+ /* spi1_cs0_m1 */
+ <3 RK_PC2 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs1: spi1m1-cs1 {
+ rockchip,pins =
+ /* spi1_cs1_m1 */
+ <3 RK_PC3 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_pins: spi1m2-pins {
+ rockchip,pins =
+ /* spi1_clk_m2 */
+ <1 RK_PD2 8 &pcfg_pull_up_drv_level_6>,
+ /* spi1_miso_m2 */
+ <1 RK_PD0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi1_mosi_m2 */
+ <1 RK_PD1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_cs0: spi1m2-cs0 {
+ rockchip,pins =
+ /* spi1_cs0_m2 */
+ <1 RK_PD3 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_cs1: spi1m2-cs1 {
+ rockchip,pins =
+ /* spi1_cs1_m2 */
+ <1 RK_PD5 8 &pcfg_pull_up_drv_level_6>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clk_m0 */
+ <1 RK_PA6 8 &pcfg_pull_up_drv_level_6>,
+ /* spi2_miso_m0 */
+ <1 RK_PA4 8 &pcfg_pull_up_drv_level_6>,
+ /* spi2_mosi_m0 */
+ <1 RK_PA5 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs0: spi2m0-cs0 {
+ rockchip,pins =
+ /* spi2_cs0_m0 */
+ <1 RK_PA7 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs1: spi2m0-cs1 {
+ rockchip,pins =
+ /* spi2_cs1_m0 */
+ <1 RK_PB0 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clk_m1 */
+ <4 RK_PA6 8 &pcfg_pull_up_drv_level_6>,
+ /* spi2_miso_m1 */
+ <4 RK_PA4 8 &pcfg_pull_up_drv_level_6>,
+ /* spi2_mosi_m1 */
+ <4 RK_PA5 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs0: spi2m1-cs0 {
+ rockchip,pins =
+ /* spi2_cs0_m1 */
+ <4 RK_PA7 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs1: spi2m1-cs1 {
+ rockchip,pins =
+ /* spi2_cs1_m1 */
+ <4 RK_PB0 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_pins: spi2m2-pins {
+ rockchip,pins =
+ /* spi2_clk_m2 */
+ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
+ /* spi2_miso_m2 */
+ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosi_m2 */
+ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_cs0: spi2m2-cs0 {
+ rockchip,pins =
+ /* spi2_cs0_m2 */
+ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_cs1: spi2m2-cs1 {
+ rockchip,pins =
+ /* spi2_cs1_m2 */
+ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m1_pins: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clk_m1 */
+ <4 RK_PB7 8 &pcfg_pull_up_drv_level_6>,
+ /* spi3_miso_m1 */
+ <4 RK_PB5 8 &pcfg_pull_up_drv_level_6>,
+ /* spi3_mosi_m1 */
+ <4 RK_PB6 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs0: spi3m1-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m1 */
+ <4 RK_PC0 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs1: spi3m1-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m1 */
+ <4 RK_PC1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_pins: spi3m2-pins {
+ rockchip,pins =
+ /* spi3_clk_m2 */
+ <0 RK_PD3 8 &pcfg_pull_up_drv_level_6>,
+ /* spi3_miso_m2 */
+ <0 RK_PD0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi3_mosi_m2 */
+ <0 RK_PD2 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_cs0: spi3m2-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m2 */
+ <0 RK_PD4 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_cs1: spi3m2-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m2 */
+ <0 RK_PD5 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m3_pins: spi3m3-pins {
+ rockchip,pins =
+ /* spi3_clk_m3 */
+ <3 RK_PD0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi3_miso_m3 */
+ <3 RK_PC6 8 &pcfg_pull_up_drv_level_6>,
+ /* spi3_mosi_m3 */
+ <3 RK_PC7 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m3_cs0: spi3m3-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m3 */
+ <3 RK_PC4 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi3m3_cs1: spi3m3-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m3 */
+ <3 RK_PC5 8 &pcfg_pull_up_drv_level_6>;
+ };
+ };
+
+ spi4 {
+ /omit-if-no-ref/
+ spi4m0_pins: spi4m0-pins {
+ rockchip,pins =
+ /* spi4_clk_m0 */
+ <1 RK_PC2 8 &pcfg_pull_up_drv_level_6>,
+ /* spi4_miso_m0 */
+ <1 RK_PC0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi4_mosi_m0 */
+ <1 RK_PC1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_cs0: spi4m0-cs0 {
+ rockchip,pins =
+ /* spi4_cs0_m0 */
+ <1 RK_PC3 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_cs1: spi4m0-cs1 {
+ rockchip,pins =
+ /* spi4_cs1_m0 */
+ <1 RK_PC4 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_pins: spi4m1-pins {
+ rockchip,pins =
+ /* spi4_clk_m1 */
+ <3 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
+ /* spi4_miso_m1 */
+ <3 RK_PA0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi4_mosi_m1 */
+ <3 RK_PA1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_cs0: spi4m1-cs0 {
+ rockchip,pins =
+ /* spi4_cs0_m1 */
+ <3 RK_PA3 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_cs1: spi4m1-cs1 {
+ rockchip,pins =
+ /* spi4_cs1_m1 */
+ <3 RK_PA4 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_pins: spi4m2-pins {
+ rockchip,pins =
+ /* spi4_clk_m2 */
+ <1 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
+ /* spi4_miso_m2 */
+ <1 RK_PA0 8 &pcfg_pull_up_drv_level_6>,
+ /* spi4_mosi_m2 */
+ <1 RK_PA1 8 &pcfg_pull_up_drv_level_6>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_cs0: spi4m2-cs0 {
+ rockchip,pins =
+ /* spi4_cs0_m2 */
+ <1 RK_PA3 8 &pcfg_pull_up_drv_level_6>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm1_shut: tsadcm1-shut {
+ rockchip,pins =
+ /* tsadcm1_shut */
+ <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shut: tsadc-shut {
+ rockchip,pins =
+ /* tsadc_shut */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shut_org: tsadc-shut-org {
+ rockchip,pins =
+ /* tsadc_shut_org */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PC4 4 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PC5 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <0 RK_PB0 4 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <0 RK_PB1 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m2_xfer: uart0m2-xfer {
+ rockchip,pins =
+ /* uart0_rx_m2 */
+ <4 RK_PA4 10 &pcfg_pull_up>,
+ /* uart0_tx_m2 */
+ <4 RK_PA3 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ /* uart0_ctsn */
+ <0 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ /* uart0_rtsn */
+ <0 RK_PC6 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <1 RK_PB7 10 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <1 RK_PB6 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <1 RK_PD7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <1 RK_PD6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_xfer: uart1m2-xfer {
+ rockchip,pins =
+ /* uart1_rx_m2 */
+ <0 RK_PD2 10 &pcfg_pull_up>,
+ /* uart1_tx_m2 */
+ <0 RK_PD1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_ctsn: uart1m2-ctsn {
+ rockchip,pins =
+ /* uart1m2_ctsn */
+ <0 RK_PD0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_rtsn: uart1m2-rtsn {
+ rockchip,pins =
+ /* uart1m2_rtsn */
+ <0 RK_PC7 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PB6 10 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <4 RK_PD1 10 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <4 RK_PD0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_xfer: uart2m2-xfer {
+ rockchip,pins =
+ /* uart2_rx_m2 */
+ <3 RK_PB2 10 &pcfg_pull_up>,
+ /* uart2_tx_m2 */
+ <3 RK_PB1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2_ctsn: uart2-ctsn {
+ rockchip,pins =
+ /* uart2_ctsn */
+ <3 RK_PB4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2_rtsn: uart2-rtsn {
+ rockchip,pins =
+ /* uart2_rtsn */
+ <3 RK_PB3 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <1 RK_PC0 10 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <1 RK_PC1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <3 RK_PB6 10 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <3 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_xfer: uart3m2-xfer {
+ rockchip,pins =
+ /* uart3_rx_m2 */
+ <4 RK_PA6 10 &pcfg_pull_up>,
+ /* uart3_tx_m2 */
+ <4 RK_PA5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3_ctsn: uart3-ctsn {
+ rockchip,pins =
+ /* uart3_ctsn */
+ <1 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3_rtsn: uart3-rtsn {
+ rockchip,pins =
+ /* uart3_rtsn */
+ <1 RK_PC2 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <1 RK_PD3 10 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <1 RK_PD2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rx_m1 */
+ <3 RK_PD0 10 &pcfg_pull_up>,
+ /* uart4_tx_m1 */
+ <3 RK_PD1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m2_xfer: uart4m2-xfer {
+ rockchip,pins =
+ /* uart4_rx_m2 */
+ <1 RK_PB2 10 &pcfg_pull_up>,
+ /* uart4_tx_m2 */
+ <1 RK_PB3 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4_ctsn: uart4-ctsn {
+ rockchip,pins =
+ /* uart4_ctsn */
+ <1 RK_PC7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4_rtsn: uart4-rtsn {
+ rockchip,pins =
+ /* uart4_rtsn */
+ <1 RK_PC5 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <4 RK_PD4 10 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <4 RK_PD5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <4 RK_PD2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <4 RK_PD3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <3 RK_PC5 10 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <3 RK_PC4 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <2 RK_PA2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <2 RK_PA3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_xfer: uart5m2-xfer {
+ rockchip,pins =
+ /* uart5_rx_m2 */
+ <2 RK_PD4 10 &pcfg_pull_up>,
+ /* uart5_tx_m2 */
+ <2 RK_PD5 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <1 RK_PA0 10 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <1 RK_PA1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_ctsn: uart6m1-ctsn {
+ rockchip,pins =
+ /* uart6m1_ctsn */
+ <1 RK_PA3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_rtsn: uart6m1-rtsn {
+ rockchip,pins =
+ /* uart6m1_rtsn */
+ <1 RK_PA2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_xfer: uart6m2-xfer {
+ rockchip,pins =
+ /* uart6_rx_m2 */
+ <1 RK_PD1 10 &pcfg_pull_up>,
+ /* uart6_tx_m2 */
+ <1 RK_PD0 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <3 RK_PC1 10 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <3 RK_PC0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_ctsn: uart7m1-ctsn {
+ rockchip,pins =
+ /* uart7m1_ctsn */
+ <3 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_rtsn: uart7m1-rtsn {
+ rockchip,pins =
+ /* uart7m1_rtsn */
+ <3 RK_PC2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m2_xfer: uart7m2-xfer {
+ rockchip,pins =
+ /* uart7_rx_m2 */
+ <1 RK_PB4 10 &pcfg_pull_up>,
+ /* uart7_tx_m2 */
+ <1 RK_PB5 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rx_m0 */
+ <4 RK_PB1 10 &pcfg_pull_up>,
+ /* uart8_tx_m0 */
+ <4 RK_PB0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <4 RK_PB3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <4 RK_PB2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rx_m1 */
+ <3 RK_PA3 10 &pcfg_pull_up>,
+ /* uart8_tx_m1 */
+ <3 RK_PA2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_ctsn: uart8m1-ctsn {
+ rockchip,pins =
+ /* uart8m1_ctsn */
+ <3 RK_PA5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_rtsn: uart8m1-rtsn {
+ rockchip,pins =
+ /* uart8m1_rtsn */
+ <3 RK_PA4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8_xfer: uart8-xfer {
+ rockchip,pins =
+ /* uart8_rx_ */
+ <4 RK_PB1 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rx_m1 */
+ <4 RK_PB5 10 &pcfg_pull_up>,
+ /* uart9_tx_m1 */
+ <4 RK_PB4 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_ctsn: uart9m1-ctsn {
+ rockchip,pins =
+ /* uart9m1_ctsn */
+ <4 RK_PA1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_rtsn: uart9m1-rtsn {
+ rockchip,pins =
+ /* uart9m1_rtsn */
+ <4 RK_PA0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_xfer: uart9m2-xfer {
+ rockchip,pins =
+ /* uart9_rx_m2 */
+ <3 RK_PD4 10 &pcfg_pull_up>,
+ /* uart9_tx_m2 */
+ <3 RK_PD5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_ctsn: uart9m2-ctsn {
+ rockchip,pins =
+ /* uart9m2_ctsn */
+ <3 RK_PD3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_rtsn: uart9m2-rtsn {
+ rockchip,pins =
+ /* uart9m2_rtsn */
+ <3 RK_PD2 10 &pcfg_pull_none>;
+ };
+ };
+
+ vop {
+ /omit-if-no-ref/
+ vop_pins: vop-pins {
+ rockchip,pins =
+ /* vop_post_empty */
+ <1 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+ bt656 {
+ /omit-if-no-ref/
+ bt656_pins: bt656-pins {
+ rockchip,pins =
+ /* bt1120_clkout */
+ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d0 */
+ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d1 */
+ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d2 */
+ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d3 */
+ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d4 */
+ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d5 */
+ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d6 */
+ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d7 */
+ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ gpio-func {
+ /omit-if-no-ref/
+ tsadc_gpio_func: tsadc-gpio-func {
+ rockchip,pins =
+ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi (revision 151)
@@ -0,0 +1,777 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&spi2 {
+ status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+
+ rk806master: rk806master@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default", "pmic-power-off";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-1 = <&rk806_dvs1_pwrdn>;
+
+ /* 2800mv-3500mv */
+ low_voltage_threshold = <3000>;
+ /* 2700mv-3400mv */
+ shutdown_voltage_threshold = <2700>;
+ /* 140 160 */
+ shutdown_temperture_threshold = <160>;
+ hotdie_temperture_threshold = <115>;
+
+ /* 0: restart PMU;
+ * 1: reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode;
+ * 2: Reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode,
+ * and simultaneously pull down the RESETB PIN for 5mS before releasing
+ */
+ pmic-reset-func = <1>;
+
+ /* PWRON_ON_TIME: 0:500mS; 1:20mS */
+ pwron-on-time-20ms;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc5v0_sys>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ pwrkey {
+ status = "okay";
+ };
+
+ pinctrl_rk806: pinctrl_rk806 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: rk806_dvs1_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: rk806_dvs1_slp {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: rk806_dvs1_rst {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_null: rk806_dvs2_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_slp: rk806_dvs2_slp {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: rk806_dvs2_rst {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: rk806_dvs2_dvs {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: rk806_dvs2_gpio {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_null: rk806_dvs3_null {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_slp: rk806_dvs3_slp {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: rk806_dvs3_rst {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: rk806_dvs3_dvs {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: rk806_dvs3_gpio {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+ };
+
+ regulators {
+ vdd_gpu_s0: DCDC_REG1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu_mem_s0: DCDC_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+ regulator-name = "vdd_gpu_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_mem_s0: DCDC_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: DCDC_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vdd_vdenc_mem_s0: DCDC_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd2_ddr_s3: DCDC_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: DCDC_REG10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+
+ avcc_1v8_s0: PLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd1_1v8_ddr_s3: PLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd1_1v8_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s3: PLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3_s0: PLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: PLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ master_pldo6_s3: PLDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "master_pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: NLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd2l_0v9_ddr_s3: NLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdd2l_0v9_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ master_nldo3: NLDO_REG3 {
+ regulator-name = "master_nldo3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v75_s0: NLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: NLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ rk806slave: rk806slave@1 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x01>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default", "pmic-sleep";
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
+ pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
+
+ /* 0: restart PMU;
+ * 1: reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode;
+ * 2: Reset all the power off reset registers,
+ * forcing the state to switch to ACTIVE mode,
+ * and simultaneously pull down the RESETB PIN for 5mS before releasing
+ */
+ pmic-reset-func = <1>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ pwrkey {
+ status = "disabled";
+ };
+
+ pinctrl_slave_rk806: pinctrl_slave_rk806 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_slave_dvs1_null: rk806_slave_dvs1_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs1_slp: rk806_slave_dvs1_slp {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs1_rst: rk806_slave_dvs1_rst {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs2_null: rk806_slave_dvs2_null {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs2_slp: rk806_slave_dvs2_slp {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs2_rst: rk806_slave_dvs2_rst {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_slave_dvs3_null: rk806_slave_dvs3_null {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs3_slp: rk806_slave_dvs3_slp {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_slave_dvs3_rst: rk806_slave_dvs3_rst {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+ };
+
+ regulators {
+ vdd_cpu_big1_s0: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big0_s0: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_cpu_big1_mem_s0: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big1_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+
+ vdd_cpu_big0_mem_s0: DCDC_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big0_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: DCDC_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_mem_s0: DCDC_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_mem_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddq_ddr_s0: DCDC_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: DCDC_REG10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_cam_s0: PLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_1v8_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd1v8_ddr_pll_s0: PLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd1v8_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_1v8_pll_s0: PLDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_1v8_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_sd_s0: PLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_2v8_cam_s0: PLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_2v8_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: PLDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_pll_s0: NLDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_0v75_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_pll_s0: NLDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ slave_nldo3: NLDO_REG3 {
+ regulator-name = "slave_nldo3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_cam_s0: NLDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_1v2_cam_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_s0: NLDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "avdd_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rk3588s.dtsi (revision 151)
@@ -0,0 +1,5896 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3588-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/rk3588-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+#include <dt-bindings/suspend/rockchip-rk3588.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3588";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ csi2dcphy0 = &csi2_dcphy0;
+ csi2dcphy1 = &csi2_dcphy1;
+ csi2dphy0 = &csi2_dphy0;
+ csi2dphy1 = &csi2_dphy1;
+ csi2dphy2 = &csi2_dphy2;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ ethernet1 = &gmac1;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ rkcif_mipi_lvds0= &rkcif_mipi_lvds;
+ rkcif_mipi_lvds1= &rkcif_mipi_lvds1;
+ rkcif_mipi_lvds2= &rkcif_mipi_lvds2;
+ rkcif_mipi_lvds3= &rkcif_mipi_lvds3;
+ rkvenc0 = &rkvenc0;
+ rkvenc1 = &rkvenc1;
+ jpege0 = &jpege0;
+ jpege1 = &jpege1;
+ jpege2 = &jpege2;
+ jpege3 = &jpege3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ spi5 = &sfc;
+ hdcp0 = &hdcp0;
+ hdcp1 = &hdcp1;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ spll: spll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <702000000>;
+ clock-output-names = "spll";
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ hclk_vo1: hclk_vo1@fd7c08ec {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08ec 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VO1USB_TOP_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08b0 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_vo0: hclk_vo0@fd7c08dc {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08dc 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VOP_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_usb: hclk_usb@fd7c08a8 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08a8 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VO1USB_TOP_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_nvm: hclk_nvm@fd7c087c {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c087c 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_NVM_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_usb: aclk_usb@fd7c08a8 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08a8 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VO1USB_TOP_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_isp1_pre: hclk_isp1_pre@fd7c0868 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c0868 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VI_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_isp1_pre: aclk_isp1_pre@fd7c0868 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c0868 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VI_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08a0 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08a0 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08a4 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08a4 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08b0 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08c0 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_RKVENC0>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08c0 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_RKVENC0>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08dc 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VOP_LOW_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c08ec 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VO1USB_TOP_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ pclk_av1_pre: pclk_av1_pre@fd7c0910 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c0910 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru HCLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_av1_pre: aclk_av1_pre@fd7c0910 {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c0910 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VDPU_ROOT>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_sdio_pre: hclk_sdio_pre@fd7c092c {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0 0xfd7c092c 0 0x10>;
+ clock-names = "link";
+ clocks = <&hclk_nvm>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ pclk_vo0_grf: pclk_vo0_grf@fd7c08dc {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0x0 0xfd7c08dc 0x0 0x4>;
+ clocks = <&hclk_vo0>;
+ clock-names = "link";
+ #clock-cells = <0>;
+ };
+
+ pclk_vo1_grf: pclk_vo1_grf@fd7c08ec {
+ compatible = "rockchip,rk3588-clock-gate-link";
+ reg = <0x0 0xfd7c08ec 0x0 0x4>;
+ clocks = <&hclk_vo1>;
+ clock-names = "link";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_l0>;
+ };
+ core1 {
+ cpu = <&cpu_l1>;
+ };
+ core2 {
+ cpu = <&cpu_l2>;
+ };
+ core3 {
+ cpu = <&cpu_l3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu_b0>;
+ };
+ core1 {
+ cpu = <&cpu_b1>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&cpu_b2>;
+ };
+ core1 {
+ cpu = <&cpu_b3>;
+ };
+ };
+ };
+
+ cpu_l0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l0>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <100>;
+ };
+
+ cpu_l1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ cpu_l2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l2>;
+ };
+
+ cpu_l3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l3>;
+ };
+
+ cpu_b0: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b0>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <300>;
+ };
+
+ cpu_b1: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b1>;
+ };
+
+ cpu_b2: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ operating-points-v2 = <&cluster2_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b2>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <300>;
+ };
+
+ cpu_b3: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ operating-points-v2 = <&cluster2_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b3>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <100>;
+ exit-latency-us = <120>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_cache_l0: l2-cache-l0 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l1: l2-cache-l1 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l2: l2-cache-l2 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l3: l2-cache-l3 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b0: l2-cache-b0 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b1: l2-cache-b1 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b2: l2-cache-b2 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b3: l2-cache-b3 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <3145728>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
+ };
+ };
+
+ cluster0_opp_table: cluster0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ nvmem-cells = <&cpul_leakage>, <&specification_serial_number>;
+ nvmem-cell-names = "leakage", "specification_serial_number";
+ rockchip,supported-hw;
+ rockchip,opp-shared-dsu;
+
+ rockchip,pvtm-voltage-sel = <
+ 0 1410 0
+ 1411 1434 1
+ 1435 1458 2
+ 1459 1482 3
+ 1483 1506 4
+ 1507 1530 5
+ 1531 9999 6
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x64>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <1416000>;
+ rockchip,pvtm-volt = <750000>;
+ rockchip,pvtm-ref-temp = <25>;
+ rockchip,pvtm-temp-prop = <244 244>;
+ rockchip,pvtm-thermal-zone = "soc-thermal";
+
+ rockchip,grf = <&litcore_grf>;
+
+ rockchip,reboot-freq = <1416000>;
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+ rockchip,high-temp = <85000>;
+ rockchip,high-temp-max-freq = <1608000>;
+
+ opp-408000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <675000 675000 950000>,
+ <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-600000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 950000>,
+ <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <675000 675000 950000>,
+ <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 950000>,
+ <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <712500 712500 950000>,
+ <712500 712500 950000>;
+ opp-microvolt-L1 = <700000 700000 950000>,
+ <700000 700000 950000>;
+ opp-microvolt-L2 = <700000 700000 950000>,
+ <700000 700000 950000>;
+ opp-microvolt-L3 = <687500 687500 950000>,
+ <687500 687500 950000>;
+ opp-microvolt-L4 = <675000 675000 950000>,
+ <675000 675000 950000>;
+ opp-microvolt-L5 = <675000 675000 950000>,
+ <675000 675000 950000>;
+ opp-microvolt-L6 = <675000 675000 950000>,
+ <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <762500 762500 950000>,
+ <762500 762500 950000>;
+ opp-microvolt-L1 = <750000 750000 950000>,
+ <750000 750000 950000>;
+ opp-microvolt-L2 = <737500 737500 950000>,
+ <737500 737500 950000>;
+ opp-microvolt-L3 = <725000 725000 950000>,
+ <725000 725000 950000>;
+ opp-microvolt-L4 = <725000 725000 950000>,
+ <725000 725000 950000>;
+ opp-microvolt-L5 = <712500 712500 950000>,
+ <712500 712500 950000>;
+ opp-microvolt-L6 = <712500 712500 950000>,
+ <712500 712500 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-1608000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <850000 850000 950000>,
+ <850000 850000 950000>;
+ opp-microvolt-L1 = <837500 837500 950000>,
+ <837500 837500 950000>;
+ opp-microvolt-L2 = <825000 825000 950000>,
+ <825000 825000 950000>;
+ opp-microvolt-L3 = <812500 812500 950000>,
+ <812500 812500 950000>;
+ opp-microvolt-L4 = <800000 800000 950000>,
+ <800000 800000 950000>;
+ opp-microvolt-L5 = <800000 800000 950000>,
+ <800000 800000 950000>;
+ opp-microvolt-L6 = <787500 787500 950000>,
+ <787500 787500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-supported-hw = <0xfd 0xffff>;
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <950000 950000 950000>,
+ <950000 950000 950000>;
+ opp-microvolt-L1 = <937500 937500 950000>,
+ <937500 937500 950000>;
+ opp-microvolt-L2 = <925000 925000 950000>,
+ <925000 925000 950000>;
+ opp-microvolt-L3 = <912500 912500 950000>,
+ <912500 912500 950000>;
+ opp-microvolt-L4 = <900000 900000 950000>,
+ <900000 900000 950000>;
+ opp-microvolt-L5 = <887500 887500 950000>,
+ <887500 887500 950000>;
+ opp-microvolt-L6 = <875000 875000 950000>,
+ <875000 875000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp_table: cluster1-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ nvmem-cells = <&cpub0_leakage>, <&specification_serial_number>;
+ nvmem-cell-names = "leakage", "specification_serial_number";
+ rockchip,supported-hw;
+
+ rockchip,pvtm-voltage-sel = <
+ 0 1595 0
+ 1596 1615 1
+ 1616 1640 2
+ 1641 1675 3
+ 1676 1710 4
+ 1711 1743 5
+ 1744 1776 6
+ 1777 9999 7
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x18>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <1608000>;
+ rockchip,pvtm-volt = <750000>;
+ rockchip,pvtm-ref-temp = <25>;
+ rockchip,pvtm-temp-prop = <270 270>;
+ rockchip,pvtm-thermal-zone = "soc-thermal";
+ rockchip,pvtm-low-len-sel = <3>;
+
+ rockchip,grf = <&bigcore0_grf>;
+ volt-mem-read-margin = <
+ 855000 1
+ 765000 2
+ 675000 3
+ 495000 4
+ >;
+ low-volt-mem-read-margin = <4>;
+ intermediate-threshold-freq = <1008000>; /* KHz */
+ rockchip,idle-threshold-freq = <2208000>; /* KHz */
+ rockchip,reboot-freq = <1800000>; /* KHz */
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+ rockchip,high-temp = <85000>;
+ rockchip,high-temp-max-freq = <2208000>;
+
+ opp-408000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>,
+ <725000 725000 1000000>;
+ opp-microvolt-L2 = <712500 712500 1000000>,
+ <712500 712500 1000000>;
+ opp-microvolt-L3 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ opp-microvolt-L4 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ opp-microvolt-L5 = <687500 687500 1000000>,
+ <687500 687500 1000000>;
+ opp-microvolt-L6 = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ opp-microvolt-L7 = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>,
+ <762500 762500 1000000>;
+ opp-microvolt-L2 = <750000 750000 1000000>,
+ <750000 750000 1000000>;
+ opp-microvolt-L3 = <737500 737500 1000000>,
+ <737500 737500 1000000>;
+ opp-microvolt-L4 = <725000 725000 1000000>,
+ <725000 725000 1000000>;
+ opp-microvolt-L5 = <712500 712500 1000000>,
+ <712500 712500 1000000>;
+ opp-microvolt-L6 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ opp-microvolt-L7 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>,
+ <850000 850000 1000000>;
+ opp-microvolt-L1 = <837500 837500 1000000>,
+ <837500 837500 1000000>;
+ opp-microvolt-L2 = <825000 825000 1000000>,
+ <825000 825000 1000000>;
+ opp-microvolt-L3 = <812500 812500 1000000>,
+ <812500 812500 1000000>;
+ opp-microvolt-L4 = <800000 800000 1000000>,
+ <800000 800000 1000000>;
+ opp-microvolt-L5 = <787500 787500 1000000>,
+ <787500 787500 1000000>;
+ opp-microvolt-L6 = <775000 775000 1000000>,
+ <775000 775000 1000000>;
+ opp-microvolt-L7 = <762500 762500 1000000>,
+ <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>,
+ <925000 925000 1000000>;
+ opp-microvolt-L1 = <912500 912500 1000000>,
+ <912500 912500 1000000>;
+ opp-microvolt-L2 = <900000 900000 1000000>,
+ <900000 900000 1000000>;
+ opp-microvolt-L3 = <887500 887500 1000000>,
+ <887500 887500 1000000>;
+ opp-microvolt-L4 = <875000 875000 1000000>,
+ <875000 875000 1000000>;
+ opp-microvolt-L5 = <862500 862500 1000000>,
+ <862500 862500 1000000>;
+ opp-microvolt-L6 = <850000 850000 1000000>,
+ <850000 850000 1000000>;
+ opp-microvolt-L7 = <837500 837500 1000000>,
+ <837500 837500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>,
+ <987500 987500 1000000>;
+ opp-microvolt-L1 = <975000 975000 1000000>,
+ <975000 975000 1000000>;
+ opp-microvolt-L2 = <962500 962500 1000000>,
+ <962500 962500 1000000>;
+ opp-microvolt-L3 = <950000 950000 1000000>,
+ <950000 950000 1000000>;
+ opp-microvolt-L4 = <962500 962500 1000000>,
+ <962500 962500 1000000>;
+ opp-microvolt-L5 = <950000 950000 1000000>,
+ <950000 950000 1000000>;
+ opp-microvolt-L6 = <925000 925000 1000000>,
+ <925000 925000 1000000>;
+ opp-microvolt-L7 = <912500 912500 1000000>,
+ <912500 912500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2256000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2256000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2304000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2352000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2352000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster2_opp_table: cluster2-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ nvmem-cells = <&cpub1_leakage>, <&specification_serial_number>;
+ nvmem-cell-names = "leakage", "specification_serial_number";
+ rockchip,supported-hw;
+
+ rockchip,pvtm-voltage-sel = <
+ 0 1595 0
+ 1596 1615 1
+ 1616 1640 2
+ 1641 1675 3
+ 1676 1710 4
+ 1711 1743 5
+ 1744 1776 6
+ 1777 9999 7
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x18>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <1608000>;
+ rockchip,pvtm-volt = <750000>;
+ rockchip,pvtm-ref-temp = <25>;
+ rockchip,pvtm-temp-prop = <270 270>;
+ rockchip,pvtm-thermal-zone = "soc-thermal";
+ rockchip,pvtm-low-len-sel = <3>;
+
+ rockchip,grf = <&bigcore1_grf>;
+ volt-mem-read-margin = <
+ 855000 1
+ 765000 2
+ 675000 3
+ 495000 4
+ >;
+ low-volt-mem-read-margin = <4>;
+ intermediate-threshold-freq = <1008000>; /* KHz */
+ rockchip,idle-threshold-freq = <2208000>; /* KHz */
+ rockchip,reboot-freq = <1800000>; /* KHz */
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+ rockchip,high-temp = <85000>;
+ rockchip,high-temp-max-freq = <2208000>;
+
+ opp-408000000 {
+ opp-supported-hw = <0xff 0x0ffff>;
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>,
+ <725000 725000 1000000>;
+ opp-microvolt-L2 = <712500 712500 1000000>,
+ <712500 712500 1000000>;
+ opp-microvolt-L3 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ opp-microvolt-L4 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ opp-microvolt-L5 = <687500 687500 1000000>,
+ <687500 687500 1000000>;
+ opp-microvolt-L6 = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ opp-microvolt-L7 = <675000 675000 1000000>,
+ <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>,
+ <762500 762500 1000000>;
+ opp-microvolt-L2 = <750000 750000 1000000>,
+ <750000 750000 1000000>;
+ opp-microvolt-L3 = <737500 737500 1000000>,
+ <737500 737500 1000000>;
+ opp-microvolt-L4 = <725000 725000 1000000>,
+ <725000 725000 1000000>;
+ opp-microvolt-L5 = <712500 712500 1000000>,
+ <712500 712500 1000000>;
+ opp-microvolt-L6 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ opp-microvolt-L7 = <700000 700000 1000000>,
+ <700000 700000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>,
+ <850000 850000 1000000>;
+ opp-microvolt-L1 = <837500 837500 1000000>,
+ <837500 837500 1000000>;
+ opp-microvolt-L2 = <825000 825000 1000000>,
+ <825000 825000 1000000>;
+ opp-microvolt-L3 = <812500 812500 1000000>,
+ <812500 812500 1000000>;
+ opp-microvolt-L4 = <800000 800000 1000000>,
+ <800000 800000 1000000>;
+ opp-microvolt-L5 = <787500 787500 1000000>,
+ <787500 787500 1000000>;
+ opp-microvolt-L6 = <775000 775000 1000000>,
+ <775000 775000 1000000>;
+ opp-microvolt-L7 = <762500 762500 1000000>,
+ <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>,
+ <925000 925000 1000000>;
+ opp-microvolt-L1 = <912500 912500 1000000>,
+ <912500 912500 1000000>;
+ opp-microvolt-L2 = <900000 900000 1000000>,
+ <900000 900000 1000000>;
+ opp-microvolt-L3 = <887500 887500 1000000>,
+ <887500 887500 1000000>;
+ opp-microvolt-L4 = <875000 875000 1000000>,
+ <875000 875000 1000000>;
+ opp-microvolt-L5 = <862500 862500 1000000>,
+ <862500 862500 1000000>;
+ opp-microvolt-L6 = <850000 850000 1000000>,
+ <850000 850000 1000000>;
+ opp-microvolt-L7 = <837500 837500 1000000>,
+ <837500 837500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>,
+ <987500 987500 1000000>;
+ opp-microvolt-L3 = <975000 975000 1000000>,
+ <975000 975000 1000000>;
+ opp-microvolt-L4 = <962500 962500 1000000>,
+ <962500 962500 1000000>;
+ opp-microvolt-L5 = <950000 950000 1000000>,
+ <950000 950000 1000000>;
+ opp-microvolt-L6 = <925000 925000 1000000>,
+ <925000 925000 1000000>;
+ opp-microvolt-L7 = <912500 912500 1000000>,
+ <912500 912500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2256000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2256000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2304000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2352000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2352000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-supported-hw = <0xff 0xffff>;
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>,
+ <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ arm_pmu: arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>,
+ <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
+ };
+
+ cpuinfo {
+ compatible = "rockchip,cpuinfo";
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
+ };
+
+ csi2_dcphy0: csi2-dcphy0 {
+ compatible = "rockchip,rk3588-csi2-dcphy";
+ phys = <&mipi_dcphy0>;
+ phy-names = "dcphy";
+ status = "disabled";
+ };
+
+ csi2_dcphy1: csi2-dcphy1 {
+ compatible = "rockchip,rk3588-csi2-dcphy";
+ phys = <&mipi_dcphy1>;
+ phy-names = "dcphy";
+ status = "disabled";
+ };
+
+ /* dphy0 full mode */
+ csi2_dphy0: csi2-dphy0 {
+ compatible = "rockchip,rk3568-csi2-dphy";
+ rockchip,hw = <&csi2_dphy0_hw>;
+ status = "disabled";
+ };
+
+ /* dphy0 split mode 01 */
+ csi2_dphy1: csi2-dphy1 {
+ compatible = "rockchip,rk3568-csi2-dphy";
+ rockchip,hw = <&csi2_dphy0_hw>;
+ status = "disabled";
+ };
+
+ /* dphy0 split mode 23 */
+ csi2_dphy2: csi2-dphy2 {
+ compatible = "rockchip,rk3568-csi2-dphy";
+ rockchip,hw = <&csi2_dphy0_hw>;
+ status = "disabled";
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+
+ route {
+ route_dp0: route-dp0 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp1_out_dp0>;
+ };
+
+ route_dsi0: route-dsi0 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp3_out_dsi0>;
+ };
+
+ route_dsi1: route-dsi1 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp3_out_dsi1>;
+ };
+
+ route_edp0: route-edp0 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp2_out_edp0>;
+ };
+
+ route_edp1: route-edp1 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ };
+
+ route_hdmi0: route-hdmi0 {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp0_out_hdmi0>;
+ };
+
+ route_rgb: route-rgb {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vp3_out_rgb>;
+ };
+ };
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3588-dmc";
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "complete";
+ devfreq-events = <&dfi>;
+ clocks = <&scmi_clk 4>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ system-status-level = <
+ /*system status freq level*/
+ SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH
+ SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
+ SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
+ SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
+ SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
+ SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
+ SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
+ SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
+ SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
+ SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
+ SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
+ >;
+ auto-freq-en = <1>;
+ status = "disabled";
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ nvmem-cells = <&log_leakage>;
+ nvmem-cell-names = "leakage";
+ rockchip,leakage-voltage-sel = <
+ 1 31 0
+ 32 44 1
+ 45 57 2
+ 58 254 3
+ >;
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+
+ opp-528000000 {
+ opp-hz = /bits/ 64 <528000000>;
+ opp-microvolt = <675000 675000 875000>,
+ <725000 725000 750000>;
+ opp-microvolt-L1 = <675000 675000 875000>,
+ <700000 700000 750000>;
+ opp-microvolt-L2 = <675000 675000 875000>,
+ <687500 687500 750000>;
+ opp-microvolt-L3 = <675000 675000 875000>,
+ <675000 675000 750000>;
+ };
+ opp-1068000000 {
+ opp-hz = /bits/ 64 <1068000000>;
+ opp-microvolt = <725000 725000 875000>,
+ <737500 737500 750000>;
+ opp-microvolt-L1 = <700000 700000 875000>,
+ <712500 712500 750000>;
+ opp-microvolt-L2 = <675000 675000 875000>,
+ <700000 700000 750000>;
+ opp-microvolt-L3 = <675000 675000 875000>,
+ <687500 687500 750000>;
+ };
+ opp-1560000000 {
+ opp-hz = /bits/ 64 <1560000000>;
+ opp-microvolt = <800000 800000 875000>,
+ <750000 750000 750000>;
+ opp-microvolt-L1 = <775000 775000 875000>,
+ <725000 725000 750000>;
+ opp-microvolt-L2 = <750000 750000 875000>,
+ <712500 712500 750000>;
+ opp-microvolt-L3 = <725000 725000 875000>,
+ <700000 700000 750000>;
+ };
+ opp-2750000000 {
+ opp-hz = /bits/ 64 <2750000000>;
+ opp-microvolt = <875000 875000 875000>,
+ <750000 750000 750000>;
+ opp-microvolt-L1 = <850000 850000 875000>,
+ <750000 750000 750000>;
+ opp-microvolt-L2 = <837500 837500 875000>,
+ <725000 725000 750000>;
+ opp-microvolt-L3 = <825000 820000 875000>,
+ <700000 700000 750000>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&scmi_shmem>;
+ arm,smc-id = <0x82000010>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>,
+ <&scmi_clk SCMI_CLK_CPUB01>,
+ <&scmi_clk SCMI_CLK_CPUB23>;
+ assigned-clock-rates = <816000000>,
+ <816000000>,
+ <816000000>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ sdei: sdei {
+ compatible = "arm,sdei-1.0";
+ method = "smc";
+ };
+ };
+
+ jpege_ccu: jpege-ccu {
+ compatible = "rockchip,vpu-jpege-ccu";
+ status = "disabled";
+ };
+
+ mpp_srv: mpp-srv {
+ compatible = "rockchip,mpp-service";
+ rockchip,taskqueue-count = <12>;
+ rockchip,resetgroup-count = <1>;
+ status = "disabled";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ rkcif_dvp: rkcif-dvp {
+ compatible = "rockchip,rkcif-dvp";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_dvp_sditf: rkcif-dvp-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_dvp>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds: rkcif-mipi-lvds {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkisp0_vir0: rkisp0-vir0 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp0>;
+ /*
+ * dual isp process image case
+ * other rkisp hw and virtual nodes should disabled
+ * rockchip,hw = <&rkisp_unite>;
+ */
+ status = "disabled";
+ };
+
+ rkisp0_vir1: rkisp0-vir1 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp0>;
+ status = "disabled";
+ };
+
+ rkisp0_vir2: rkisp0-vir2 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp0>;
+ status = "disabled";
+ };
+
+ rkisp0_vir3: rkisp0-vir3 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp0>;
+ status = "disabled";
+ };
+
+ rkisp1_vir0: rkisp1-vir0 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp1>;
+ status = "disabled";
+ };
+
+ rkisp1_vir1: rkisp1-vir1 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp1>;
+ status = "disabled";
+ };
+
+ rkisp1_vir2: rkisp1-vir2 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp1>;
+ status = "disabled";
+ };
+
+ rkisp1_vir3: rkisp1-vir3 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp1>;
+ status = "disabled";
+ };
+
+ rkispp0_vir0: rkispp0-vir0 {
+ compatible = "rockchip,rk3588-rkispp-vir";
+ rockchip,hw = <&rkispp0>;
+ status = "disabled";
+ };
+
+ rkispp1_vir0: rkispp1-vir0 {
+ compatible = "rockchip,rk3588-rkispp-vir";
+ rockchip,hw = <&rkispp1>;
+ status = "disabled";
+ };
+
+ rkvenc_ccu: rkvenc-ccu {
+ compatible = "rockchip,rkv-encoder-v2-ccu";
+ status = "disabled";
+ };
+
+ rockchip_suspend: rockchip-suspend {
+ compatible = "rockchip,pm-rk3588";
+ status = "disabled";
+ rockchip,sleep-debug-en = <0>;
+ rockchip,sleep-mode-config = <
+ (0
+ | RKPM_SLP_ARMOFF_LOGOFF
+ | RKPM_SLP_PMU_PMUALIVE_32K
+ | RKPM_SLP_PMU_DIS_OSC
+ | RKPM_SLP_32K_EXT
+ )
+ >;
+ rockchip,wakeup-config = <
+ (0
+ | RKPM_GPIO_WKUP_EN
+ )
+ >;
+ };
+
+ rockchip_system_monitor: rockchip-system-monitor {
+ compatible = "rockchip,system-monitor";
+
+ rockchip,thermal-zone = "soc-thermal";
+ };
+
+ thermal_zones: thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ sustainable-power = <2100>; /* milliwatts */
+
+ thermal-sensors = <&tsadc 0>;
+ trips {
+ threshold: trip-point-0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ target: trip-point-1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ soc_crit: soc-crit {
+ /* millicelsius */
+ temperature = <115000>;
+ /* millicelsius */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <1024>;
+ };
+ map1 {
+ trip = <&target>;
+ cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <1024>;
+ };
+ map2 {
+ trip = <&target>;
+ cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <1024>;
+ };
+ map3 {
+ trip = <&target>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <1024>;
+ };
+ };
+ };
+
+ bigcore0_thermal: bigcore0-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 1>;
+ };
+
+ bigcore1_thermal: bigcore1-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 2>;
+ };
+
+ little_core_thermal: littlecore-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 3>;
+ };
+
+ center_thermal: center-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 4>;
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 5>;
+ };
+
+ npu_thermal: npu-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 6>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sram@10f000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x0010f000 0x100>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ gpu: gpu@fb000000 {
+ compatible = "arm,mali-bifrost";
+ reg = <0x0 0xfb000000 0x0 0x200000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "GPU", "MMU", "JOB";
+
+ clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
+ <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>;
+ clock-names = "clk_mali", "clk_gpu_coregroup",
+ "clk_gpu_stacks", "clk_gpu";
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&power RK3588_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <2982>;
+
+ upthreshold = <30>;
+ downdifferential = <10>;
+
+ status = "disabled";
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ nvmem-cells = <&gpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ rockchip,pvtm-voltage-sel = <
+ 0 815 0
+ 816 835 1
+ 836 860 2
+ 861 885 3
+ 886 910 4
+ 911 9999 5
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x1c>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <800000>;
+ rockchip,pvtm-volt = <750000>;
+ rockchip,pvtm-ref-temp = <25>;
+ rockchip,pvtm-temp-prop = <(-135) (-135)>;
+ rockchip,pvtm-thermal-zone = "gpu-thermal";
+
+ clocks = <&cru CLK_GPU>;
+ clock-names = "clk";
+ rockchip,grf = <&gpu_grf>;
+ volt-mem-read-margin = <
+ 855000 1
+ 765000 2
+ 675000 3
+ 495000 4
+ >;
+ low-volt-mem-read-margin = <4>;
+ intermediate-threshold-freq = <400000>; /* KHz */
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+ rockchip,high-temp = <85000>;
+ rockchip,high-temp-max-freq = <800000>;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L2 = <687500 687500 850000>,
+ <687500 687500 850000>;
+ opp-microvolt-L3 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <750000 750000 850000>,
+ <750000 750000 850000>;
+ opp-microvolt-L1 = <737500 737500 850000>,
+ <737500 737500 850000>;
+ opp-microvolt-L2 = <725000 725000 850000>,
+ <725000 725000 850000>;
+ opp-microvolt-L3 = <712500 712500 850000>,
+ <712500 712500 850000>;
+ opp-microvolt-L4 = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L5 = <700000 700000 850000>,
+ <700000 700000 850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <800000 800000 850000>,
+ <800000 800000 850000>;
+ opp-microvolt-L1 = <787500 787500 850000>,
+ <787500 787500 850000>;
+ opp-microvolt-L2 = <775000 775000 850000>,
+ <775000 775000 850000>;
+ opp-microvolt-L3 = <762500 762500 850000>,
+ <762500 762500 850000>;
+ opp-microvolt-L4 = <750000 750000 850000>,
+ <750000 750000 850000>;
+ opp-microvolt-L5 = <737500 737500 850000>,
+ <737500 737500 850000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <850000 850000 850000>,
+ <850000 850000 850000>;
+ opp-microvolt-L1 = <837500 837500 850000>,
+ <837500 837500 850000>;
+ opp-microvolt-L2 = <825000 825000 850000>,
+ <825000 825000 850000>;
+ opp-microvolt-L3 = <812500 812500 850000>,
+ <812500 812500 850000>;
+ opp-microvolt-L4 = <800000 800000 850000>,
+ <800000 800000 850000>;
+ opp-microvolt-L5 = <787500 787500 850000>,
+ <787500 787500 850000>;
+ };
+ };
+
+ usbdrd3_0: usbdrd3_0 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref", "suspend", "bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_0: usb@fc000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfc000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ reset-names = "usb3-otg";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,parkmode-disable-ss-quirk;
+ quirk-skip-phy-init;
+ status = "disabled";
+ };
+ };
+
+ usb_host0_ehci: usb@fc800000 {
+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
+ reg = <0x0 0xfc800000 0x0 0x40000>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ companion = <&usb_host0_ohci>;
+ phys = <&u2phy2_host>;
+ phy-names = "usb2-phy";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@fc840000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfc840000 0x0 0x40000>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy2_host>;
+ phy-names = "usb2-phy";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@fc880000 {
+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
+ reg = <0x0 0xfc880000 0x0 0x40000>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ companion = <&usb_host1_ohci>;
+ phys = <&u2phy3_host>;
+ phy-names = "usb2-phy";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@fc8c0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfc8c0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy3_host>;
+ phy-names = "usb2-phy";
+ power-domains = <&power RK3588_PD_USB>;
+ status = "disabled";
+ };
+
+ mmu600_pcie: iommu@fc900000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfc900000 0x0 0x200000>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ mmu600_php: iommu@fcb00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfcb00000 0x0 0x200000>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ usbhost3_0: usbhost3_0 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
+ <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>;
+ clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbhost_dwc3_0: usb@fcd00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfcd00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_A_USB3OTG2>;
+ reset-names = "usb3-host";
+ dr_mode = "host";
+ phys = <&combphy2_psu PHY_TYPE_USB3>;
+ phy-names = "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
+ };
+ };
+
+ pmu0_grf: syscon@fd588000 {
+ compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd588000 0x0 0x2000>;
+
+ reboot_mode: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x80>;
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
+ mode-charge = <BOOT_CHARGING>;
+ mode-fastboot = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-ums = <BOOT_UMS>;
+ mode-panic = <BOOT_PANIC>;
+ mode-watchdog = <BOOT_WATCHDOG>;
+ };
+ };
+
+ pmu1_grf: syscon@fd58a000 {
+ compatible = "rockchip,rk3588-pmu1-grf", "syscon";
+ reg = <0x0 0xfd58a000 0x0 0x2000>;
+ };
+
+ sys_grf: syscon@fd58c000 {
+ compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd58c000 0x0 0x1000>;
+
+ rgb: rgb {
+ compatible = "rockchip,rk3588-rgb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt1120_pins>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgb_in_vp3: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp3_out_rgb>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
+ bigcore0_grf: syscon@fd590000 {
+ compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
+ reg = <0x0 0xfd590000 0x0 0x100>;
+ };
+
+ bigcore1_grf: syscon@fd592000 {
+ compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
+ reg = <0x0 0xfd592000 0x0 0x100>;
+ };
+
+ litcore_grf: syscon@fd594000 {
+ compatible = "rockchip,rk3588-litcore-grf", "syscon";
+ reg = <0x0 0xfd594000 0x0 0x100>;
+ };
+
+ dsu_grf: syscon@fd598000 {
+ compatible = "rockchip,rk3588-dsu-grf", "syscon";
+ reg = <0x0 0xfd598000 0x0 0x100>;
+ };
+
+ gpu_grf: syscon@fd5a0000 {
+ compatible = "rockchip,rk3588-gpu-grf", "syscon";
+ reg = <0x0 0xfd5a0000 0x0 0x100>;
+ };
+
+ npu_grf: syscon@fd5a2000 {
+ compatible = "rockchip,rk3588-npu-grf", "syscon";
+ reg = <0x0 0xfd5a2000 0x0 0x100>;
+ };
+
+ vop_grf: syscon@fd5a4000 {
+ compatible = "rockchip,rk3588-vop-grf", "syscon";
+ reg = <0x0 0xfd5a4000 0x0 0x2000>;
+ };
+
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&pclk_vo0_grf>;
+ };
+
+ vo1_grf: syscon@fd5a8000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a8000 0x0 0x100>;
+ clocks = <&pclk_vo1_grf>;
+ };
+
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
+ php_grf: syscon@fd5b0000 {
+ compatible = "rockchip,rk3588-php-grf", "syscon";
+ reg = <0x0 0xfd5b0000 0x0 0x1000>;
+ };
+
+ mipidphy0_grf: syscon@fd5b4000 {
+ compatible = "rockchip,mipi-dphy-grf", "syscon";
+ reg = <0x0 0xfd5b4000 0x0 0x1000>;
+ };
+
+ mipidphy1_grf: syscon@fd5b5000 {
+ compatible = "rockchip,mipi-dphy-grf", "syscon";
+ reg = <0x0 0xfd5b5000 0x0 0x1000>;
+ };
+
+ pipe_phy0_grf: syscon@fd5bc000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
+ };
+
+ pipe_phy2_grf: syscon@fd5c4000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c4000 0x0 0x100>;
+ };
+
+ usbdpphy0_grf: syscon@fd5c8000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
+ };
+
+ usb2phy0_grf: syscon@fd5d0000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2-phy@0 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x0 0x10>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ rockchip,usbctrl-grf = <&usb_grf>;
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usb2phy2_grf: syscon@fd5d8000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xfd5d8000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy2: usb2-phy@8000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x8000 0x10>;
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy2";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy2_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usb2phy3_grf: syscon@fd5dc000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xfd5dc000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy3: usb2-phy@c000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0xc000 0x10>;
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy3";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy3_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ hdptxphy0_grf: syscon@fd5e0000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e0000 0x0 0x100>;
+ };
+
+ mipidcphy0_grf: syscon@fd5e8000 {
+ compatible = "rockchip,mipi-dcphy-grf", "syscon";
+ reg = <0x0 0xfd5e8000 0x0 0x4000>;
+ };
+
+ mipidcphy1_grf: syscon@fd5ec000 {
+ compatible = "rockchip,mipi-dcphy-grf", "syscon";
+ reg = <0x0 0xfd5ec000 0x0 0x4000>;
+ };
+
+ ioc: syscon@fd5f0000 {
+ compatible = "rockchip,rk3588-ioc", "syscon";
+ reg = <0x0 0xfd5f0000 0x0 0x10000>;
+ };
+
+ cru: clock-controller@fd7c0000 {
+ compatible = "rockchip,rk3588-cru";
+ rockchip,grf = <&php_grf>;
+ reg = <0x0 0xfd7c0000 0x0 0x5c000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ assigned-clocks =
+ <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
+ <&cru PLL_NPLL>, <&cru PLL_GPLL>,
+ <&cru ACLK_CENTER_ROOT>,
+ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
+ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
+ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
+ <&cru HCLK_PMU_CM0_ROOT>,
+ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
+ <&cru CLK_GPU>;
+ assigned-clock-rates =
+ <1100000000>, <786432000>,
+ <850000000>, <1188000000>,
+ <702000000>,
+ <400000000>, <500000000>,
+ <800000000>, <100000000>,
+ <400000000>, <100000000>,
+ <200000000>,
+ <375000000>, <150000000>,
+ <200000000>;
+ };
+
+ i2c0: i2c@fd880000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfd880000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@fd890000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfd890000 0x0 0x100>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac0 6>, <&dmac0 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m1_xfer>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@fd8b0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0m0_pins>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@fd8b0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1m0_pins>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@fd8b0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2m0_pins>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@fd8b0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0030 0x0 0x10>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m0_pins>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pmu: power-management@fd8d8000 {
+ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xfd8d8000 0x0 0x400>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3588-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* These power domains are grouped by VD_NPU */
+ power-domain@RK3588_PD_NPU {
+ reg = <RK3588_PD_NPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3588_PD_NPUTOP {
+ reg = <RK3588_PD_NPUTOP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru HCLK_NPU_ROOT>,
+ <&cru PCLK_NPU_ROOT>,
+ <&cru CLK_NPU_DSU0>,
+ <&cru HCLK_NPU_CM0_ROOT>;
+ pm_qos = <&qos_npu0_mwr>,
+ <&qos_npu0_mro>,
+ <&qos_mcu_npu>;
+
+ power-domain@RK3588_PD_NPU1 {
+ reg = <RK3588_PD_NPU1>;
+ clocks = <&cru HCLK_NPU_ROOT>,
+ <&cru PCLK_NPU_ROOT>,
+ <&cru CLK_NPU_DSU0>;
+ pm_qos = <&qos_npu1>;
+ };
+ power-domain@RK3588_PD_NPU2 {
+ reg = <RK3588_PD_NPU2>;
+ clocks = <&cru HCLK_NPU_ROOT>,
+ <&cru PCLK_NPU_ROOT>,
+ <&cru CLK_NPU_DSU0>;
+ pm_qos = <&qos_npu2>;
+ };
+ };
+ };
+ /* These power domains are grouped by VD_GPU */
+ power-domain@RK3588_PD_GPU {
+ reg = <RK3588_PD_GPU>;
+ clocks = <&cru CLK_GPU>,
+ <&cru CLK_GPU_COREGROUP>,
+ <&cru CLK_GPU_STACKS>;
+ pm_qos = <&qos_gpu_m0>,
+ <&qos_gpu_m1>,
+ <&qos_gpu_m2>,
+ <&qos_gpu_m3>;
+ };
+ /* These power domains are grouped by VD_VCODEC */
+ power-domain@RK3588_PD_VCODEC {
+ reg = <RK3588_PD_VCODEC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3588_PD_RKVDEC0 {
+ reg = <RK3588_PD_RKVDEC0>;
+ clocks = <&cru HCLK_RKVDEC0>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_RKVDEC0>,
+ <&cru ACLK_RKVDEC_CCU>;
+ pm_qos = <&qos_rkvdec0>;
+ };
+ power-domain@RK3588_PD_RKVDEC1 {
+ reg = <RK3588_PD_RKVDEC1>;
+ clocks = <&cru HCLK_RKVDEC1>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_RKVDEC1>;
+ pm_qos = <&qos_rkvdec1>;
+ };
+ power-domain@RK3588_PD_VENC0 {
+ reg = <RK3588_PD_VENC0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru HCLK_RKVENC0>,
+ <&cru ACLK_RKVENC0>;
+ pm_qos = <&qos_rkvenc0_m0ro>,
+ <&qos_rkvenc0_m1ro>,
+ <&qos_rkvenc0_m2wo>;
+
+ power-domain@RK3588_PD_VENC1 {
+ reg = <RK3588_PD_VENC1>;
+ clocks = <&cru HCLK_RKVENC1>,
+ <&cru HCLK_RKVENC0>,
+ <&cru ACLK_RKVENC0>,
+ <&cru ACLK_RKVENC1>;
+ pm_qos = <&qos_rkvenc1_m0ro>,
+ <&qos_rkvenc1_m1ro>,
+ <&qos_rkvenc1_m2wo>;
+ };
+ };
+ };
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@RK3588_PD_VDPU {
+ reg = <RK3588_PD_VDPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_LOW_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_JPEG_DECODER_ROOT>,
+ <&cru ACLK_IEP2P0>,
+ <&cru HCLK_IEP2P0>,
+ <&cru ACLK_JPEG_ENCODER0>,
+ <&cru HCLK_JPEG_ENCODER0>,
+ <&cru ACLK_JPEG_ENCODER1>,
+ <&cru HCLK_JPEG_ENCODER1>,
+ <&cru ACLK_JPEG_ENCODER2>,
+ <&cru HCLK_JPEG_ENCODER2>,
+ <&cru ACLK_JPEG_ENCODER3>,
+ <&cru HCLK_JPEG_ENCODER3>,
+ <&cru ACLK_JPEG_DECODER>,
+ <&cru HCLK_JPEG_DECODER>,
+ <&cru ACLK_RGA2>,
+ <&cru HCLK_RGA2>;
+ pm_qos = <&qos_iep>,
+ <&qos_jpeg_dec>,
+ <&qos_jpeg_enc0>,
+ <&qos_jpeg_enc1>,
+ <&qos_jpeg_enc2>,
+ <&qos_jpeg_enc3>,
+ <&qos_rga2_mro>,
+ <&qos_rga2_mwo>;
+
+ power-domain@RK3588_PD_AV1 {
+ reg = <RK3588_PD_AV1>;
+ clocks = <&cru PCLK_AV1>,
+ <&cru ACLK_AV1>,
+ <&cru HCLK_VDPU_ROOT>;
+ pm_qos = <&qos_av1>;
+ };
+ power-domain@RK3588_PD_RKVDEC0 {
+ reg = <RK3588_PD_RKVDEC0>;
+ clocks = <&cru HCLK_RKVDEC0>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_RKVDEC0>;
+ pm_qos = <&qos_rkvdec0>;
+ };
+ power-domain@RK3588_PD_RKVDEC1 {
+ reg = <RK3588_PD_RKVDEC1>;
+ clocks = <&cru HCLK_RKVDEC1>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>;
+ pm_qos = <&qos_rkvdec1>;
+ };
+ power-domain@RK3588_PD_RGA30 {
+ reg = <RK3588_PD_RGA30>;
+ clocks = <&cru ACLK_RGA3_0>,
+ <&cru HCLK_RGA3_0>;
+ pm_qos = <&qos_rga3_0>;
+ };
+ };
+ power-domain@RK3588_PD_VOP {
+ reg = <RK3588_PD_VOP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru PCLK_VOP_ROOT>,
+ <&cru HCLK_VOP_ROOT>,
+ <&cru ACLK_VOP>;
+ pm_qos = <&qos_vop_m0>,
+ <&qos_vop_m1>;
+
+ power-domain@RK3588_PD_VO0 {
+ reg = <RK3588_PD_VO0>;
+ clocks = <&cru PCLK_VO0_ROOT>,
+ <&cru PCLK_VO0_S_ROOT>,
+ <&cru HCLK_VO0_S_ROOT>,
+ <&cru ACLK_VO0_ROOT>,
+ <&cru HCLK_HDCP0>,
+ <&cru ACLK_HDCP0>,
+ <&cru HCLK_VOP_ROOT>;
+ pm_qos = <&qos_hdcp0>;
+ };
+ };
+ power-domain@RK3588_PD_VO1 {
+ reg = <RK3588_PD_VO1>;
+ clocks = <&cru PCLK_VO1_ROOT>,
+ <&cru PCLK_VO1_S_ROOT>,
+ <&cru HCLK_VO1_S_ROOT>,
+ <&cru HCLK_HDCP1>,
+ <&cru ACLK_HDCP1>,
+ <&cru ACLK_HDMIRX_ROOT>,
+ <&cru HCLK_VO1USB_TOP_ROOT>;
+ pm_qos = <&qos_hdcp1>,
+ <&qos_hdmirx>;
+ };
+ power-domain@RK3588_PD_VI {
+ reg = <RK3588_PD_VI>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru HCLK_VI_ROOT>,
+ <&cru PCLK_VI_ROOT>,
+ <&cru HCLK_ISP0>,
+ <&cru ACLK_ISP0>,
+ <&cru HCLK_VICAP>,
+ <&cru ACLK_VICAP>;
+ pm_qos = <&qos_isp0_mro>,
+ <&qos_isp0_mwo>,
+ <&qos_vicap_m0>,
+ <&qos_vicap_m1>;
+
+ power-domain@RK3588_PD_ISP1 {
+ reg = <RK3588_PD_ISP1>;
+ clocks = <&cru HCLK_ISP1>,
+ <&cru ACLK_ISP1>,
+ <&cru HCLK_VI_ROOT>,
+ <&cru PCLK_VI_ROOT>;
+ pm_qos = <&qos_isp1_mwo>,
+ <&qos_isp1_mro>;
+ };
+ power-domain@RK3588_PD_FEC {
+ reg = <RK3588_PD_FEC>;
+ clocks = <&cru HCLK_FISHEYE0>,
+ <&cru ACLK_FISHEYE0>,
+ <&cru HCLK_FISHEYE1>,
+ <&cru ACLK_FISHEYE1>,
+ <&cru PCLK_VI_ROOT>;
+ pm_qos = <&qos_fisheye0>,
+ <&qos_fisheye1>;
+ };
+ };
+ power-domain@RK3588_PD_RGA31 {
+ reg = <RK3588_PD_RGA31>;
+ clocks = <&cru HCLK_RGA3_1>,
+ <&cru ACLK_RGA3_1>;
+ pm_qos = <&qos_rga3_1>;
+ };
+ power-domain@RK3588_PD_USB {
+ reg = <RK3588_PD_USB>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_USB_ROOT>,
+ <&cru HCLK_USB_ROOT>,
+ <&cru HCLK_HOST0>,
+ <&cru HCLK_HOST_ARB0>,
+ <&cru HCLK_HOST1>,
+ <&cru HCLK_HOST_ARB1>;
+ pm_qos = <&qos_usb3_0>,
+ <&qos_usb3_1>,
+ <&qos_usb2host_0>,
+ <&qos_usb2host_1>;
+ };
+ power-domain@RK3588_PD_GMAC {
+ reg = <RK3588_PD_GMAC>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_PCIE_ROOT>,
+ <&cru ACLK_PHP_ROOT>;
+ };
+ power-domain@RK3588_PD_PCIE {
+ reg = <RK3588_PD_PCIE>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_PCIE_ROOT>,
+ <&cru ACLK_PHP_ROOT>;
+ };
+ power-domain@RK3588_PD_SDIO {
+ reg = <RK3588_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru HCLK_NVM_ROOT>;
+ pm_qos = <&qos_sdio>;
+ };
+ power-domain@RK3588_PD_AUDIO {
+ reg = <RK3588_PD_AUDIO>;
+ clocks = <&cru HCLK_AUDIO_ROOT>,
+ <&cru PCLK_AUDIO_ROOT>;
+ };
+ power-domain@RK3588_PD_SDMMC {
+ reg = <RK3588_PD_SDMMC>;
+ pm_qos = <&qos_sdmmc>;
+ };
+ };
+ };
+
+ pvtm@fda40000 {
+ compatible = "rockchip,rk3588-bigcore0-pvtm";
+ reg = <0x0 0xfda40000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pvtm@0 {
+ reg = <0>;
+ clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>;
+ clock-names = "clk", "pclk";
+ };
+ };
+
+ pvtm@fda50000 {
+ compatible = "rockchip,rk3588-bigcore1-pvtm";
+ reg = <0x0 0xfda50000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pvtm@1 {
+ reg = <1>;
+ clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>;
+ clock-names = "clk", "pclk";
+ };
+ };
+
+ pvtm@fda60000 {
+ compatible = "rockchip,rk3588-litcore-pvtm";
+ reg = <0x0 0xfda60000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pvtm@2 {
+ reg = <2>;
+ clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>;
+ clock-names = "clk", "pclk";
+ };
+ };
+
+ pvtm@fdaf0000 {
+ compatible = "rockchip,rk3588-npu-pvtm";
+ reg = <0x0 0xfdaf0000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pvtm@3 {
+ reg = <3>;
+ clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>;
+ clock-names = "clk", "pclk";
+ resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
+ reset-names = "rts", "rst-p";
+ };
+ };
+
+ pvtm@fdb30000 {
+ compatible = "rockchip,rk3588-gpu-pvtm";
+ reg = <0x0 0xfdb30000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pvtm@4 {
+ reg = <4>;
+ clocks = <&cru CLK_GPU_PVTM>;
+ clock-names = "clk";
+ resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
+ reset-names = "rts", "rst-p";
+ };
+ };
+
+ rknpu: npu@fdab0000 {
+ compatible = "rockchip,rk3588-rknpu";
+ reg = <0x0 0xfdab0000 0x0 0x10000>,
+ <0x0 0xfdac0000 0x0 0x10000>,
+ <0x0 0xfdad0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
+ clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>,
+ <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
+ <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
+ <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "clk_npu", "aclk0",
+ "aclk1", "aclk2",
+ "hclk0", "hclk1",
+ "hclk2", "pclk";
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>,
+ <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
+ reset-names = "srst_a0", "srst_a1", "srst_a2",
+ "srst_h0", "srst_h1", "srst_h2";
+ power-domains = <&power RK3588_PD_NPUTOP>,
+ <&power RK3588_PD_NPU1>,
+ <&power RK3588_PD_NPU2>;
+ power-domain-names = "npu0", "npu1", "npu2";
+ operating-points-v2 = <&npu_opp_table>;
+ iommus = <&rknpu_mmu>;
+ status = "disabled";
+ };
+
+ npu_opp_table: npu-opp-table {
+ compatible = "operating-points-v2";
+
+ nvmem-cells = <&npu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ rockchip,pvtm-voltage-sel = <
+ 0 815 0
+ 816 835 1
+ 836 860 2
+ 861 885 3
+ 886 910 4
+ 911 9999 5
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x50>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <800000>;
+ rockchip,pvtm-volt = <750000>;
+ rockchip,pvtm-ref-temp = <25>;
+ rockchip,pvtm-temp-prop = <(-113) (-113)>;
+ rockchip,pvtm-thermal-zone = "npu-thermal";
+
+ clocks = <&cru PCLK_NPU_GRF>;
+ clock-names = "pclk";
+ rockchip,grf = <&npu_grf>;
+ volt-mem-read-margin = <
+ 855000 1
+ 765000 2
+ 675000 3
+ 495000 4
+ >;
+ low-volt-read-margin = <4>;
+ intermediate-threshold-freq = <500000>; /* KHz*/
+ rockchip,init-freq = <1000000>; /* KHz */
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+ rockchip,high-temp = <85000>;
+ rockchip,high-temp-max-freq = <800000>;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L1 = <687500 687500 850000>,
+ <687500 687500 850000>;
+ opp-microvolt-L2 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L3 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L1 = <687500 687500 850000>,
+ <687500 687500 850000>;
+ opp-microvolt-L2 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L3 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L1 = <687500 687500 850000>,
+ <687500 687500 850000>;
+ opp-microvolt-L2 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L3 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L1 = <687500 687500 850000>,
+ <687500 687500 850000>;
+ opp-microvolt-L2 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L3 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <700000 700000 850000>,
+ <700000 700000 850000>;
+ opp-microvolt-L3 = <687500 687500 850000>,
+ <687500 687500 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>,
+ <675000 675000 850000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <750000 750000 850000>,
+ <750000 750000 850000>;
+ opp-microvolt-L2 = <737500 737500 850000>,
+ <737500 737500 850000>;
+ opp-microvolt-L3 = <725000 725000 850000>,
+ <725000 725000 850000>;
+ opp-microvolt-L4 = <712500 712500 850000>,
+ <712500 712500 850000>;
+ opp-microvolt-L5 = <700000 700000 850000>,
+ <700000 700000 850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <800000 800000 850000>,
+ <800000 800000 850000>;
+ opp-microvolt-L1 = <787500 787500 850000>,
+ <787500 787500 850000>;
+ opp-microvolt-L2 = <775000 775000 850000>,
+ <775000 775000 850000>;
+ opp-microvolt-L3 = <762500 762500 850000>,
+ <762500 762500 850000>;
+ opp-microvolt-L4 = <750000 750000 850000>,
+ <750000 750000 850000>;
+ opp-microvolt-L5 = <737500 737500 850000>,
+ <737500 737500 850000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <850000 850000 850000>,
+ <850000 850000 850000>;
+ opp-microvolt-L1 = <837500 837500 850000>,
+ <837500 837500 850000>;
+ opp-microvolt-L2 = <825000 825000 850000>,
+ <825000 825000 850000>;
+ opp-microvolt-L3 = <812500 812500 850000>,
+ <812500 812500 850000>;
+ opp-microvolt-L4 = <800000 800000 850000>,
+ <800000 800000 850000>;
+ opp-microvolt-L5 = <787500 787500 850000>,
+ <787500 787500 850000>;
+ };
+ };
+
+ rknpu_mmu: iommu@fdab9000 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdab9000 0x0 0x100>,
+ <0x0 0xfdaba000 0x0 0x100>,
+ <0x0 0xfdaca000 0x0 0x100>,
+ <0x0 0xfdada000 0x0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
+ clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
+ <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>;
+ clock-names = "aclk0", "aclk1", "aclk2",
+ "iface0", "iface1", "iface2";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vepu: vepu@fdb50000 {
+ compatible = "rockchip,vpu-encoder-v2";
+ reg = <0x0 0xfdb50000 0x0 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_vepu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <594000000>, <0>;
+ assigned-clocks = <&cru ACLK_VPU>;
+ assigned-clock-rates = <594000000>;
+ resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
+ reset-names = "shared_video_a", "shared_video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&vdpu_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ vdpu: vdpu@fdb50400 {
+ compatible = "rockchip,vpu-decoder-v2";
+ reg = <0x0 0xfdb50400 0x0 0x400>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <594000000>, <0>;
+ assigned-clocks = <&cru ACLK_VPU>;
+ assigned-clock-rates = <594000000>;
+ resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
+ reset-names = "shared_video_a", "shared_video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&vdpu_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ vdpu_mmu: iommu@fdb50800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdb50800 0x0 0x40>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_vdpu_mmu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ avsd: avsd-plus@fdb51000 {
+ compatible = "rockchip,avs-plus-decoder";
+ reg = <0x0 0xfdb51000 0x0 0x200>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_avsd";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
+ reset-names = "shared_video_a", "shared_video_h";
+ iommus = <&vdpu_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
+ status = "disabled";
+ };
+
+ rga3_core0: rga@fdb60000 {
+ compatible = "rockchip,rga3_core0";
+ reg = <0x0 0xfdb60000 0x0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga3_core0_irq";
+ clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>;
+ clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0";
+ power-domains = <&power RK3588_PD_RGA30>;
+ iommus = <&rga3_0_mmu>;
+ status = "disabled";
+ };
+
+ rga3_0_mmu: iommu@fdb60f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdb60f00 0x0 0x100>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga3_0_mmu";
+ clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RGA30>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rga3_core1: rga@fdb70000 {
+ compatible = "rockchip,rga3_core1";
+ reg = <0x0 0xfdb70000 0x0 0x1000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga3_core1_irq";
+ clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>;
+ clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1";
+ power-domains = <&power RK3588_PD_RGA31>;
+ iommus = <&rga3_1_mmu>;
+ status = "disabled";
+ };
+
+ rga3_1_mmu: iommu@fdb70f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdb70f00 0x0 0x100>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga3_1_mmu";
+ clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RGA31>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rga2: rga@fdb80000 {
+ compatible = "rockchip,rga2_core0";
+ reg = <0x0 0xfdb80000 0x0 0x1000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga2_irq";
+ clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
+ clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ jpegd: jpegd@fdb90000 {
+ compatible = "rockchip,rkv-jpeg-decoder-v1";
+ reg = <0x0 0xfdb90000 0x0 0x400>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpegd";
+ clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <600000000>, <0>;
+ assigned-clocks = <&cru ACLK_JPEG_DECODER>;
+ assigned-clock-rates = <600000000>;
+ resets = <&cru SRST_A_JPEG_DECODER>, <&cru SRST_H_JPEG_DECODER>;
+ reset-names = "video_a", "video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&jpegd_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <1>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ jpegd_mmu: iommu@fdb90480 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdb90480 0x0 0x40>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpegd_mmu";
+ clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ jpege0: jpege-core@fdba0000 {
+ compatible = "rockchip,vpu-jpege-core";
+ reg = <0x0 0xfdba0000 0x0 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege0";
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <594000000>, <0>;
+ assigned-clocks = <&cru ACLK_JPEG_ENCODER0>;
+ assigned-clock-rates = <594000000>;
+ resets = <&cru SRST_A_JPEG_ENCODER0>, <&cru SRST_H_JPEG_ENCODER0>;
+ reset-names = "video_a", "video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&jpege0_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,ccu = <&jpege_ccu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ jpege0_mmu: iommu@fdba0800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdba0800 0x0 0x40>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege0_mmu";
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ jpege1: jpege-core@fdba4000 {
+ compatible = "rockchip,vpu-jpege-core";
+ reg = <0x0 0xfdba4000 0x0 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege1";
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <594000000>, <0>;
+ assigned-clocks = <&cru ACLK_JPEG_ENCODER1>;
+ assigned-clock-rates = <594000000>;
+ resets = <&cru SRST_A_JPEG_ENCODER1>, <&cru SRST_H_JPEG_ENCODER1>;
+ reset-names = "video_a", "video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&jpege1_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,ccu = <&jpege_ccu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ jpege1_mmu: iommu@fdba4800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdba4800 0x0 0x40>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege1_mmu";
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ jpege2: jpege-core@fdba8000 {
+ compatible = "rockchip,vpu-jpege-core";
+ reg = <0x0 0xfdba8000 0x0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege2";
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <594000000>, <0>;
+ assigned-clocks = <&cru ACLK_JPEG_ENCODER2>;
+ assigned-clock-rates = <594000000>;
+ resets = <&cru SRST_A_JPEG_ENCODER2>, <&cru SRST_H_JPEG_ENCODER2>;
+ reset-names = "video_a", "video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&jpege2_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,ccu = <&jpege_ccu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ jpege2_mmu: iommu@fdba8800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdba8800 0x0 0x40>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege2_mmu";
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ jpege3: jpege-core@fdbac000 {
+ compatible = "rockchip,vpu-jpege-core";
+ reg = <0x0 0xfdbac000 0x0 0x400>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege3";
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <594000000>, <0>;
+ assigned-clocks = <&cru ACLK_JPEG_ENCODER3>;
+ assigned-clock-rates = <594000000>;
+ resets = <&cru SRST_A_JPEG_ENCODER3>, <&cru SRST_H_JPEG_ENCODER3>;
+ reset-names = "video_a", "video_h";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&jpege3_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,ccu = <&jpege_ccu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ jpege3_mmu: iommu@fdbac800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdbac800 0x0 0x40>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_jpege3_mmu";
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ iep: iep@fdbb0000 {
+ compatible = "rockchip,iep-v2";
+ reg = <0x0 0xfdbb0000 0x0 0x500>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_iep";
+ clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>;
+ clock-names = "aclk", "hclk", "sclk";
+ resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>;
+ reset-names = "rst_a", "rst_h", "rst_s";
+ rockchip,skip-pmu-idle-request;
+ power-domains = <&power RK3588_PD_VDPU>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <6>;
+ iommus = <&iep_mmu>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@fdbb0800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdbb0800 0x0 0x100>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_iep_mmu";
+ clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ status = "disabled";
+ };
+
+ rkvenc0: rkvenc-core@fdbd0000 {
+ compatible = "rockchip,rkv-encoder-v2-core";
+ reg = <0x0 0xfdbd0000 0x0 0x6000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvenc0";
+ clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+ rockchip,normal-rates = <600000000>, <0>, <800000000>;
+ assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>;
+ assigned-clock-rates = <600000000>, <800000000>;
+ resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>;
+ reset-names = "video_a", "video_h", "video_core";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&rkvenc0_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,ccu = <&rkvenc_ccu>;
+ rockchip,taskqueue-node = <7>;
+ rockchip,task-capacity = <8>;
+ power-domains = <&power RK3588_PD_VENC0>;
+ status = "disabled";
+ };
+
+ rkvenc0_mmu: iommu@fdbdf000 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
+ clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
+ clock-names = "aclk", "iface";
+ rockchip,disable-mmu-reset;
+ rockchip,enable-cmd-retry;
+ rockchip,shootdown-entire;
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_VENC0>;
+ status = "disabled";
+ };
+
+ rkvenc1: rkvenc-core@fdbe0000 {
+ compatible = "rockchip,rkv-encoder-v2-core";
+ reg = <0x0 0xfdbe0000 0x0 0x6000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvenc1";
+ clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+ rockchip,normal-rates = <600000000>, <0>, <800000000>;
+ assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
+ assigned-clock-rates = <600000000>, <800000000>;
+ resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>;
+ reset-names = "video_a", "video_h", "video_core";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&rkvenc1_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,ccu = <&rkvenc_ccu>;
+ rockchip,taskqueue-node = <7>;
+ rockchip,task-capacity = <8>;
+ power-domains = <&power RK3588_PD_VENC1>;
+ status = "disabled";
+ };
+
+ rkvenc1_mmu: iommu@fdbef000 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
+ clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
+ lock-names = "aclk", "iface";
+ rockchip,disable-mmu-reset;
+ rockchip,enable-cmd-retry;
+ rockchip,shootdown-entire;
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_VENC1>;
+ status = "disabled";
+ };
+
+ rkvdec_ccu: rkvdec-ccu@fdc30000 {
+ compatible = "rockchip,rkv-decoder-v2-ccu";
+ reg = <0x0 0xfdc30000 0x0 0x100>;
+ reg-names = "ccu";
+ clocks = <&cru ACLK_RKVDEC_CCU>;
+ clock-names = "aclk_ccu";
+ assigned-clocks = <&cru ACLK_RKVDEC_CCU>;
+ assigned-clock-rates = <600000000>;
+ resets = <&cru SRST_A_RKVDEC_CCU>;
+ reset-names = "video_ccu";
+ rockchip,skip-pmu-idle-request;
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ status = "disabled";
+ };
+
+ rkvdec0: rkvdec-core@fdc38000 {
+ compatible = "rockchip,rkv-decoder-v2";
+ reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>;
+ reg-names = "regs", "link";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvdec0";
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
+ "clk_cabac", "clk_hevc_cabac";
+ rockchip,normal-rates = <800000000>, <0>, <600000000>,
+ <600000000>, <1000000000>;
+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CORE>,
+ <&cru SRST_RKVDEC0_CA>, <&cru SRST_RKVDEC0_HEVC_CA>;
+ reset-names = "video_a", "video_h", "video_core",
+ "video_cabac", "video_hevc_cabac";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&rkvdec0_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,ccu = <&rkvdec_ccu>;
+ rockchip,core-mask = <0x00010001>;
+ rockchip,taskqueue-node = <9>;
+ rockchip,sram = <&rkvdec0_sram>;
+ /* rcb_iova: start and size 1M@4095M */
+ rockchip,rcb-iova = <0xFFF00000 0x100000>;
+ rockchip,rcb-min-width = <512>;
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ status = "disabled";
+ };
+
+ rkvdec0_mmu: iommu@fdc38700 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvdec0_mmu";
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
+ clock-names = "aclk", "iface";
+ rockchip,disable-mmu-reset;
+ rockchip,enable-cmd-retry;
+ rockchip,shootdown-entire;
+ rockchip,master-handle-irq;
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ status = "disabled";
+ };
+
+ rkvdec1: rkvdec-core@fdc48000 {
+ compatible = "rockchip,rkv-decoder-v2";
+ reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>;
+ reg-names = "regs", "link";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvdec1";
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
+ "clk_cabac", "clk_hevc_cabac";
+ rockchip,normal-rates = <800000000>, <0>, <600000000>,
+ <600000000>, <1000000000>;
+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CORE>,
+ <&cru SRST_RKVDEC1_CA>, <&cru SRST_RKVDEC1_HEVC_CA>;
+ reset-names = "video_a", "video_h", "video_core",
+ "video_cabac", "video_hevc_cabac";
+ rockchip,skip-pmu-idle-request;
+ iommus = <&rkvdec1_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,ccu = <&rkvdec_ccu>;
+ rockchip,core-mask = <0x00020002>;
+ rockchip,taskqueue-node = <9>;
+ rockchip,sram = <&rkvdec1_sram>;
+ /* rcb_iova: start and size 1M@4094M */
+ rockchip,rcb-iova = <0xFFE00000 0x100000>;
+ rockchip,rcb-min-width = <512>;
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ status = "disabled";
+ };
+
+ rkvdec1_mmu: iommu@fdc48700 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvdec1_mmu";
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
+ clock-names = "aclk", "iface";
+ rockchip,disable-mmu-reset;
+ rockchip,enable-cmd-retry;
+ rockchip,shootdown-entire;
+ rockchip,master-handle-irq;
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ status = "disabled";
+ };
+
+ av1d: av1d@fdc70000 {
+ compatible = "rockchip,av1-decoder";
+ reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>,
+ <0x0 0xfdc90000 0x0 0x400>;
+ reg-names = "vcd", "cache", "afbc";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_av1d", "irq_cache", "irq_afbc";
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <400000000>, <400000000>;
+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ assigned-clock-rates = <400000000>, <400000000>;
+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>;
+ reset-names = "video_a", "video_h";
+ iommus = <&av1d_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <11>;
+ power-domains = <&power RK3588_PD_AV1>;
+ status = "disabled";
+ };
+
+ av1d_mmu: iommu@fdca0000 {
+ compatible = "rockchip,iommu-av1";
+ reg = <0x0 0xfdca0000 0x0 0x600>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_av1d_mmu";
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_AV1>;
+ status = "disabled";
+ };
+
+ rkisp_unite: rkisp-unite@fdcb0000 {
+ compatible = "rockchip,rk3588-rkisp-unite";
+ reg = <0x0 0xfdcb0000 0x0 0x10000>,
+ <0x0 0xfdcc0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
+ <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
+ <&cru CLK_ISP0_CORE_VICAP>, <&cru ACLK_ISP1>,
+ <&cru HCLK_ISP1>, <&cru CLK_ISP1_CORE>,
+ <&cru CLK_ISP1_CORE_MARVIN>, <&cru CLK_ISP1_CORE_VICAP>;
+ clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0",
+ "clk_isp_core_marvin0", "clk_isp_core_vicap0",
+ "aclk_isp1", "hclk_isp1", "clk_isp_core1",
+ "clk_isp_core_marvin1", "clk_isp_core_vicap1";
+ power-domains = <&power RK3588_PD_ISP1>;
+ iommus = <&rkisp_unite_mmu>;
+ status = "disabled";
+ };
+
+ rkisp0: rkisp@fdcb0000 {
+ compatible = "rockchip,rk3588-rkisp";
+ reg = <0x0 0xfdcb0000 0x0 0x7f00>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
+ <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
+ <&cru CLK_ISP0_CORE_VICAP>;
+ clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
+ "clk_isp_core_marvin", "clk_isp_core_vicap";
+ power-domains = <&power RK3588_PD_VI>;
+ iommus = <&isp0_mmu>;
+ status = "disabled";
+ };
+
+ rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp0_mmu", "isp1_mmu";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
+ <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
+ clock-names = "aclk0", "iface0", "aclk1", "iface1";
+ power-domains = <&power RK3588_PD_ISP1>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ isp0_mmu: iommu@fdcb7f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdcb7f00 0x0 0x100>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp0_mmu";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VI>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ rkisp1: rkisp@fdcc0000 {
+ compatible = "rockchip,rk3588-rkisp";
+ reg = <0x0 0xfdcc0000 0x0 0x7f00>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
+ clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
+ <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>,
+ <&cru CLK_ISP1_CORE_VICAP>;
+ clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
+ "clk_isp_core_marvin", "clk_isp_core_vicap";
+ power-domains = <&power RK3588_PD_ISP1>;
+ iommus = <&isp1_mmu>;
+ status = "disabled";
+ };
+
+ isp1_mmu: iommu@fdcc7f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdcc7f00 0x0 0x100>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp1_mmu";
+ clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_ISP1>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ rkispp0: rkispp@fdcd0000 {
+ compatible = "rockchip,rk3588-rkispp";
+ reg = <0x0 0xfdcd0000 0x0 0x0f00>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fec_irq";
+ clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>,
+ <&cru CLK_FISHEYE0_CORE>;
+ clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
+ power-domains = <&power RK3588_PD_FEC>;
+ iommus = <&fec0_mmu>;
+ status = "disabled";
+ };
+
+ fec0_mmu: iommu@fdcd0f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdcd0f00 0x0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fec0_mmu";
+ clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, <&cru CLK_FISHEYE0_CORE>;
+ clock-names = "aclk", "iface", "pclk";
+ power-domains = <&power RK3588_PD_FEC>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ rkispp1: rkispp@fdcd8000 {
+ compatible = "rockchip,rk3588-rkispp";
+ reg = <0x0 0xfdcd8000 0x0 0x0f00>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fec_irq";
+ clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>,
+ <&cru CLK_FISHEYE1_CORE>;
+ clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
+ power-domains = <&power RK3588_PD_FEC>;
+ iommus = <&fec1_mmu>;
+ status = "disabled";
+ };
+
+ fec1_mmu: iommu@fdcd8f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdcd8f00 0x0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fec1_mmu";
+ clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, <&cru CLK_FISHEYE1_CORE>;
+ clock-names = "aclk", "iface", "pclk";
+ power-domains = <&power RK3588_PD_FEC>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ rkcif: rkcif@fdce0000 {
+ compatible = "rockchip,rk3588-cif";
+ reg = <0x0 0xfdce0000 0x0 0x800>;
+ reg-names = "cif_regs";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cif-intr";
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>;
+ clock-names = "aclk_cif", "hclk_cif", "dclk_cif";
+ resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>;
+ reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d";
+ assigned-clocks = <&cru DCLK_VICAP>;
+ assigned-clock-rates = <600000000>;
+ power-domains = <&power RK3588_PD_VI>;
+ rockchip,grf = <&sys_grf>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mmu: iommu@fdce0800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdce0800 0x0 0x100>,
+ <0x0 0xfdce0900 0x0 0x100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cif_mmu";
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VI>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi0_csi2: mipi0-csi2@fdd10000 {
+ compatible = "rockchip,rk3588-mipi-csi2";
+ reg = <0x0 0xfdd10000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>;
+ clock-names = "pclk_csi2host", "iclk_csi2host";
+ resets = <&cru SRST_P_CSI_HOST_0>, <&cru SRST_CSIHOST0_VICAP>;
+ reset-names = "srst_csihost_p", "srst_csihost_vicap";
+ status = "disabled";
+ };
+
+ mipi1_csi2: mipi1-csi2@fdd20000 {
+ compatible = "rockchip,rk3588-mipi-csi2";
+ reg = <0x0 0xfdd20000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSI_HOST_1>, <&cru ICLK_CSIHOST1>;
+ clock-names = "pclk_csi2host", "iclk_csi2host";
+ resets = <&cru SRST_P_CSI_HOST_1>, <&cru SRST_CSIHOST1_VICAP>;
+ reset-names = "srst_csihost_p", "srst_csihost_vicap";
+ status = "disabled";
+ };
+
+ mipi2_csi2: mipi2-csi2@fdd30000 {
+ compatible = "rockchip,rk3588-mipi-csi2";
+ reg = <0x0 0xfdd30000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSI_HOST_2>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSI_HOST_2>, <&cru SRST_CSIHOST2_VICAP>;
+ reset-names = "srst_csihost_p", "srst_csihost_vicap";
+ status = "disabled";
+ };
+
+ mipi3_csi2: mipi3-csi2@fdd40000 {
+ compatible = "rockchip,rk3588-mipi-csi2";
+ reg = <0x0 0xfdd40000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSI_HOST_3>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSI_HOST_3>, <&cru SRST_CSIHOST3_VICAP>;
+ reset-names = "srst_csihost_p", "srst_csihost_vicap";
+ status = "disabled";
+ };
+
+ vop: vop@fdd90000 {
+ compatible = "rockchip,rk3588-vop";
+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
+ reg-names = "regs", "gamma_lut";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>,
+ <&cru DCLK_VOP0_SRC>,
+ <&cru DCLK_VOP1_SRC>,
+ <&cru DCLK_VOP2_SRC>;
+ clock-names = "aclk_vop",
+ "hclk_vop",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "pclk_vop",
+ "dclk_src_vp0",
+ "dclk_src_vp1",
+ "dclk_src_vp2";
+ assigned-clocks = <&cru ACLK_VOP>;
+ assigned-clock-rates = <800000000>;
+ resets = <&cru SRST_A_VOP>,
+ <&cru SRST_H_VOP>,
+ <&cru SRST_D_VOP0>,
+ <&cru SRST_D_VOP1>,
+ <&cru SRST_D_VOP2>,
+ <&cru SRST_D_VOP3>;
+ reset-names = "axi",
+ "ahb",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3588_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vop-grf = <&vop_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ rockchip,pmu = <&pmu>;
+
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vp0_out_dp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dp0_in_vp0>;
+ };
+
+ vp0_out_edp0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&edp0_in_vp0>;
+ };
+
+ vp0_out_hdmi0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+ };
+
+ vp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vp1_out_dp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dp0_in_vp1>;
+ };
+
+ vp1_out_edp0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&edp0_in_vp1>;
+ };
+
+ vp1_out_hdmi0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi0_in_vp1>;
+ };
+ };
+
+ vp2: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ assigned-clocks = <&cru DCLK_VOP2_SRC>;
+ assigned-clock-parents = <&cru PLL_V0PLL>;
+
+ vp2_out_dp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dp0_in_vp2>;
+ };
+
+ vp2_out_edp0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&edp0_in_vp2>;
+ };
+
+ vp2_out_hdmi0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi0_in_vp2>;
+ };
+
+ vp2_out_dsi0: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dsi0_in_vp2>;
+ };
+
+ vp2_out_dsi1: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&dsi1_in_vp2>;
+ };
+ };
+
+ vp3: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ vp3_out_dsi0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi0_in_vp3>;
+ };
+
+ vp3_out_dsi1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi1_in_vp3>;
+ };
+
+ vp3_out_rgb: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&rgb_in_vp3>;
+ };
+ };
+ };
+ };
+
+ vop_mmu: iommu@fdd97e00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ rockchip,disable-device-link-resume;
+ rockchip,shootdown-entire;
+ status = "disabled";
+ };
+
+ spdif_tx2: spdif-tx@fddb0000 {
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xfddb0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac1 6>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
+ assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ power-domains = <&power RK3588_PD_VO0>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s4_8ch: i2s@fddc0000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddc0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 0>;
+ dma-names = "tx";
+ power-domains = <&power RK3588_PD_VO0>;
+ resets = <&cru SRST_M_I2S4_8CH_TX>;
+ reset-names = "tx-m";
+ rockchip,playback-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_tx3: spdif-tx@fdde0000 {
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xfdde0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac1 7>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
+ assigned-clocks = <&cru CLK_SPDIF3_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ power-domains = <&power RK3588_PD_VO1>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s5_8ch: i2s@fddf0000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddf0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 2>;
+ dma-names = "tx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S5_8CH_TX>;
+ reset-names = "tx-m";
+ rockchip,always-on;
+ rockchip,hdmi-path;
+ rockchip,playback-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s9_8ch: i2s@fddfc000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddfc000 0x0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac2 23>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_I2S9_8CH_RX>;
+ reset-names = "rx-m";
+ rockchip,capture-only;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_rx0: spdif-rx@fde08000 {
+ compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
+ reg = <0x0 0xfde08000 0x0 0x1000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>;
+ clock-names = "mclk", "hclk";
+ assigned-clocks = <&cru MCLK_SPDIFRX0>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac0 21>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_M_SPDIFRX0>;
+ reset-names = "spdifrx-m";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ dsi0: dsi@fde20000 {
+ compatible = "rockchip,rk3588-mipi-dsi2";
+ reg = <0x0 0xfde20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
+ clock-names = "pclk", "sys_clk";
+ resets = <&cru SRST_P_DSIHOST0>;
+ reset-names = "apb";
+ power-domains = <&power RK3588_PD_VOP>;
+ phys = <&mipi_dcphy0>;
+ phy-names = "dcphy";
+ rockchip,grf = <&vop_grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi0_in_vp2: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp2_out_dsi0>;
+ status = "disabled";
+ };
+
+ dsi0_in_vp3: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp3_out_dsi0>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dsi1: dsi@fde30000 {
+ compatible = "rockchip,rk3588-mipi-dsi2";
+ reg = <0x0 0xfde30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
+ clock-names = "pclk", "sys_clk";
+ resets = <&cru SRST_P_DSIHOST1>;
+ reset-names = "apb";
+ power-domains = <&power RK3588_PD_VOP>;
+ phys = <&mipi_dcphy1>;
+ phy-names = "dcphy";
+ rockchip,grf = <&vop_grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi1_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi1_in_vp2: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp2_out_dsi1>;
+ status = "disabled";
+ };
+
+ dsi1_in_vp3: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp3_out_dsi1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ hdcp0: hdcp@fde40000 {
+ compatible = "rockchip,rk3588-hdcp";
+ reg = <0x0 0xfde40000 0x0 0x80>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HDCP0>, <&cru PCLK_HDCP0>,
+ <&cru HCLK_HDCP0>, <&cru HCLK_HDCP_KEY0>,
+ <&cru ACLK_TRNG0>, <&cru PCLK_TRNG0>;
+ clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
+ resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>,
+ <&cru SRST_A_HDCP0>, <&cru SRST_H_HDCP_KEY0>,
+ <&cru SRST_P_TRNG0>;
+ reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
+ power-domains = <&power RK3588_PD_VO0>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+ };
+
+ dp0: dp@fde50000 {
+ compatible = "rockchip,rk3588-dp";
+ reg = <0x0 0xfde50000 0x0 0x4000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
+ <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_SPDIF2_DP0>,
+ <&hclk_vo0>;
+ clock-names = "apb", "aux", "i2s", "spdif", "hclk";
+ assigned-clocks = <&cru CLK_AUX16M_0>;
+ assigned-clock-rates = <16000000>;
+ resets = <&cru SRST_DP0>;
+ phys = <&usbdp_phy0_dp>;
+ power-domains = <&power RK3588_PD_VO0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp0_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_dp0>;
+ status = "disabled";
+ };
+
+ dp0_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_dp0>;
+ status = "disabled";
+ };
+
+ dp0_in_vp2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp2_out_dp0>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ hdcp1: hdcp@fde70000 {
+ compatible = "rockchip,rk3588-hdcp";
+ reg = <0x0 0xfde70000 0x0 0x80>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HDCP1>, <&cru PCLK_HDCP1>,
+ <&cru HCLK_HDCP1>, <&cru HCLK_HDCP_KEY1>,
+ <&cru ACLK_TRNG1>, <&cru PCLK_TRNG1>;
+ clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
+ resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>,
+ <&cru SRST_A_HDCP1>, <&cru SRST_H_HDCP_KEY1>,
+ <&cru SRST_P_TRNG1>;
+ reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
+ power-domains = <&power RK3588_PD_VO1>;
+ rockchip,vo-grf = <&vo1_grf>;
+ status = "disabled";
+ };
+
+ hdmi0: hdmi@fde80000 {
+ compatible = "rockchip,rk3588-dw-hdmi";
+ reg = <0x0 0xfde80000 0x0 0x20000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMIHDP0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_I2S5_8CH_TX>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&hclk_vo1>,
+ <&hdptxphy_hdmi_clk0>;
+ clock-names = "pclk",
+ "hpd",
+ "earc",
+ "hdmitx_ref",
+ "aud",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "hclk_vo1",
+ "link_clk";
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+ reset-names = "ref", "hdp";
+ power-domains = <&power RK3588_PD_VO1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+ reg-io-width = <4>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1_grf = <&vo1_grf>;
+ phys = <&hdptxphy_hdmi0>;
+ phy-names = "hdmi";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi0_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_hdmi0>;
+ status = "disabled";
+ };
+
+ hdmi0_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_hdmi0>;
+ status = "disabled";
+ };
+
+ hdmi0_in_vp2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp2_out_hdmi0>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ edp0: edp@fdec0000 {
+ compatible = "rockchip,rk3588-edp";
+ reg = <0x0 0xfdec0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
+ <&cru CLK_EDP0_200M>, <&hclk_vo1>;
+ clock-names = "dp", "pclk", "spdif", "hclk";
+ resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
+ reset-names = "dp", "apb";
+ phys = <&hdptxphy0>;
+ phy-names = "dp";
+ power-domains = <&power RK3588_PD_VO1>;
+ rockchip,grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp0_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_edp0>;
+ status = "disabled";
+ };
+
+ edp0_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_edp0>;
+ status = "disabled";
+ };
+
+ edp0_in_vp2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vp2_out_edp0>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ qos_gpu_m0: qos@fdf35000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf35000 0x0 0x20>;
+ };
+
+ qos_gpu_m1: qos@fdf35200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf35200 0x0 0x20>;
+ };
+
+ qos_gpu_m2: qos@fdf35400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf35400 0x0 0x20>;
+ };
+
+ qos_gpu_m3: qos@fdf35600 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf35600 0x0 0x20>;
+ };
+
+ qos_rga3_1: qos@fdf36000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf36000 0x0 0x20>;
+ };
+
+ qos_sdio: qos@fdf39000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf39000 0x0 0x20>;
+ };
+
+ qos_sdmmc: qos@fdf3d800 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf3d800 0x0 0x20>;
+ };
+
+ qos_usb3_1: qos@fdf3e000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf3e000 0x0 0x20>;
+ };
+
+ qos_usb3_0: qos@fdf3e200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf3e200 0x0 0x20>;
+ };
+
+ qos_usb2host_0: qos@fdf3e400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf3e400 0x0 0x20>;
+ };
+
+ qos_usb2host_1: qos@fdf3e600 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf3e600 0x0 0x20>;
+ };
+
+ qos_fisheye0: qos@fdf40000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf40000 0x0 0x20>;
+ };
+
+ qos_fisheye1: qos@fdf40200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf40200 0x0 0x20>;
+ };
+
+ qos_isp0_mro: qos@fdf40400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf40400 0x0 0x20>;
+ };
+
+ qos_isp0_mwo: qos@fdf40500 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf40500 0x0 0x20>;
+ };
+
+ qos_vicap_m0: qos@fdf40600 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf40600 0x0 0x20>;
+ };
+
+ qos_vicap_m1: qos@fdf40800 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf40800 0x0 0x20>;
+ };
+
+ qos_isp1_mwo: qos@fdf41000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf41000 0x0 0x20>;
+ };
+
+ qos_isp1_mro: qos@fdf41100 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf41100 0x0 0x20>;
+ };
+
+ qos_rkvenc0_m0ro: qos@fdf60000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf60000 0x0 0x20>;
+ };
+
+ qos_rkvenc0_m1ro: qos@fdf60200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf60200 0x0 0x20>;
+ };
+
+ qos_rkvenc0_m2wo: qos@fdf60400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf60400 0x0 0x20>;
+ };
+
+ qos_rkvenc1_m0ro: qos@fdf61000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf61000 0x0 0x20>;
+ };
+
+ qos_rkvenc1_m1ro: qos@fdf61200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf61200 0x0 0x20>;
+ };
+
+ qos_rkvenc1_m2wo: qos@fdf61400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf61400 0x0 0x20>;
+ };
+
+ qos_rkvdec0: qos@fdf62000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf62000 0x0 0x20>;
+ };
+
+ qos_rkvdec1: qos@fdf63000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf63000 0x0 0x20>;
+ };
+
+ qos_av1: qos@fdf64000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf64000 0x0 0x20>;
+ };
+
+ qos_iep: qos@fdf66000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66000 0x0 0x20>;
+ };
+
+ qos_jpeg_dec: qos@fdf66200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66200 0x0 0x20>;
+ };
+
+ qos_jpeg_enc0: qos@fdf66400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66400 0x0 0x20>;
+ };
+
+ qos_jpeg_enc1: qos@fdf66600 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66600 0x0 0x20>;
+ };
+
+ qos_jpeg_enc2: qos@fdf66800 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66800 0x0 0x20>;
+ };
+
+ qos_jpeg_enc3: qos@fdf66a00 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66a00 0x0 0x20>;
+ };
+
+ qos_rga2_mro: qos@fdf66c00 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66c00 0x0 0x20>;
+ };
+
+ qos_rga2_mwo: qos@fdf66e00 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf66e00 0x0 0x20>;
+ };
+
+ qos_rga3_0: qos@fdf67000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf67000 0x0 0x20>;
+ };
+
+ qos_vdpu: qos@fdf67200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf67200 0x0 0x20>;
+ };
+
+ qos_npu1: qos@fdf70000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf70000 0x0 0x20>;
+ };
+
+ qos_npu2: qos@fdf71000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf71000 0x0 0x20>;
+ };
+
+ qos_npu0_mwr: qos@fdf72000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf72000 0x0 0x20>;
+ };
+
+ qos_npu0_mro: qos@fdf72200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf72200 0x0 0x20>;
+ };
+
+ qos_mcu_npu: qos@fdf72400 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf72400 0x0 0x20>;
+ };
+
+ qos_hdcp0: qos@fdf80000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf80000 0x0 0x20>;
+ };
+
+ qos_hdcp1: qos@fdf81000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf81000 0x0 0x20>;
+ };
+
+ qos_hdmirx: qos@fdf81200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf81200 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@fdf82000 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf82000 0x0 0x20>;
+ };
+
+ qos_vop_m1: qos@fdf82200 {
+ compatible = "syscon";
+ reg = <0x0 0xfdf82200 0x0 0x20>;
+ };
+
+ dfi: dfi@fe060000 {
+ compatible = "rockchip,rk3588-dfi";
+ reg = <0x00 0xfe060000 0x00 0x10000>;
+ rockchip,pmu_grf = <&pmu1_grf>;
+ status = "disabled";
+ };
+
+ pcie2x1l1: pcie@fe180000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x30 0x3f>;
+ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
+ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
+ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
+ <0 0 0 2 &pcie2x1l1_intc 1>,
+ <0 0 0 3 &pcie2x1l1_intc 2>,
+ <0 0 0 4 &pcie2x1l1_intc 3>;
+ linux,pci-domain = <3>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ msi-map = <0x3000 &its0 0x3000 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy2_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
+ 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
+ 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
+ 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
+ reg = <0x0 0xfe180000 0x0 0x10000>,
+ <0xa 0x40c00000 0x0 0x400000>;
+ reg-names = "pcie-apb", "pcie-dbi";
+ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+
+ pcie2x1l1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie2x1l2: pcie@fe190000 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x40 0x4f>;
+ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
+ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
+ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
+ <0 0 0 2 &pcie2x1l2_intc 1>,
+ <0 0 0 3 &pcie2x1l2_intc 2>,
+ <0 0 0 4 &pcie2x1l2_intc 3>;
+ linux,pci-domain = <4>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ msi-map = <0x4000 &its0 0x4000 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
+ 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
+ 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
+ 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe190000 0x0 0x10000>,
+ <0xa 0x41000000 0x0 0x400000>;
+ reg-names = "pcie-apb", "pcie-dbi";
+ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
+ reset-names = "pcie", "periph";
+ rockchip,pipe-grf = <&php_grf>;
+ status = "disabled";
+
+ pcie2x1l2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ gmac1: ethernet@fe1c0000 {
+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe1c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&sys_grf>;
+ rockchip,php_grf = <&php_grf>;
+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
+ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
+ <&cru CLK_GMAC1_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ resets = <&cru SRST_A_GMAC1>;
+ reset-names = "stmmaceth";
+ power-domains = <&power RK3588_PD_GMAC>;
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+ };
+
+ sata0: sata@fe210000 {
+ compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe210000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy0_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ status = "disabled";
+ };
+
+ sata2: sata@fe230000 {
+ compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe230000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy2_psu PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ status = "disabled";
+ };
+
+ sfc: spi@fe2b0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@fe2c0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+ power-domains = <&power RK3588_PD_SDMMC>;
+ status = "disabled";
+ };
+
+ sdio: mmc@fe2d0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2d0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom1_pins>;
+ power-domains = <&power RK3588_PD_SDIO>;
+ status = "disabled";
+ };
+
+ sdhci: mmc@fe2e0000 {
+ compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
+ reg = <0x0 0xfe2e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TMCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ crypto: crypto@fe370000 {
+ compatible = "rockchip,rk3588-crypto";
+ reg = <0x0 0xfe370000 0x0 0x2000>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk SCMI_ACLK_SECURE_NS>, <&scmi_clk SCMI_HCLK_SECURE_NS>,
+ <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>;
+ clock-names = "aclk", "hclk", "sclk", "pka";
+ resets = <&scmi_reset SRST_CRYPTO_CORE>;
+ reset-names = "crypto-rst";
+ status = "disabled";
+ };
+
+ rng: rng@fe378000 {
+ compatible = "rockchip,trngv1";
+ reg = <0x0 0xfe378000 0x0 0x200>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+ clock-names = "hclk_trng";
+ resets = <&scmi_reset SRST_H_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ i2s0_8ch: i2s@fe470000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfe470000 0x0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
+ dmas = <&dmac0 0>, <&dmac0 1>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3588_PD_AUDIO>;
+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
+ reset-names = "tx-m", "rx-m";
+ rockchip,clk-trcm = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdi1
+ &i2s0_sdi2
+ &i2s0_sdi3
+ &i2s0_sdo0
+ &i2s0_sdo1
+ &i2s0_sdo2
+ &i2s0_sdo3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s1_8ch: i2s@fe480000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfe480000 0x0 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ dmas = <&dmac0 2>, <&dmac0 3>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
+ reset-names = "tx-m", "rx-m";
+ rockchip,clk-trcm = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_lrck
+ &i2s1m0_sclk
+ &i2s1m0_sdi0
+ &i2s1m0_sdi1
+ &i2s1m0_sdi2
+ &i2s1m0_sdi3
+ &i2s1m0_sdo0
+ &i2s1m0_sdo1
+ &i2s1m0_sdo2
+ &i2s1m0_sdo3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s2_2ch: i2s@fe490000 {
+ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xfe490000 0x0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac1 0>, <&dmac1 1>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3588_PD_AUDIO>;
+ rockchip,clk-trcm = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2m1_lrck
+ &i2s2m1_sclk
+ &i2s2m1_sdi
+ &i2s2m1_sdo>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s3_2ch: i2s@fe4a0000 {
+ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xfe4a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac1 2>, <&dmac1 3>;
+ dma-names = "tx", "rx";
+ power-domains = <&power RK3588_PD_AUDIO>;
+ rockchip,clk-trcm = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s3_lrck
+ &i2s3_sclk
+ &i2s3_sdi
+ &i2s3_sdo>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm0: pdm@fe4b0000 {
+ compatible = "rockchip,rk3588-pdm";
+ reg = <0x0 0xfe4b0000 0x0 0x1000>;
+ clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac0 4>;
+ dma-names = "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pdm0m0_clk
+ &pdm0m0_clk1
+ &pdm0m0_sdi0
+ &pdm0m0_sdi1
+ &pdm0m0_sdi2
+ &pdm0m0_sdi3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm1: pdm@fe4c0000 {
+ compatible = "rockchip,rk3588-pdm";
+ reg = <0x0 0xfe4c0000 0x0 0x1000>;
+ clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ assigned-clocks = <&cru MCLK_PDM1>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ dmas = <&dmac1 4>;
+ dma-names = "rx";
+ power-domains = <&power RK3588_PD_AUDIO>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pdm1m0_clk
+ &pdm1m0_clk1
+ &pdm1m0_sdi0
+ &pdm1m0_sdi1
+ &pdm1m0_sdi2
+ &pdm1m0_sdi3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ vad: vad@fe4d0000 {
+ compatible = "rockchip,rk3588-vad";
+ reg = <0x0 0xfe4d0000 0x0 0x1000>;
+ reg-names = "vad";
+ clocks = <&cru HCLK_VAD>;
+ clock-names = "hclk";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,audio-src = <0>;
+ rockchip,det-channel = <0>;
+ rockchip,mode = <0>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_tx0: spdif-tx@fe4e0000 {
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xfe4e0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac0 5>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
+ assigned-clocks = <&cru CLK_SPDIF0_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ power-domains = <&power RK3588_PD_AUDIO>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif0m0_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_tx1: spdif-tx@fe4f0000 {
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xfe4f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac1 5>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
+ assigned-clocks = <&cru CLK_SPDIF1_SRC>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ power-domains = <&power RK3588_PD_AUDIO>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif1m0_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ acdcdig_dsm: codec-digital@fe500000 {
+ compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
+ reg = <0x0 0xfe500000 0x0 0x1000>;
+ clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>;
+ clock-names = "dac", "pclk";
+ power-domains = <&power RK3588_PD_AUDIO>;
+ resets = <&cru SRST_DAC_ACDCDIG>;
+ reset-names = "reset" ;
+ rockchip,grf = <&sys_grf>;
+ rockchip,pwm-output-mode;
+ pinctrl-names = "default";
+ pinctrl-0 = <&auddsm_pins>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ hwlock: hwspinlock@fe5a0000 {
+ compatible = "rockchip,hwspinlock";
+ reg = <0 0xfe5a0000 0 0x100>;
+ #hwlock-cells = <1>;
+ };
+
+ gic: interrupt-controller@fe600000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+
+ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
+ <0x0 0xfe680000 0 0x100000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ its0: msi-controller@fe640000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfe640000 0x0 0x20000>;
+ };
+ its1: msi-controller@fe660000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfe660000 0x0 0x20000>;
+ };
+ };
+
+ dmac0: dma-controller@fea10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfea10000 0x0 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+
+ dmac1: dma-controller@fea30000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfea30000 0x0 0x4000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+
+ can0: can@fea50000 {
+ compatible = "rockchip,can-2.0";
+ reg = <0x0 0xfea50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
+ reset-names = "can", "can-apb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0m0_pins>;
+ tx-fifo-depth = <1>;
+ rx-fifo-depth = <6>;
+ status = "disabled";
+ };
+
+ can1: can@fea60000 {
+ compatible = "rockchip,can-2.0";
+ reg = <0x0 0xfea60000 0x0 0x1000>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
+ reset-names = "can", "can-apb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1m0_pins>;
+ tx-fifo-depth = <1>;
+ rx-fifo-depth = <6>;
+ status = "disabled";
+ };
+
+ can2: can@fea70000 {
+ compatible = "rockchip,can-2.0";
+ reg = <0x0 0xfea70000 0x0 0x1000>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
+ reset-names = "can", "can-apb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can2m0_pins>;
+ tx-fifo-depth = <1>;
+ rx-fifo-depth = <6>;
+ status = "disabled";
+ };
+
+ hw_decompress: decompress@fea80000 {
+ compatible = "rockchip,hw-decompress";
+ reg = <0x0 0xfea80000 0x0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
+ clock-names = "aclk", "dclk", "pclk";
+ resets = <&cru SRST_D_DECOM>;
+ reset-names = "dresetn";
+ status = "disabled";
+ };
+
+ i2c1: i2c@fea90000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfea90000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@feaa0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeaa0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@feab0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeab0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@feac0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeac0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@fead0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfead0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rktimer: timer@feae0000 {
+ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0xfeae0000 0x0 0x20>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ wdt: watchdog@feaf0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xfeaf0000 0x0 0x100>;
+ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi0: spi@feb00000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 14>, <&dmac0 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ spi1: spi@feb10000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 16>, <&dmac0 17>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ spi2: spi@feb20000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb20000 0x0 0x1000>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 15>, <&dmac1 16>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ spi3: spi@feb30000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb30000 0x0 0x1000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 17>, <&dmac1 18>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@feb40000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb40000 0x0 0x100>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac0 8>, <&dmac0 9>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m1_xfer>;
+ status = "disabled";
+ };
+
+ uart2: serial@feb50000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb50000 0x0 0x100>;
+ interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac0 10>, <&dmac0 11>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "disabled";
+ };
+
+ uart3: serial@feb60000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb60000 0x0 0x100>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac0 12>, <&dmac0 13>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m1_xfer>;
+ status = "disabled";
+ };
+
+ uart4: serial@feb70000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb70000 0x0 0x100>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac1 9>, <&dmac1 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m1_xfer>;
+ status = "disabled";
+ };
+
+ uart5: serial@feb80000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb80000 0x0 0x100>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac1 11>, <&dmac1 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m1_xfer>;
+ status = "disabled";
+ };
+
+ uart6: serial@feb90000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb90000 0x0 0x100>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac1 13>, <&dmac1 14>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m1_xfer>;
+ status = "disabled";
+ };
+
+ uart7: serial@feba0000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeba0000 0x0 0x100>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac2 7>, <&dmac2 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7m1_xfer>;
+ status = "disabled";
+ };
+
+ uart8: serial@febb0000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfebb0000 0x0 0x100>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac2 9>, <&dmac2 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m1_xfer>;
+ status = "disabled";
+ };
+
+ uart9: serial@febc0000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfebc0000 0x0 0x100>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac2 11>, <&dmac2 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart9m1_xfer>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@febd0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm4m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@febd0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm5m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@febd0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@febd0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0030 0x0 0x10>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm7m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm8: pwm@febe0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm8m0_pins>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm9: pwm@febe0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm9m0_pins>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm10: pwm@febe0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm10m0_pins>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm11: pwm@febe0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0030 0x0 0x10>;
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm11m0_pins>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm12: pwm@febf0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm12m0_pins>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm13: pwm@febf0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m0_pins>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm14: pwm@febf0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm14m0_pins>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm15: pwm@febf0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0030 0x0 0x10>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm15m0_pins>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ tsadc: tsadc@fec00000 {
+ compatible = "rockchip,rk3588-tsadc";
+ reg = <0x0 0xfec00000 0x0 0x400>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ assigned-clocks = <&cru CLK_TSADC>;
+ assigned-clock-rates = <2000000>;
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
+ reset-names = "tsadc", "tsadc-apb";
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <120000>;
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ pinctrl-names = "gpio", "otpout";
+ pinctrl-0 = <&tsadc_gpio_func>;
+ pinctrl-1 = <&tsadc_shut>;
+ status = "disabled";
+ };
+
+ saradc: saradc@fec10000 {
+ compatible = "rockchip,rk3588-saradc";
+ reg = <0x0 0xfec10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ mailbox0: mailbox@fec60000 {
+ compatible = "rockchip,rk3588-mailbox",
+ "rockchip,rk3368-mailbox";
+ reg = <0x0 0xfec60000 0x0 0x200>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX0>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox1: mailbox@fec70000 {
+ compatible = "rockchip,rk3588-mailbox",
+ "rockchip,rk3368-mailbox";
+ reg = <0x0 0xfec70000 0x0 0x200>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX1>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@fec80000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfec80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@fec90000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfec90000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@feca0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeca0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@fecb0000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xfecb0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac2 13>, <&dmac2 14>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ otp: otp@fecc0000 {
+ compatible = "rockchip,rk3588-otp";
+ reg = <0x0 0xfecc0000 0x0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+ <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
+ clock-names = "otpc", "apb", "arb", "phy";
+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+ <&cru SRST_OTPC_ARB>;
+ reset-names = "otpc", "apb", "arb";
+
+ /* Data cells */
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+ specification_serial_number: specification-serial-number@6 {
+ reg = <0x06 0x1>;
+ bits = <0 5>;
+ };
+ otp_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ otp_cpu_version: cpu-version@1c {
+ reg = <0x1c 0x1>;
+ bits = <3 3>;
+ };
+ cpub0_leakage: cpub0-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ cpub1_leakage: cpub1-leakage@18 {
+ reg = <0x18 0x1>;
+ };
+ cpul_leakage: cpul-leakage@19 {
+ reg = <0x19 0x1>;
+ };
+ log_leakage: log-leakage@1a {
+ reg = <0x1a 0x1>;
+ };
+ gpu_leakage: gpu-leakage@1b {
+ reg = <0x1b 0x1>;
+ };
+ npu_leakage: npu-leakage@28 {
+ reg = <0x28 0x1>;
+ };
+ codec_leakage: codec-leakage@29 {
+ reg = <0x29 0x1>;
+ };
+ };
+
+ mailbox2: mailbox@fece0000 {
+ compatible = "rockchip,rk3588-mailbox",
+ "rockchip,rk3368-mailbox";
+ reg = <0x0 0xfece0000 0x0 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX2>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ dmac2: dma-controller@fed10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfed10000 0x0 0x4000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+
+ hdptxphy0: phy@fed60000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ clock-names = "ref", "apb";
+ resets = <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>,
+ <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>;
+ reset-names = "apb", "init", "cmn", "lane";
+ rockchip,grf = <&hdptxphy0_grf>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hdptxphy_hdmi0: hdmiphy@fed60000 {
+ compatible = "rockchip,rk3588-hdptx-phy-hdmi";
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ clock-names = "ref", "apb";
+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
+ <&cru SRST_HDPTX0_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy0_grf>;
+ #phy-cells = <0>;
+ status = "disabled";
+
+ hdptxphy_hdmi_clk0: clk-port {
+ #clock-cells = <0>;
+ status = "okay";
+ };
+ };
+
+ usbdp_phy0: phy@fed80000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed80000 0x0 0x10000>;
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
+ <&cru PCLK_USBDPPHY0>,
+ <&u2phy0>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+ <&cru SRST_P_USBDPPHY0>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ status = "disabled";
+
+ usbdp_phy0_dp: dp-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbdp_phy0_u3: u3-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ mipi_dcphy0: phy@feda0000 {
+ compatible = "rockchip,rk3588-mipi-dcphy";
+ reg = <0x0 0xfeda0000 0x0 0x10000>;
+ rockchip,grf = <&mipidcphy0_grf>;
+ clocks = <&cru PCLK_MIPI_DCPHY0>,
+ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
+ clock-names = "pclk", "ref";
+ resets = <&cru SRST_M_MIPI_DCPHY0>,
+ <&cru SRST_P_MIPI_DCPHY0>,
+ <&cru SRST_P_MIPI_DCPHY0_GRF>,
+ <&cru SRST_S_MIPI_DCPHY0>;
+ reset-names = "m_phy", "apb", "grf", "s_phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_dcphy1: phy@fedb0000 {
+ compatible = "rockchip,rk3588-mipi-dcphy";
+ reg = <0x0 0xfedb0000 0x0 0x10000>;
+ rockchip,grf = <&mipidcphy1_grf>;
+ clocks = <&cru PCLK_MIPI_DCPHY1>,
+ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
+ clock-names = "pclk", "ref";
+ resets = <&cru SRST_M_MIPI_DCPHY1>,
+ <&cru SRST_P_MIPI_DCPHY1>,
+ <&cru SRST_P_MIPI_DCPHY1_GRF>,
+ <&cru SRST_S_MIPI_DCPHY1>;
+ reset-names = "m_phy", "apb", "grf", "s_phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 {
+ compatible = "rockchip,rk3588-csi2-dphy-hw";
+ reg = <0x0 0xfedc0000 0x0 0x8000>;
+ clocks = <&cru PCLK_CSIPHY0>;
+ clock-names = "pclk";
+ resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>;
+ reset-names = "srst_csiphy0", "srst_p_csiphy0";
+ rockchip,grf = <&mipidphy0_grf>;
+ rockchip,sys_grf = <&sys_grf>;
+ status = "disabled";
+ };
+
+ combphy0_ps: phy@fee00000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee00000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "refclk", "apbclk", "phpclk";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+ status = "disabled";
+ };
+
+ combphy2_psu: phy@fee20000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee20000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "refclk", "apbclk", "phpclk";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
+ rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
+ status = "disabled";
+ };
+
+ syssram: sram@ff001000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xff001000 0x0 0xef000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff001000 0xef000>;
+ /* start address and size should be 4k algin */
+ rkvdec0_sram: rkvdec-sram@0 {
+ reg = <0x0 0x78000>;
+ };
+ rkvdec1_sram: rkvdec-sram@78000 {
+ reg = <0x78000 0x77000>;
+ };
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3588-pinctrl";
+ rockchip,grf = <&ioc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@fd8a0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfd8a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@fec20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec20000 0x0 0x100>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@fec30000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec30000 0x0 0x100>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@fec40000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec40000 0x0 0x100>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@fec50000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec50000 0x0 0x100>;
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3588s-pinctrl.dtsi"
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi (revision 151)
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020~2021 Rockchip Electronics Co., Ltd.
+ */
+
+&pinctrl {
+
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+ bias-disable;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
+ bias-disable;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
+ bias-disable;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
+ bias-disable;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
+ bias-disable;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
+ bias-disable;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
+ bias-disable;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
+ bias-disable;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
+ bias-disable;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
+ bias-pull-up;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
+ bias-pull-up;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
+ bias-pull-up;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
+ bias-pull-up;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
+ bias-pull-up;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
+ bias-pull-up;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
+ bias-pull-up;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+ bias-pull-down;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+ bias-pull-down;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
+ bias-pull-down;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
+ bias-pull-down;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
+ bias-pull-down;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
+ bias-pull-down;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
+ bias-pull-down;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
+ bias-pull-down;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
+ bias-pull-down;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
+ bias-pull-down;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
+ bias-pull-down;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
+ bias-pull-down;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
+ bias-pull-down;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
+ bias-pull-down;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_smt: pcfg-pull-up-smt {
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_smt: pcfg-pull-down-smt {
+ bias-pull-down;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+ bias-disable;
+ drive-strength = <0>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
+ bias-disable;
+ drive-strength = <1>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
+ bias-disable;
+ drive-strength = <2>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
+ bias-disable;
+ drive-strength = <3>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
+ bias-disable;
+ drive-strength = <4>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
+ bias-disable;
+ drive-strength = <5>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high_pull_up: pcfg-output-high-pull-up {
+ output-high;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high_pull_down: pcfg-output-high-pull-down {
+ output-high;
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high_pull_none: pcfg-output-high-pull-none {
+ output-high;
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low_pull_up: pcfg-output-low-pull-up {
+ output-low;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low_pull_down: pcfg-output-low-pull-down {
+ output-low;
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low_pull_none: pcfg-output-low-pull-none {
+ output-low;
+ bias-disable;
+ };
+};
+
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/clock/rk3588-cru.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/clock/rk3588-cru.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/clock/rk3588-cru.h (revision 151)
@@ -0,0 +1,1497 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_B0PLL 1
+#define PLL_B1PLL 2
+#define PLL_LPLL 3
+#define PLL_V0PLL 4
+#define PLL_AUPLL 5
+#define PLL_CPLL 6
+#define PLL_GPLL 7
+#define PLL_NPLL 8
+#define PLL_PPLL 9
+#define ARMCLK_L 10
+#define ARMCLK_B01 11
+#define ARMCLK_B23 12
+
+/* cru clocks */
+#define PCLK_BIGCORE0_ROOT 20
+#define PCLK_BIGCORE0_PVTM 21
+#define PCLK_BIGCORE1_ROOT 22
+#define PCLK_BIGCORE1_PVTM 23
+#define PCLK_DSU_S_ROOT 24
+#define PCLK_DSU_ROOT 25
+#define PCLK_DSU_NS_ROOT 26
+#define PCLK_LITCORE_PVTM 27
+#define PCLK_DBG 28
+#define PCLK_DSU 29
+#define PCLK_S_DAPLITE 30
+#define PCLK_M_DAPLITE 31
+#define MBIST_MCLK_PDM1 32
+#define MBIST_CLK_ACDCDIG 33
+#define HCLK_I2S2_2CH 34
+#define HCLK_I2S3_2CH 35
+#define CLK_I2S2_2CH_SRC 36
+#define CLK_I2S2_2CH_FRAC 37
+#define CLK_I2S2_2CH 38
+#define MCLK_I2S2_2CH 39
+#define I2S2_2CH_MCLKOUT 40
+#define CLK_DAC_ACDCDIG 41
+#define CLK_I2S3_2CH_SRC 42
+#define CLK_I2S3_2CH_FRAC 43
+#define CLK_I2S3_2CH 44
+#define MCLK_I2S3_2CH 45
+#define I2S3_2CH_MCLKOUT 46
+#define PCLK_ACDCDIG 47
+#define HCLK_I2S0_8CH 48
+#define CLK_I2S0_8CH_TX_SRC 49
+#define CLK_I2S0_8CH_TX_FRAC 50
+#define MCLK_I2S0_8CH_TX 51
+#define CLK_I2S0_8CH_TX 52
+#define CLK_I2S0_8CH_RX_SRC 53
+#define CLK_I2S0_8CH_RX_FRAC 54
+#define MCLK_I2S0_8CH_RX 55
+#define CLK_I2S0_8CH_RX 56
+#define I2S0_8CH_MCLKOUT 57
+#define HCLK_PDM1 58
+#define MCLK_PDM1 59
+#define HCLK_AUDIO_ROOT 60
+#define PCLK_AUDIO_ROOT 61
+#define HCLK_SPDIF0 62
+#define CLK_SPDIF0_SRC 63
+#define CLK_SPDIF0_FRAC 64
+#define MCLK_SPDIF0 65
+#define CLK_SPDIF0 66
+#define CLK_SPDIF1 67
+#define HCLK_SPDIF1 68
+#define CLK_SPDIF1_SRC 69
+#define CLK_SPDIF1_FRAC 70
+#define MCLK_SPDIF1 71
+#define ACLK_AV1_ROOT 72
+#define ACLK_AV1 73
+#define PCLK_AV1_ROOT 74
+#define PCLK_AV1 75
+#define PCLK_MAILBOX0 76
+#define PCLK_MAILBOX1 77
+#define PCLK_MAILBOX2 78
+#define PCLK_PMU2 79
+#define PCLK_PMUCM0_INTMUX 80
+#define PCLK_DDRCM0_INTMUX 81
+#define PCLK_TOP 82
+#define PCLK_PWM1 83
+#define CLK_PWM1 84
+#define CLK_PWM1_CAPTURE 85
+#define PCLK_PWM2 86
+#define CLK_PWM2 87
+#define CLK_PWM2_CAPTURE 88
+#define PCLK_PWM3 89
+#define CLK_PWM3 90
+#define CLK_PWM3_CAPTURE 91
+#define PCLK_BUSTIMER0 92
+#define PCLK_BUSTIMER1 93
+#define CLK_BUS_TIMER_ROOT 94
+#define CLK_BUSTIMER0 95
+#define CLK_BUSTIMER1 96
+#define CLK_BUSTIMER2 97
+#define CLK_BUSTIMER3 98
+#define CLK_BUSTIMER4 99
+#define CLK_BUSTIMER5 100
+#define CLK_BUSTIMER6 101
+#define CLK_BUSTIMER7 102
+#define CLK_BUSTIMER8 103
+#define CLK_BUSTIMER9 104
+#define CLK_BUSTIMER10 105
+#define CLK_BUSTIMER11 106
+#define PCLK_WDT0 107
+#define TCLK_WDT0 108
+#define PCLK_CAN0 111
+#define CLK_CAN0 112
+#define PCLK_CAN1 113
+#define CLK_CAN1 114
+#define PCLK_CAN2 115
+#define CLK_CAN2 116
+#define ACLK_DECOM 117
+#define PCLK_DECOM 118
+#define DCLK_DECOM 119
+#define ACLK_DMAC0 120
+#define ACLK_DMAC1 121
+#define ACLK_DMAC2 122
+#define ACLK_BUS_ROOT 123
+#define ACLK_GIC 124
+#define PCLK_GPIO1 125
+#define DBCLK_GPIO1 126
+#define PCLK_GPIO2 127
+#define DBCLK_GPIO2 128
+#define PCLK_GPIO3 129
+#define DBCLK_GPIO3 130
+#define PCLK_GPIO4 131
+#define DBCLK_GPIO4 132
+#define PCLK_I2C1 133
+#define PCLK_I2C2 134
+#define PCLK_I2C3 135
+#define PCLK_I2C4 136
+#define PCLK_I2C5 137
+#define PCLK_I2C6 138
+#define PCLK_I2C7 139
+#define PCLK_I2C8 140
+#define CLK_I2C1 141
+#define CLK_I2C2 142
+#define CLK_I2C3 143
+#define CLK_I2C4 144
+#define CLK_I2C5 145
+#define CLK_I2C6 146
+#define CLK_I2C7 147
+#define CLK_I2C8 148
+#define PCLK_OTPC_NS 149
+#define CLK_OTPC_NS 150
+#define CLK_OTPC_ARB 151
+#define CLK_OTPC_AUTO_RD_G 152
+#define CLK_OTP_PHY_G 153
+#define PCLK_SARADC 156
+#define CLK_SARADC 157
+#define PCLK_SPI0 158
+#define PCLK_SPI1 159
+#define PCLK_SPI2 160
+#define PCLK_SPI3 161
+#define PCLK_SPI4 162
+#define CLK_SPI0 163
+#define CLK_SPI1 164
+#define CLK_SPI2 165
+#define CLK_SPI3 166
+#define CLK_SPI4 167
+#define ACLK_SPINLOCK 168
+#define PCLK_TSADC 169
+#define CLK_TSADC 170
+#define PCLK_UART1 171
+#define PCLK_UART2 172
+#define PCLK_UART3 173
+#define PCLK_UART4 174
+#define PCLK_UART5 175
+#define PCLK_UART6 176
+#define PCLK_UART7 177
+#define PCLK_UART8 178
+#define PCLK_UART9 179
+#define CLK_UART1_SRC 180
+#define CLK_UART1_FRAC 181
+#define CLK_UART1 182
+#define SCLK_UART1 183
+#define CLK_UART2_SRC 184
+#define CLK_UART2_FRAC 185
+#define CLK_UART2 186
+#define SCLK_UART2 187
+#define CLK_UART3_SRC 188
+#define CLK_UART3_FRAC 189
+#define CLK_UART3 190
+#define SCLK_UART3 191
+#define CLK_UART4_SRC 192
+#define CLK_UART4_FRAC 193
+#define CLK_UART4 194
+#define SCLK_UART4 195
+#define CLK_UART5_SRC 196
+#define CLK_UART5_FRAC 197
+#define CLK_UART5 198
+#define SCLK_UART5 199
+#define CLK_UART6_SRC 200
+#define CLK_UART6_FRAC 201
+#define CLK_UART6 202
+#define SCLK_UART6 203
+#define CLK_UART7_SRC 204
+#define CLK_UART7_FRAC 205
+#define CLK_UART7 206
+#define SCLK_UART7 207
+#define CLK_UART8_SRC 208
+#define CLK_UART8_FRAC 209
+#define CLK_UART8 210
+#define SCLK_UART8 211
+#define CLK_UART9_SRC 212
+#define CLK_UART9_FRAC 213
+#define CLK_UART9 214
+#define SCLK_UART9 215
+#define ACLK_CENTER_ROOT 216
+#define ACLK_CENTER_LOW_ROOT 217
+#define HCLK_CENTER_ROOT 218
+#define PCLK_CENTER_ROOT 219
+#define ACLK_DMA2DDR 220
+#define ACLK_DDR_SHAREMEM 221
+#define ACLK_CENTER_S200_ROOT 222
+#define ACLK_CENTER_S400_ROOT 223
+#define FCLK_DDR_CM0_CORE 224
+#define CLK_DDR_TIMER_ROOT 225
+#define CLK_DDR_TIMER0 226
+#define CLK_DDR_TIMER1 227
+#define TCLK_WDT_DDR 228
+#define CLK_DDR_CM0_RTC 228
+#define PCLK_WDT 230
+#define PCLK_TIMER 231
+#define PCLK_DMA2DDR 232
+#define PCLK_SHAREMEM 233
+#define CLK_50M_SRC 234
+#define CLK_100M_SRC 235
+#define CLK_150M_SRC 236
+#define CLK_200M_SRC 237
+#define CLK_250M_SRC 238
+#define CLK_300M_SRC 239
+#define CLK_350M_SRC 240
+#define CLK_400M_SRC 241
+#define CLK_450M_SRC 242
+#define CLK_500M_SRC 243
+#define CLK_600M_SRC 244
+#define CLK_650M_SRC 245
+#define CLK_700M_SRC 246
+#define CLK_800M_SRC 247
+#define CLK_1000M_SRC 248
+#define CLK_1200M_SRC 249
+#define ACLK_TOP_M300_ROOT 250
+#define ACLK_TOP_M500_ROOT 251
+#define ACLK_TOP_M400_ROOT 252
+#define ACLK_TOP_S200_ROOT 253
+#define ACLK_TOP_S400_ROOT 254
+#define CLK_MIPI_CAMARAOUT_M0 255
+#define CLK_MIPI_CAMARAOUT_M1 256
+#define CLK_MIPI_CAMARAOUT_M2 257
+#define CLK_MIPI_CAMARAOUT_M3 258
+#define CLK_MIPI_CAMARAOUT_M4 259
+#define MCLK_GMAC0_OUT 260
+#define REFCLKO25M_ETH0_OUT 261
+#define REFCLKO25M_ETH1_OUT 262
+#define CLK_CIFOUT_OUT 263
+#define PCLK_MIPI_DCPHY0 264
+#define PCLK_MIPI_DCPHY1 265
+#define PCLK_CSIPHY0 268
+#define PCLK_CSIPHY1 269
+#define ACLK_TOP_ROOT 270
+#define PCLK_TOP_ROOT 271
+#define ACLK_LOW_TOP_ROOT 272
+#define PCLK_CRU 273
+#define PCLK_GPU_ROOT 274
+#define CLK_GPU_SRC 275
+#define CLK_GPU 276
+#define CLK_GPU_COREGROUP 277
+#define CLK_GPU_STACKS 278
+#define PCLK_GPU_PVTM 279
+#define CLK_GPU_PVTM 280
+#define CLK_CORE_GPU_PVTM 281
+#define PCLK_GPU_GRF 282
+#define ACLK_ISP1_ROOT 283
+#define HCLK_ISP1_ROOT 284
+#define CLK_ISP1_CORE 285
+#define CLK_ISP1_CORE_MARVIN 286
+#define CLK_ISP1_CORE_VICAP 287
+#define ACLK_ISP1 288
+#define HCLK_ISP1 289
+#define ACLK_NPU1 290
+#define HCLK_NPU1 291
+#define ACLK_NPU2 292
+#define HCLK_NPU2 293
+#define HCLK_NPU_CM0_ROOT 294
+#define FCLK_NPU_CM0_CORE 295
+#define CLK_NPU_CM0_RTC 296
+#define PCLK_NPU_PVTM 297
+#define PCLK_NPU_GRF 298
+#define CLK_NPU_PVTM 299
+#define CLK_CORE_NPU_PVTM 300
+#define ACLK_NPU0 301
+#define HCLK_NPU0 302
+#define HCLK_NPU_ROOT 303
+#define CLK_NPU_DSU0 304
+#define PCLK_NPU_ROOT 305
+#define PCLK_NPU_TIMER 306
+#define CLK_NPUTIMER_ROOT 307
+#define CLK_NPUTIMER0 308
+#define CLK_NPUTIMER1 309
+#define PCLK_NPU_WDT 310
+#define TCLK_NPU_WDT 311
+#define HCLK_EMMC 312
+#define ACLK_EMMC 313
+#define CCLK_EMMC 314
+#define BCLK_EMMC 315
+#define TMCLK_EMMC 316
+#define SCLK_SFC 317
+#define HCLK_SFC 318
+#define HCLK_SFC_XIP 319
+#define HCLK_NVM_ROOT 320
+#define ACLK_NVM_ROOT 321
+#define CLK_GMAC0_PTP_REF 322
+#define CLK_GMAC1_PTP_REF 323
+#define CLK_GMAC_125M 324
+#define CLK_GMAC_50M 325
+#define ACLK_PHP_GIC_ITS 326
+#define ACLK_MMU_PCIE 327
+#define ACLK_MMU_PHP 328
+#define ACLK_PCIE_4L_DBI 329
+#define ACLK_PCIE_2L_DBI 330
+#define ACLK_PCIE_1L0_DBI 331
+#define ACLK_PCIE_1L1_DBI 332
+#define ACLK_PCIE_1L2_DBI 333
+#define ACLK_PCIE_4L_MSTR 334
+#define ACLK_PCIE_2L_MSTR 335
+#define ACLK_PCIE_1L0_MSTR 336
+#define ACLK_PCIE_1L1_MSTR 337
+#define ACLK_PCIE_1L2_MSTR 338
+#define ACLK_PCIE_4L_SLV 339
+#define ACLK_PCIE_2L_SLV 340
+#define ACLK_PCIE_1L0_SLV 341
+#define ACLK_PCIE_1L1_SLV 342
+#define ACLK_PCIE_1L2_SLV 343
+#define PCLK_PCIE_4L 344
+#define PCLK_PCIE_2L 345
+#define PCLK_PCIE_1L0 347
+#define PCLK_PCIE_1L1 348
+#define PCLK_PCIE_1L2 349
+#define CLK_PCIE_AUX0 350
+#define CLK_PCIE_AUX1 351
+#define CLK_PCIE_AUX2 352
+#define CLK_PCIE_AUX3 353
+#define CLK_PCIE_AUX4 354
+#define CLK_PIPEPHY0_REF 355
+#define CLK_PIPEPHY1_REF 356
+#define CLK_PIPEPHY2_REF 357
+#define PCLK_PHP_ROOT 358
+#define PCLK_GMAC0 359
+#define PCLK_GMAC1 360
+#define ACLK_PCIE_ROOT 361
+#define ACLK_PHP_ROOT 362
+#define ACLK_PCIE_BRIDGE 363
+#define ACLK_GMAC0 364
+#define ACLK_GMAC1 365
+#define CLK_PMALIVE0 366
+#define CLK_PMALIVE1 367
+#define CLK_PMALIVE2 368
+#define ACLK_SATA0 369
+#define ACLK_SATA1 370
+#define ACLK_SATA2 371
+#define CLK_RXOOB0 372
+#define CLK_RXOOB1 373
+#define CLK_RXOOB2 374
+#define ACLK_USB3OTG2 375
+#define SUSPEND_CLK_USB3OTG2 376
+#define REF_CLK_USB3OTG2 377
+#define CLK_UTMI_OTG2 378
+#define CLK_PIPEPHY0_PIPE_G 379
+#define CLK_PIPEPHY1_PIPE_G 380
+#define CLK_PIPEPHY2_PIPE_G 381
+#define CLK_PIPEPHY0_PIPE_ASIC_G 382
+#define CLK_PIPEPHY1_PIPE_ASIC_G 383
+#define CLK_PIPEPHY2_PIPE_ASIC_G 384
+#define CLK_PIPEPHY2_PIPE_U3_G 385
+#define CLK_PCIE1L2_PIPE 386
+#define CLK_PCIE4L_PIPE 387
+#define CLK_PCIE2L_PIPE 388
+#define PCLK_PCIE_COMBO_PIPE_PHY0 389
+#define PCLK_PCIE_COMBO_PIPE_PHY1 390
+#define PCLK_PCIE_COMBO_PIPE_PHY2 391
+#define PCLK_PCIE_COMBO_PIPE_PHY 392
+#define HCLK_RGA3_1 393
+#define ACLK_RGA3_1 394
+#define CLK_RGA3_1_CORE 395
+#define ACLK_RGA3_ROOT 396
+#define HCLK_RGA3_ROOT 397
+#define ACLK_RKVDEC_CCU 398
+#define HCLK_RKVDEC0 399
+#define ACLK_RKVDEC0 400
+#define CLK_RKVDEC0_CA 401
+#define CLK_RKVDEC0_HEVC_CA 402
+#define CLK_RKVDEC0_CORE 403
+#define HCLK_RKVDEC1 404
+#define ACLK_RKVDEC1 405
+#define CLK_RKVDEC1_CA 406
+#define CLK_RKVDEC1_HEVC_CA 407
+#define CLK_RKVDEC1_CORE 408
+#define HCLK_SDIO 409
+#define CCLK_SRC_SDIO 410
+#define ACLK_USB_ROOT 411
+#define HCLK_USB_ROOT 412
+#define HCLK_HOST0 413
+#define HCLK_HOST_ARB0 414
+#define HCLK_HOST1 415
+#define HCLK_HOST_ARB1 416
+#define ACLK_USB3OTG0 417
+#define SUSPEND_CLK_USB3OTG0 418
+#define REF_CLK_USB3OTG0 419
+#define ACLK_USB3OTG1 420
+#define SUSPEND_CLK_USB3OTG1 421
+#define REF_CLK_USB3OTG1 422
+#define UTMI_OHCI_CLK48_HOST0 423
+#define UTMI_OHCI_CLK48_HOST1 424
+#define HCLK_IEP2P0 425
+#define ACLK_IEP2P0 426
+#define CLK_IEP2P0_CORE 427
+#define ACLK_JPEG_ENCODER0 428
+#define HCLK_JPEG_ENCODER0 429
+#define ACLK_JPEG_ENCODER1 430
+#define HCLK_JPEG_ENCODER1 431
+#define ACLK_JPEG_ENCODER2 432
+#define HCLK_JPEG_ENCODER2 433
+#define ACLK_JPEG_ENCODER3 434
+#define HCLK_JPEG_ENCODER3 435
+#define ACLK_JPEG_DECODER 436
+#define HCLK_JPEG_DECODER 437
+#define HCLK_RGA2 438
+#define ACLK_RGA2 439
+#define CLK_RGA2_CORE 440
+#define HCLK_RGA3_0 441
+#define ACLK_RGA3_0 442
+#define CLK_RGA3_0_CORE 443
+#define ACLK_VDPU_ROOT 444
+#define ACLK_VDPU_LOW_ROOT 445
+#define HCLK_VDPU_ROOT 446
+#define ACLK_JPEG_DECODER_ROOT 447
+#define ACLK_VPU 448
+#define HCLK_VPU 449
+#define HCLK_RKVENC0_ROOT 450
+#define ACLK_RKVENC0_ROOT 451
+#define HCLK_RKVENC0 452
+#define ACLK_RKVENC0 453
+#define CLK_RKVENC0_CORE 454
+#define HCLK_RKVENC1_ROOT 455
+#define ACLK_RKVENC1_ROOT 456
+#define HCLK_RKVENC1 457
+#define ACLK_RKVENC1 458
+#define CLK_RKVENC1_CORE 459
+#define ICLK_CSIHOST01 460
+#define ICLK_CSIHOST0 461
+#define ICLK_CSIHOST1 462
+#define PCLK_CSI_HOST_0 463
+#define PCLK_CSI_HOST_1 464
+#define PCLK_CSI_HOST_2 465
+#define PCLK_CSI_HOST_3 466
+#define PCLK_CSI_HOST_4 467
+#define PCLK_CSI_HOST_5 468
+#define ACLK_FISHEYE0 469
+#define HCLK_FISHEYE0 470
+#define CLK_FISHEYE0_CORE 471
+#define ACLK_FISHEYE1 472
+#define HCLK_FISHEYE1 473
+#define CLK_FISHEYE1_CORE 474
+#define CLK_ISP0_CORE 475
+#define CLK_ISP0_CORE_MARVIN 476
+#define CLK_ISP0_CORE_VICAP 477
+#define ACLK_ISP0 478
+#define HCLK_ISP0 479
+#define ACLK_VI_ROOT 480
+#define HCLK_VI_ROOT 481
+#define PCLK_VI_ROOT 482
+#define DCLK_VICAP 483
+#define ACLK_VICAP 484
+#define HCLK_VICAP 485
+#define PCLK_DP0 486
+#define PCLK_DP1 487
+#define PCLK_S_DP0 488
+#define PCLK_S_DP1 489
+#define CLK_DP0 490
+#define CLK_DP1 491
+#define HCLK_HDCP_KEY0 492
+#define ACLK_HDCP0 493
+#define HCLK_HDCP0 494
+#define PCLK_HDCP0 495
+#define HCLK_I2S4_8CH 496
+#define ACLK_TRNG0 497
+#define PCLK_TRNG0 498
+#define ACLK_VO0_ROOT 499
+#define HCLK_VO0_ROOT 500
+#define HCLK_VO0_S_ROOT 501
+#define PCLK_VO0_ROOT 502
+#define PCLK_VO0_S_ROOT 503
+#define PCLK_VO0GRF 504
+#define CLK_I2S4_8CH_TX_SRC 505
+#define CLK_I2S4_8CH_TX_FRAC 506
+#define MCLK_I2S4_8CH_TX 507
+#define CLK_I2S4_8CH_TX 508
+#define HCLK_I2S8_8CH 510
+#define CLK_I2S8_8CH_TX_SRC 511
+#define CLK_I2S8_8CH_TX_FRAC 512
+#define MCLK_I2S8_8CH_TX 513
+#define CLK_I2S8_8CH_TX 514
+#define HCLK_SPDIF2_DP0 516
+#define CLK_SPDIF2_DP0_SRC 517
+#define CLK_SPDIF2_DP0_FRAC 518
+#define MCLK_SPDIF2_DP0 519
+#define CLK_SPDIF2_DP0 520
+#define MCLK_SPDIF2 521
+#define HCLK_SPDIF5_DP1 522
+#define CLK_SPDIF5_DP1_SRC 523
+#define CLK_SPDIF5_DP1_FRAC 524
+#define MCLK_SPDIF5_DP1 525
+#define CLK_SPDIF5_DP1 526
+#define MCLK_SPDIF5 527
+#define PCLK_EDP0 528
+#define CLK_EDP0_24M 529
+#define CLK_EDP0_200M 530
+#define PCLK_EDP1 531
+#define CLK_EDP1_24M 532
+#define CLK_EDP1_200M 533
+#define HCLK_HDCP_KEY1 534
+#define ACLK_HDCP1 535
+#define HCLK_HDCP1 536
+#define PCLK_HDCP1 537
+#define ACLK_HDMIRX 538
+#define PCLK_HDMIRX 539
+#define CLK_HDMIRX_REF 540
+#define CLK_HDMIRX_AUD_SRC 541
+#define CLK_HDMIRX_AUD_FRAC 542
+#define CLK_HDMIRX_AUD 543
+#define CLK_HDMIRX_AUD_P_MUX 544
+#define PCLK_HDMITX0 545
+#define CLK_HDMITX0_EARC 546
+#define CLK_HDMITX0_REF 547
+#define PCLK_HDMITX1 548
+#define CLK_HDMITX1_EARC 549
+#define CLK_HDMITX1_REF 550
+#define CLK_HDMITRX_REFSRC 551
+#define ACLK_TRNG1 552
+#define PCLK_TRNG1 553
+#define ACLK_HDCP1_ROOT 554
+#define ACLK_HDMIRX_ROOT 555
+#define HCLK_VO1_ROOT 556
+#define HCLK_VO1_S_ROOT 557
+#define PCLK_VO1_ROOT 558
+#define PCLK_VO1_S_ROOT 559
+#define PCLK_S_EDP0 560
+#define PCLK_S_EDP1 561
+#define PCLK_S_HDMIRX 562
+#define HCLK_I2S10_8CH 563
+#define CLK_I2S10_8CH_RX_SRC 564
+#define CLK_I2S10_8CH_RX_FRAC 565
+#define CLK_I2S10_8CH_RX 566
+#define MCLK_I2S10_8CH_RX 567
+#define HCLK_I2S7_8CH 568
+#define CLK_I2S7_8CH_RX_SRC 569
+#define CLK_I2S7_8CH_RX_FRAC 570
+#define CLK_I2S7_8CH_RX 571
+#define MCLK_I2S7_8CH_RX 572
+#define HCLK_I2S9_8CH 574
+#define CLK_I2S9_8CH_RX_SRC 575
+#define CLK_I2S9_8CH_RX_FRAC 576
+#define CLK_I2S9_8CH_RX 577
+#define MCLK_I2S9_8CH_RX 578
+#define CLK_I2S5_8CH_TX_SRC 579
+#define CLK_I2S5_8CH_TX_FRAC 580
+#define CLK_I2S5_8CH_TX 581
+#define MCLK_I2S5_8CH_TX 582
+#define HCLK_I2S5_8CH 584
+#define CLK_I2S6_8CH_TX_SRC 585
+#define CLK_I2S6_8CH_TX_FRAC 586
+#define CLK_I2S6_8CH_TX 587
+#define MCLK_I2S6_8CH_TX 588
+#define CLK_I2S6_8CH_RX_SRC 589
+#define CLK_I2S6_8CH_RX_FRAC 590
+#define CLK_I2S6_8CH_RX 591
+#define MCLK_I2S6_8CH_RX 592
+#define I2S6_8CH_MCLKOUT 593
+#define HCLK_I2S6_8CH 594
+#define HCLK_SPDIF3 595
+#define CLK_SPDIF3_SRC 596
+#define CLK_SPDIF3_FRAC 597
+#define CLK_SPDIF3 598
+#define MCLK_SPDIF3 599
+#define HCLK_SPDIF4 600
+#define CLK_SPDIF4_SRC 601
+#define CLK_SPDIF4_FRAC 602
+#define CLK_SPDIF4 603
+#define MCLK_SPDIF4 604
+#define HCLK_SPDIFRX0 605
+#define MCLK_SPDIFRX0 606
+#define HCLK_SPDIFRX1 607
+#define MCLK_SPDIFRX1 608
+#define HCLK_SPDIFRX2 609
+#define MCLK_SPDIFRX2 610
+#define ACLK_VO1USB_TOP_ROOT 611
+#define HCLK_VO1USB_TOP_ROOT 612
+#define CLK_HDMIHDP0 613
+#define CLK_HDMIHDP1 614
+#define PCLK_HDPTX0 615
+#define PCLK_HDPTX1 616
+#define PCLK_USBDPPHY0 617
+#define PCLK_USBDPPHY1 618
+#define ACLK_VOP_ROOT 619
+#define ACLK_VOP_LOW_ROOT 620
+#define HCLK_VOP_ROOT 621
+#define PCLK_VOP_ROOT 622
+#define HCLK_VOP 623
+#define ACLK_VOP 624
+#define DCLK_VOP0_SRC 625
+#define DCLK_VOP1_SRC 626
+#define DCLK_VOP2_SRC 627
+#define DCLK_VOP0 628
+#define DCLK_VOP1 629
+#define DCLK_VOP2 630
+#define DCLK_VOP3 631
+#define PCLK_DSIHOST0 632
+#define PCLK_DSIHOST1 633
+#define CLK_DSIHOST0 634
+#define CLK_DSIHOST1 635
+#define CLK_VOP_PMU 636
+#define ACLK_VOP_DOBY 637
+#define ACLK_VOP_DIV2_SRC 638
+#define CLK_USBDP_PHY0_IMMORTAL 639
+#define CLK_USBDP_PHY1_IMMORTAL 640
+#define CLK_PMU0 641
+#define PCLK_PMU0 642
+#define PCLK_PMU0IOC 643
+#define PCLK_GPIO0 644
+#define DBCLK_GPIO0 645
+#define PCLK_I2C0 646
+#define CLK_I2C0 647
+#define HCLK_I2S1_8CH 648
+#define CLK_I2S1_8CH_TX_SRC 649
+#define CLK_I2S1_8CH_TX_FRAC 650
+#define CLK_I2S1_8CH_TX 651
+#define MCLK_I2S1_8CH_TX 652
+#define CLK_I2S1_8CH_RX_SRC 653
+#define CLK_I2S1_8CH_RX_FRAC 654
+#define CLK_I2S1_8CH_RX 655
+#define MCLK_I2S1_8CH_RX 656
+#define I2S1_8CH_MCLKOUT 657
+#define CLK_PMU1_50M_SRC 658
+#define CLK_PMU1_100M_SRC 659
+#define CLK_PMU1_200M_SRC 660
+#define CLK_PMU1_300M_SRC 661
+#define CLK_PMU1_400M_SRC 662
+#define HCLK_PMU1_ROOT 663
+#define PCLK_PMU1_ROOT 664
+#define PCLK_PMU0_ROOT 665
+#define HCLK_PMU_CM0_ROOT 666
+#define PCLK_PMU1 667
+#define CLK_DDR_FAIL_SAFE 668
+#define CLK_PMU1 669
+#define HCLK_PDM0 670
+#define MCLK_PDM0 671
+#define HCLK_VAD 672
+#define FCLK_PMU_CM0_CORE 673
+#define CLK_PMU_CM0_RTC 674
+#define PCLK_PMU1_IOC 675
+#define PCLK_PMU1PWM 676
+#define CLK_PMU1PWM 677
+#define CLK_PMU1PWM_CAPTURE 678
+#define PCLK_PMU1TIMER 679
+#define CLK_PMU1TIMER_ROOT 680
+#define CLK_PMU1TIMER0 681
+#define CLK_PMU1TIMER1 682
+#define CLK_UART0_SRC 683
+#define CLK_UART0_FRAC 684
+#define CLK_UART0 685
+#define SCLK_UART0 686
+#define PCLK_UART0 687
+#define PCLK_PMU1WDT 688
+#define TCLK_PMU1WDT 689
+#define CLK_CR_PARA 690
+#define CLK_USB2PHY_HDPTXRXPHY_REF 693
+#define CLK_USBDPPHY_MIPIDCPPHY_REF 694
+#define CLK_REF_PIPE_PHY0_OSC_SRC 695
+#define CLK_REF_PIPE_PHY1_OSC_SRC 696
+#define CLK_REF_PIPE_PHY2_OSC_SRC 697
+#define CLK_REF_PIPE_PHY0_PLL_SRC 698
+#define CLK_REF_PIPE_PHY1_PLL_SRC 699
+#define CLK_REF_PIPE_PHY2_PLL_SRC 700
+#define CLK_REF_PIPE_PHY0 701
+#define CLK_REF_PIPE_PHY1 702
+#define CLK_REF_PIPE_PHY2 703
+#define SCLK_SDIO_DRV 704
+#define SCLK_SDIO_SAMPLE 705
+#define SCLK_SDMMC_DRV 706
+#define SCLK_SDMMC_SAMPLE 707
+#define CLK_PCIE1L0_PIPE 708
+#define CLK_PCIE1L1_PIPE 709
+#define CLK_BIGCORE0_PVTM 710
+#define CLK_CORE_BIGCORE0_PVTM 711
+#define CLK_BIGCORE1_PVTM 712
+#define CLK_CORE_BIGCORE1_PVTM 713
+#define CLK_LITCORE_PVTM 714
+#define CLK_CORE_LITCORE_PVTM 715
+#define CLK_AUX16M_0 716
+#define CLK_AUX16M_1 717
+#define CLK_PHY0_REF_ALT_P 718
+#define CLK_PHY0_REF_ALT_M 719
+#define CLK_PHY1_REF_ALT_P 720
+#define CLK_PHY1_REF_ALT_M 721
+
+#define CLK_NR_CLKS (CLK_PHY1_REF_ALT_M + 1)
+
+/********Name=SOFTRST_CON01,Offset=0xA04********/
+#define SRST_A_TOP_BIU 19
+#define SRST_P_TOP_BIU 20
+#define SRST_P_CSIPHY0 22
+#define SRST_CSIPHY0 23
+#define SRST_P_CSIPHY1 24
+#define SRST_CSIPHY1 25
+#define SRST_A_TOP_M500_BIU 31
+/********Name=SOFTRST_CON02,Offset=0xA08********/
+#define SRST_A_TOP_M400_BIU 32
+#define SRST_A_TOP_S200_BIU 33
+#define SRST_A_TOP_S400_BIU 34
+#define SRST_A_TOP_M300_BIU 35
+#define SRST_USBDP_COMBO_PHY0_INIT 40
+#define SRST_USBDP_COMBO_PHY0_CMN 41
+#define SRST_USBDP_COMBO_PHY0_LANE 42
+#define SRST_USBDP_COMBO_PHY0_PCS 43
+#define SRST_USBDP_COMBO_PHY1_INIT 47
+/********Name=SOFTRST_CON03,Offset=0xA0C********/
+#define SRST_USBDP_COMBO_PHY1_CMN 48
+#define SRST_USBDP_COMBO_PHY1_LANE 49
+#define SRST_USBDP_COMBO_PHY1_PCS 50
+#define SRST_DCPHY0 59
+#define SRST_P_MIPI_DCPHY0 62
+#define SRST_P_MIPI_DCPHY0_GRF 63
+/********Name=SOFTRST_CON04,Offset=0xA10********/
+#define SRST_DCPHY1 64
+#define SRST_P_MIPI_DCPHY1 67
+#define SRST_P_MIPI_DCPHY1_GRF 68
+#define SRST_P_APB2ASB_SLV_CDPHY 69
+#define SRST_P_APB2ASB_SLV_CSIPHY 70
+#define SRST_P_APB2ASB_SLV_VCCIO3_5 71
+#define SRST_P_APB2ASB_SLV_VCCIO6 72
+#define SRST_P_APB2ASB_SLV_EMMCIO 73
+#define SRST_P_APB2ASB_SLV_IOC_TOP 74
+#define SRST_P_APB2ASB_SLV_IOC_RIGHT 75
+/********Name=SOFTRST_CON05,Offset=0xA14********/
+#define SRST_P_CRU 80
+#define SRST_A_CHANNEL_SECURE2VO1USB 87
+#define SRST_A_CHANNEL_SECURE2CENTER 88
+#define SRST_H_CHANNEL_SECURE2VO1USB 94
+#define SRST_H_CHANNEL_SECURE2CENTER 95
+/********Name=SOFTRST_CON06,Offset=0xA18********/
+#define SRST_P_CHANNEL_SECURE2VO1USB 96
+#define SRST_P_CHANNEL_SECURE2CENTER 97
+/********Name=SOFTRST_CON07,Offset=0xA1C********/
+#define SRST_H_AUDIO_BIU 114
+#define SRST_P_AUDIO_BIU 115
+#define SRST_H_I2S0_8CH 116
+#define SRST_M_I2S0_8CH_TX 119
+#define SRST_M_I2S0_8CH_RX 122
+#define SRST_P_ACDCDIG 123
+#define SRST_H_I2S2_2CH 124
+#define SRST_H_I2S3_2CH 125
+/********Name=SOFTRST_CON08,Offset=0xA20********/
+#define SRST_M_I2S2_2CH 128
+#define SRST_M_I2S3_2CH 131
+#define SRST_DAC_ACDCDIG 132
+#define SRST_H_SPDIF0 142
+/********Name=SOFTRST_CON09,Offset=0xA24********/
+#define SRST_M_SPDIF0 145
+#define SRST_H_SPDIF1 146
+#define SRST_M_SPDIF1 149
+#define SRST_H_PDM1 150
+#define SRST_PDM1 151
+/********Name=SOFTRST_CON10,Offset=0xA28********/
+#define SRST_A_BUS_BIU 161
+#define SRST_P_BUS_BIU 162
+#define SRST_A_GIC 163
+#define SRST_A_GIC_DBG 164
+#define SRST_A_DMAC0 165
+#define SRST_A_DMAC1 166
+#define SRST_A_DMAC2 167
+#define SRST_P_I2C1 168
+#define SRST_P_I2C2 169
+#define SRST_P_I2C3 170
+#define SRST_P_I2C4 171
+#define SRST_P_I2C5 172
+#define SRST_P_I2C6 173
+#define SRST_P_I2C7 174
+#define SRST_P_I2C8 175
+/********Name=SOFTRST_CON11,Offset=0xA2C********/
+#define SRST_I2C1 176
+#define SRST_I2C2 177
+#define SRST_I2C3 178
+#define SRST_I2C4 179
+#define SRST_I2C5 180
+#define SRST_I2C6 181
+#define SRST_I2C7 182
+#define SRST_I2C8 183
+#define SRST_P_CAN0 184
+#define SRST_CAN0 185
+#define SRST_P_CAN1 186
+#define SRST_CAN1 187
+#define SRST_P_CAN2 188
+#define SRST_CAN2 189
+#define SRST_P_SARADC 190
+/********Name=SOFTRST_CON12,Offset=0xA30********/
+#define SRST_P_TSADC 192
+#define SRST_TSADC 193
+#define SRST_P_UART1 194
+#define SRST_P_UART2 195
+#define SRST_P_UART3 196
+#define SRST_P_UART4 197
+#define SRST_P_UART5 198
+#define SRST_P_UART6 199
+#define SRST_P_UART7 200
+#define SRST_P_UART8 201
+#define SRST_P_UART9 202
+#define SRST_S_UART1 205
+/********Name=SOFTRST_CON13,Offset=0xA34********/
+#define SRST_S_UART2 208
+#define SRST_S_UART3 211
+#define SRST_S_UART4 214
+#define SRST_S_UART5 217
+#define SRST_S_UART6 220
+#define SRST_S_UART7 223
+/********Name=SOFTRST_CON14,Offset=0xA38********/
+#define SRST_S_UART8 226
+#define SRST_S_UART9 229
+#define SRST_P_SPI0 230
+#define SRST_P_SPI1 231
+#define SRST_P_SPI2 232
+#define SRST_P_SPI3 233
+#define SRST_P_SPI4 234
+#define SRST_SPI0 235
+#define SRST_SPI1 236
+#define SRST_SPI2 237
+#define SRST_SPI3 238
+#define SRST_SPI4 239
+/********Name=SOFTRST_CON15,Offset=0xA3C********/
+#define SRST_P_WDT0 240
+#define SRST_T_WDT0 241
+#define SRST_P_SYS_GRF 242
+#define SRST_P_PWM1 243
+#define SRST_PWM1 244
+#define SRST_P_PWM2 246
+#define SRST_PWM2 247
+#define SRST_P_PWM3 249
+#define SRST_PWM3 250
+#define SRST_P_BUSTIMER0 252
+#define SRST_P_BUSTIMER1 253
+#define SRST_BUSTIMER0 255
+/********Name=SOFTRST_CON16,Offset=0xA40********/
+#define SRST_BUSTIMER1 256
+#define SRST_BUSTIMER2 257
+#define SRST_BUSTIMER3 258
+#define SRST_BUSTIMER4 259
+#define SRST_BUSTIMER5 260
+#define SRST_BUSTIMER6 261
+#define SRST_BUSTIMER7 262
+#define SRST_BUSTIMER8 263
+#define SRST_BUSTIMER9 264
+#define SRST_BUSTIMER10 265
+#define SRST_BUSTIMER11 266
+#define SRST_P_MAILBOX0 267
+#define SRST_P_MAILBOX1 268
+#define SRST_P_MAILBOX2 269
+#define SRST_P_GPIO1 270
+#define SRST_GPIO1 271
+/********Name=SOFTRST_CON17,Offset=0xA44********/
+#define SRST_P_GPIO2 272
+#define SRST_GPIO2 273
+#define SRST_P_GPIO3 274
+#define SRST_GPIO3 275
+#define SRST_P_GPIO4 276
+#define SRST_GPIO4 277
+#define SRST_A_DECOM 278
+#define SRST_P_DECOM 279
+#define SRST_D_DECOM 280
+#define SRST_P_TOP 281
+#define SRST_A_GICADB_GIC2CORE_BUS 283
+#define SRST_P_DFT2APB 284
+#define SRST_P_APB2ASB_MST_TOP 285
+#define SRST_P_APB2ASB_MST_CDPHY 286
+#define SRST_P_APB2ASB_MST_BOT_RIGHT 287
+/********Name=SOFTRST_CON18,Offset=0xA48********/
+#define SRST_P_APB2ASB_MST_IOC_TOP 288
+#define SRST_P_APB2ASB_MST_IOC_RIGHT 289
+#define SRST_P_APB2ASB_MST_CSIPHY 290
+#define SRST_P_APB2ASB_MST_VCCIO3_5 291
+#define SRST_P_APB2ASB_MST_VCCIO6 292
+#define SRST_P_APB2ASB_MST_EMMCIO 293
+#define SRST_A_SPINLOCK 294
+#define SRST_P_OTPC_NS 297
+#define SRST_OTPC_NS 298
+#define SRST_OTPC_ARB 299
+/********Name=SOFTRST_CON19,Offset=0xA4C********/
+#define SRST_P_BUSIOC 304
+#define SRST_P_PMUCM0_INTMUX 308
+#define SRST_P_DDRCM0_INTMUX 309
+/********Name=SOFTRST_CON20,Offset=0xA50********/
+#define SRST_P_DDR_DFICTL_CH0 320
+#define SRST_P_DDR_MON_CH0 321
+#define SRST_P_DDR_STANDBY_CH0 322
+#define SRST_P_DDR_UPCTL_CH0 323
+#define SRST_TM_DDR_MON_CH0 324
+#define SRST_P_DDR_GRF_CH01 325
+#define SRST_DFI_CH0 326
+#define SRST_SBR_CH0 327
+#define SRST_DDR_UPCTL_CH0 328
+#define SRST_DDR_DFICTL_CH0 329
+#define SRST_DDR_MON_CH0 330
+#define SRST_DDR_STANDBY_CH0 331
+#define SRST_A_DDR_UPCTL_CH0 332
+#define SRST_P_DDR_DFICTL_CH1 333
+#define SRST_P_DDR_MON_CH1 334
+#define SRST_P_DDR_STANDBY_CH1 335
+/********Name=SOFTRST_CON21,Offset=0xA54********/
+#define SRST_P_DDR_UPCTL_CH1 336
+#define SRST_TM_DDR_MON_CH1 337
+#define SRST_DFI_CH1 338
+#define SRST_SBR_CH1 339
+#define SRST_DDR_UPCTL_CH1 340
+#define SRST_DDR_DFICTL_CH1 341
+#define SRST_DDR_MON_CH1 342
+#define SRST_DDR_STANDBY_CH1 343
+#define SRST_A_DDR_UPCTL_CH1 344
+#define SRST_A_DDR01_MSCH0 349
+#define SRST_A_DDR01_RS_MSCH0 350
+#define SRST_A_DDR01_FRS_MSCH0 351
+/********Name=SOFTRST_CON22,Offset=0xA58********/
+#define SRST_A_DDR01_SCRAMBLE0 352
+#define SRST_A_DDR01_FRS_SCRAMBLE0 353
+#define SRST_A_DDR01_MSCH1 354
+#define SRST_A_DDR01_RS_MSCH1 355
+#define SRST_A_DDR01_FRS_MSCH1 356
+#define SRST_A_DDR01_SCRAMBLE1 357
+#define SRST_A_DDR01_FRS_SCRAMBLE1 358
+#define SRST_P_DDR01_MSCH0 359
+#define SRST_P_DDR01_MSCH1 360
+/********Name=SOFTRST_CON23,Offset=0xA5C********/
+#define SRST_P_DDR_DFICTL_CH2 368
+#define SRST_P_DDR_MON_CH2 369
+#define SRST_P_DDR_STANDBY_CH2 370
+#define SRST_P_DDR_UPCTL_CH2 371
+#define SRST_TM_DDR_MON_CH2 372
+#define SRST_P_DDR_GRF_CH23 373
+#define SRST_DFI_CH2 374
+#define SRST_SBR_CH2 375
+#define SRST_DDR_UPCTL_CH2 376
+#define SRST_DDR_DFICTL_CH2 377
+#define SRST_DDR_MON_CH2 378
+#define SRST_DDR_STANDBY_CH2 379
+#define SRST_A_DDR_UPCTL_CH2 380
+#define SRST_P_DDR_DFICTL_CH3 381
+#define SRST_P_DDR_MON_CH3 382
+#define SRST_P_DDR_STANDBY_CH3 383
+/********Name=SOFTRST_CON24,Offset=0xA60********/
+#define SRST_P_DDR_UPCTL_CH3 384
+#define SRST_TM_DDR_MON_CH3 385
+#define SRST_DFI_CH3 386
+#define SRST_SBR_CH3 387
+#define SRST_DDR_UPCTL_CH3 388
+#define SRST_DDR_DFICTL_CH3 389
+#define SRST_DDR_MON_CH3 390
+#define SRST_DDR_STANDBY_CH3 391
+#define SRST_A_DDR_UPCTL_CH3 392
+#define SRST_A_DDR23_MSCH2 397
+#define SRST_A_DDR23_RS_MSCH2 398
+#define SRST_A_DDR23_FRS_MSCH2 399
+/********Name=SOFTRST_CON25,Offset=0xA64********/
+#define SRST_A_DDR23_SCRAMBLE2 400
+#define SRST_A_DDR23_FRS_SCRAMBLE2 401
+#define SRST_A_DDR23_MSCH3 402
+#define SRST_A_DDR23_RS_MSCH3 403
+#define SRST_A_DDR23_FRS_MSCH3 404
+#define SRST_A_DDR23_SCRAMBLE3 405
+#define SRST_A_DDR23_FRS_SCRAMBLE3 406
+#define SRST_P_DDR23_MSCH2 407
+#define SRST_P_DDR23_MSCH3 408
+/********Name=SOFTRST_CON26,Offset=0xA68********/
+#define SRST_ISP1 419
+#define SRST_ISP1_VICAP 420
+#define SRST_A_ISP1_BIU 422
+#define SRST_H_ISP1_BIU 424
+/********Name=SOFTRST_CON27,Offset=0xA6C********/
+#define SRST_A_RKNN1 432
+#define SRST_A_RKNN1_BIU 433
+#define SRST_H_RKNN1 434
+#define SRST_H_RKNN1_BIU 435
+/********Name=SOFTRST_CON28,Offset=0xA70********/
+#define SRST_A_RKNN2 448
+#define SRST_A_RKNN2_BIU 449
+#define SRST_H_RKNN2 450
+#define SRST_H_RKNN2_BIU 451
+/********Name=SOFTRST_CON29,Offset=0xA74********/
+#define SRST_A_RKNN_DSU0 467
+#define SRST_P_NPUTOP_BIU 469
+#define SRST_P_NPU_TIMER 470
+#define SRST_NPUTIMER0 472
+#define SRST_NPUTIMER1 473
+#define SRST_P_NPU_WDT 474
+#define SRST_T_NPU_WDT 475
+#define SRST_P_NPU_PVTM 476
+#define SRST_P_NPU_GRF 477
+#define SRST_NPU_PVTM 478
+/********Name=SOFTRST_CON30,Offset=0xA78********/
+#define SRST_NPU_PVTPLL 480
+#define SRST_H_NPU_CM0_BIU 482
+#define SRST_F_NPU_CM0_CORE 483
+#define SRST_T_NPU_CM0_JTAG 484
+#define SRST_A_RKNN0 486
+#define SRST_A_RKNN0_BIU 487
+#define SRST_H_RKNN0 488
+#define SRST_H_RKNN0_BIU 489
+/********Name=SOFTRST_CON31,Offset=0xA7C********/
+#define SRST_H_NVM_BIU 498
+#define SRST_A_NVM_BIU 499
+#define SRST_H_EMMC 500
+#define SRST_A_EMMC 501
+#define SRST_C_EMMC 502
+#define SRST_B_EMMC 503
+#define SRST_T_EMMC 504
+#define SRST_S_SFC 505
+#define SRST_H_SFC 506
+#define SRST_H_SFC_XIP 507
+/********Name=SOFTRST_CON32,Offset=0xA80********/
+#define SRST_P_GRF 513
+#define SRST_P_DEC_BIU 514
+#define SRST_P_PHP_BIU 517
+#define SRST_A_PCIE_GRIDGE 520
+#define SRST_A_PHP_BIU 521
+#define SRST_A_GMAC0 522
+#define SRST_A_GMAC1 523
+#define SRST_A_PCIE_BIU 524
+#define SRST_PCIE0_POWER_UP 525
+#define SRST_PCIE1_POWER_UP 526
+#define SRST_PCIE2_POWER_UP 527
+/********Name=SOFTRST_CON33,Offset=0xA84********/
+#define SRST_PCIE3_POWER_UP 528
+#define SRST_PCIE4_POWER_UP 529
+#define SRST_P_PCIE0 540
+#define SRST_P_PCIE1 541
+#define SRST_P_PCIE2 542
+#define SRST_P_PCIE3 543
+/********Name=SOFTRST_CON34,Offset=0xA88********/
+#define SRST_P_PCIE4 544
+#define SRST_A_PHP_GIC_ITS 550
+#define SRST_A_MMU_PCIE 551
+#define SRST_A_MMU_PHP 552
+#define SRST_A_MMU_BIU 553
+/********Name=SOFTRST_CON35,Offset=0xA8C********/
+#define SRST_A_USB3OTG2 567
+/********Name=SOFTRST_CON37,Offset=0xA94********/
+#define SRST_PMALIVE0 596
+#define SRST_PMALIVE1 597
+#define SRST_PMALIVE2 598
+#define SRST_A_SATA0 599
+#define SRST_A_SATA1 600
+#define SRST_A_SATA2 601
+#define SRST_RXOOB0 602
+#define SRST_RXOOB1 603
+#define SRST_RXOOB2 604
+#define SRST_ASIC0 605
+#define SRST_ASIC1 606
+#define SRST_ASIC2 607
+/********Name=SOFTRST_CON40,Offset=0xAA0********/
+#define SRST_A_RKVDEC_CCU 642
+#define SRST_H_RKVDEC0 643
+#define SRST_A_RKVDEC0 644
+#define SRST_H_RKVDEC0_BIU 645
+#define SRST_A_RKVDEC0_BIU 646
+#define SRST_RKVDEC0_CA 647
+#define SRST_RKVDEC0_HEVC_CA 648
+#define SRST_RKVDEC0_CORE 649
+/********Name=SOFTRST_CON41,Offset=0xAA4********/
+#define SRST_H_RKVDEC1 658
+#define SRST_A_RKVDEC1 659
+#define SRST_H_RKVDEC1_BIU 660
+#define SRST_A_RKVDEC1_BIU 661
+#define SRST_RKVDEC1_CA 662
+#define SRST_RKVDEC1_HEVC_CA 663
+#define SRST_RKVDEC1_CORE 664
+/********Name=SOFTRST_CON42,Offset=0xAA8********/
+#define SRST_A_USB_BIU 674
+#define SRST_H_USB_BIU 675
+#define SRST_A_USB3OTG0 676
+#define SRST_A_USB3OTG1 679
+#define SRST_H_HOST0 682
+#define SRST_H_HOST_ARB0 683
+#define SRST_H_HOST1 684
+#define SRST_H_HOST_ARB1 685
+#define SRST_A_USB_GRF 686
+#define SRST_C_USB2P0_HOST0 687
+/********Name=SOFTRST_CON43,Offset=0xAAC********/
+#define SRST_C_USB2P0_HOST1 688
+#define SRST_HOST_UTMI0 689
+#define SRST_HOST_UTMI1 690
+/********Name=SOFTRST_CON44,Offset=0xAB0********/
+#define SRST_A_VDPU_BIU 708
+#define SRST_A_VDPU_LOW_BIU 709
+#define SRST_H_VDPU_BIU 710
+#define SRST_A_JPEG_DECODER_BIU 711
+#define SRST_A_VPU 712
+#define SRST_H_VPU 713
+#define SRST_A_JPEG_ENCODER0 714
+#define SRST_H_JPEG_ENCODER0 715
+#define SRST_A_JPEG_ENCODER1 716
+#define SRST_H_JPEG_ENCODER1 717
+#define SRST_A_JPEG_ENCODER2 718
+#define SRST_H_JPEG_ENCODER2 719
+/********Name=SOFTRST_CON45,Offset=0xAB4********/
+#define SRST_A_JPEG_ENCODER3 720
+#define SRST_H_JPEG_ENCODER3 721
+#define SRST_A_JPEG_DECODER 722
+#define SRST_H_JPEG_DECODER 723
+#define SRST_H_IEP2P0 724
+#define SRST_A_IEP2P0 725
+#define SRST_IEP2P0_CORE 726
+#define SRST_H_RGA2 727
+#define SRST_A_RGA2 728
+#define SRST_RGA2_CORE 729
+#define SRST_H_RGA3_0 730
+#define SRST_A_RGA3_0 731
+#define SRST_RGA3_0_CORE 732
+/********Name=SOFTRST_CON47,Offset=0xABC********/
+#define SRST_H_RKVENC0_BIU 754
+#define SRST_A_RKVENC0_BIU 755
+#define SRST_H_RKVENC0 756
+#define SRST_A_RKVENC0 757
+#define SRST_RKVENC0_CORE 758
+/********Name=SOFTRST_CON48,Offset=0xAC0********/
+#define SRST_H_RKVENC1_BIU 770
+#define SRST_A_RKVENC1_BIU 771
+#define SRST_H_RKVENC1 772
+#define SRST_A_RKVENC1 773
+#define SRST_RKVENC1_CORE 774
+/********Name=SOFTRST_CON49,Offset=0xAC4********/
+#define SRST_A_VI_BIU 787
+#define SRST_H_VI_BIU 788
+#define SRST_P_VI_BIU 789
+#define SRST_D_VICAP 790
+#define SRST_A_VICAP 791
+#define SRST_H_VICAP 792
+#define SRST_ISP0 794
+#define SRST_ISP0_VICAP 795
+/********Name=SOFTRST_CON50,Offset=0xAC8********/
+#define SRST_FISHEYE0 800
+#define SRST_FISHEYE1 803
+#define SRST_P_CSI_HOST_0 804
+#define SRST_P_CSI_HOST_1 805
+#define SRST_P_CSI_HOST_2 806
+#define SRST_P_CSI_HOST_3 807
+#define SRST_P_CSI_HOST_4 808
+#define SRST_P_CSI_HOST_5 809
+/********Name=SOFTRST_CON51,Offset=0xACC********/
+#define SRST_CSIHOST0_VICAP 820
+#define SRST_CSIHOST1_VICAP 821
+#define SRST_CSIHOST2_VICAP 822
+#define SRST_CSIHOST3_VICAP 823
+#define SRST_CSIHOST4_VICAP 824
+#define SRST_CSIHOST5_VICAP 825
+#define SRST_CIFIN 829
+/********Name=SOFTRST_CON52,Offset=0xAD0********/
+#define SRST_A_VOP_BIU 836
+#define SRST_A_VOP_LOW_BIU 837
+#define SRST_H_VOP_BIU 838
+#define SRST_P_VOP_BIU 839
+#define SRST_H_VOP 840
+#define SRST_A_VOP 841
+#define SRST_D_VOP0 845
+#define SRST_D_VOP2HDMI_BRIDGE0 846
+#define SRST_D_VOP2HDMI_BRIDGE1 847
+/********Name=SOFTRST_CON53,Offset=0xAD4********/
+#define SRST_D_VOP1 848
+#define SRST_D_VOP2 849
+#define SRST_D_VOP3 850
+#define SRST_P_VOPGRF 851
+#define SRST_P_DSIHOST0 852
+#define SRST_P_DSIHOST1 853
+#define SRST_DSIHOST0 854
+#define SRST_DSIHOST1 855
+#define SRST_VOP_PMU 856
+#define SRST_P_VOP_CHANNEL_BIU 857
+/********Name=SOFTRST_CON55,Offset=0xADC********/
+#define SRST_H_VO0_BIU 885
+#define SRST_H_VO0_S_BIU 886
+#define SRST_P_VO0_BIU 887
+#define SRST_P_VO0_S_BIU 888
+#define SRST_A_HDCP0_BIU 889
+#define SRST_P_VO0GRF 890
+#define SRST_H_HDCP_KEY0 891
+#define SRST_A_HDCP0 892
+#define SRST_H_HDCP0 893
+#define SRST_HDCP0 895
+/********Name=SOFTRST_CON56,Offset=0xAE0********/
+#define SRST_P_TRNG0 897
+#define SRST_DP0 904
+#define SRST_DP1 905
+#define SRST_H_I2S4_8CH 906
+#define SRST_M_I2S4_8CH_TX 909
+#define SRST_H_I2S8_8CH 910
+/********Name=SOFTRST_CON57,Offset=0xAE4********/
+#define SRST_M_I2S8_8CH_TX 913
+#define SRST_H_SPDIF2_DP0 914
+#define SRST_M_SPDIF2_DP0 918
+#define SRST_H_SPDIF5_DP1 919
+#define SRST_M_SPDIF5_DP1 923
+/********Name=SOFTRST_CON59,Offset=0xAEC********/
+#define SRST_A_HDCP1_BIU 950
+#define SRST_A_HDMIRX_BIU 951
+#define SRST_A_VO1_BIU 952
+#define SRST_H_VOP1_BIU 953
+#define SRST_H_VOP1_S_BIU 954
+#define SRST_P_VOP1_BIU 955
+#define SRST_P_VO1GRF 956
+#define SRST_P_VO1_S_BIU 957
+/********Name=SOFTRST_CON60,Offset=0xAF0********/
+#define SRST_H_I2S7_8CH 960
+#define SRST_M_I2S7_8CH_RX 963
+#define SRST_H_HDCP_KEY1 964
+#define SRST_A_HDCP1 965
+#define SRST_H_HDCP1 966
+#define SRST_HDCP1 968
+#define SRST_P_TRNG1 970
+#define SRST_P_HDMITX0 971
+/********Name=SOFTRST_CON61,Offset=0xAF4********/
+#define SRST_HDMITX0_REF 976
+#define SRST_P_HDMITX1 978
+#define SRST_HDMITX1_REF 983
+#define SRST_A_HDMIRX 985
+#define SRST_P_HDMIRX 986
+#define SRST_HDMIRX_REF 987
+/********Name=SOFTRST_CON62,Offset=0xAF8********/
+#define SRST_P_EDP0 992
+#define SRST_EDP0_24M 993
+#define SRST_P_EDP1 995
+#define SRST_EDP1_24M 996
+#define SRST_M_I2S5_8CH_TX 1000
+#define SRST_H_I2S5_8CH 1004
+#define SRST_M_I2S6_8CH_TX 1007
+/********Name=SOFTRST_CON63,Offset=0xAFC********/
+#define SRST_M_I2S6_8CH_RX 1010
+#define SRST_H_I2S6_8CH 1011
+#define SRST_H_SPDIF3 1012
+#define SRST_M_SPDIF3 1015
+#define SRST_H_SPDIF4 1016
+#define SRST_M_SPDIF4 1019
+#define SRST_H_SPDIFRX0 1020
+#define SRST_M_SPDIFRX0 1021
+#define SRST_H_SPDIFRX1 1022
+#define SRST_M_SPDIFRX1 1023
+/********Name=SOFTRST_CON64,Offset=0xB00********/
+#define SRST_H_SPDIFRX2 1024
+#define SRST_M_SPDIFRX2 1025
+#define SRST_LINKSYM_HDMITXPHY0 1036
+#define SRST_LINKSYM_HDMITXPHY1 1037
+#define SRST_VO1_BRIDGE0 1038
+#define SRST_VO1_BRIDGE1 1039
+/********Name=SOFTRST_CON65,Offset=0xB04********/
+#define SRST_H_I2S9_8CH 1040
+#define SRST_M_I2S9_8CH_RX 1043
+#define SRST_H_I2S10_8CH 1044
+#define SRST_M_I2S10_8CH_RX 1047
+#define SRST_P_S_HDMIRX 1048
+/********Name=SOFTRST_CON66,Offset=0xB08********/
+#define SRST_GPU 1060
+#define SRST_SYS_GPU 1061
+#define SRST_A_S_GPU_BIU 1064
+#define SRST_A_M0_GPU_BIU 1065
+#define SRST_A_M1_GPU_BIU 1066
+#define SRST_A_M2_GPU_BIU 1067
+#define SRST_A_M3_GPU_BIU 1068
+#define SRST_P_GPU_BIU 1070
+#define SRST_P_GPU_PVTM 1071
+/********Name=SOFTRST_CON67,Offset=0xB0C********/
+#define SRST_GPU_PVTM 1072
+#define SRST_P_GPU_GRF 1074
+#define SRST_GPU_PVTPLL 1075
+#define SRST_GPU_JTAG 1076
+/********Name=SOFTRST_CON68,Offset=0xB10********/
+#define SRST_A_AV1_BIU 1089
+#define SRST_A_AV1 1090
+#define SRST_P_AV1_BIU 1092
+#define SRST_P_AV1 1093
+/********Name=SOFTRST_CON69,Offset=0xB14********/
+#define SRST_A_DDR_BIU 1108
+#define SRST_A_DMA2DDR 1109
+#define SRST_A_DDR_SHAREMEM 1110
+#define SRST_A_DDR_SHAREMEM_BIU 1111
+#define SRST_A_CENTER_S200_BIU 1114
+#define SRST_A_CENTER_S400_BIU 1115
+#define SRST_H_AHB2APB 1116
+#define SRST_H_CENTER_BIU 1117
+#define SRST_F_DDR_CM0_CORE 1118
+/********Name=SOFTRST_CON70,Offset=0xB18********/
+#define SRST_DDR_TIMER0 1120
+#define SRST_DDR_TIMER1 1121
+#define SRST_T_WDT_DDR 1122
+#define SRST_T_DDR_CM0_JTAG 1123
+#define SRST_P_CENTER_GRF 1125
+#define SRST_P_AHB2APB 1126
+#define SRST_P_WDT 1127
+#define SRST_P_TIMER 1128
+#define SRST_P_DMA2DDR 1129
+#define SRST_P_SHAREMEM 1130
+#define SRST_P_CENTER_BIU 1131
+#define SRST_P_CENTER_CHANNEL_BIU 1132
+/********Name=SOFTRST_CON72,Offset=0xB20********/
+#define SRST_P_USBDPGRF0 1153
+#define SRST_P_USBDPPHY0 1154
+#define SRST_P_USBDPGRF1 1155
+#define SRST_P_USBDPPHY1 1156
+#define SRST_P_HDPTX0 1157
+#define SRST_P_HDPTX1 1158
+#define SRST_P_APB2ASB_SLV_BOT_RIGHT 1159
+#define SRST_P_USB2PHY_U3_0_GRF0 1160
+#define SRST_P_USB2PHY_U3_1_GRF0 1161
+#define SRST_P_USB2PHY_U2_0_GRF0 1162
+#define SRST_P_USB2PHY_U2_1_GRF0 1163
+#define SRST_HDPTX0_ROPLL 1164
+#define SRST_HDPTX0_LCPLL 1165
+#define SRST_HDPTX0 1166
+#define SRST_HDPTX1_ROPLL 1167
+/********Name=SOFTRST_CON73,Offset=0xB24********/
+#define SRST_HDPTX1_LCPLL 1168
+#define SRST_HDPTX1 1169
+#define SRST_HDPTX0_HDMIRXPHY_SET 1170
+#define SRST_USBDP_COMBO_PHY0 1171
+#define SRST_USBDP_COMBO_PHY0_LCPLL 1172
+#define SRST_USBDP_COMBO_PHY0_ROPLL 1173
+#define SRST_USBDP_COMBO_PHY0_PCS_HS 1174
+#define SRST_USBDP_COMBO_PHY1 1175
+#define SRST_USBDP_COMBO_PHY1_LCPLL 1176
+#define SRST_USBDP_COMBO_PHY1_ROPLL 1177
+#define SRST_USBDP_COMBO_PHY1_PCS_HS 1178
+#define SRST_HDMIHDP0 1180
+#define SRST_HDMIHDP1 1181
+/********Name=SOFTRST_CON74,Offset=0xB28********/
+#define SRST_A_VO1USB_TOP_BIU 1185
+#define SRST_H_VO1USB_TOP_BIU 1187
+/********Name=SOFTRST_CON75,Offset=0xB2C********/
+#define SRST_H_SDIO_BIU 1201
+#define SRST_H_SDIO 1202
+#define SRST_SDIO 1203
+/********Name=SOFTRST_CON76,Offset=0xB30********/
+#define SRST_H_RGA3_BIU 1218
+#define SRST_A_RGA3_BIU 1219
+#define SRST_H_RGA3_1 1220
+#define SRST_A_RGA3_1 1221
+#define SRST_RGA3_1_CORE 1222
+/********Name=SOFTRST_CON77,Offset=0xB34********/
+#define SRST_REF_PIPE_PHY0 1238
+#define SRST_REF_PIPE_PHY1 1239
+#define SRST_REF_PIPE_PHY2 1240
+
+/********Name=PHPTOPSOFTRST_CON0,Offset=0x8A00********/
+#define SRST_P_PHPTOP_CRU 131073
+#define SRST_P_PCIE2_GRF0 131074
+#define SRST_P_PCIE2_GRF1 131075
+#define SRST_P_PCIE2_GRF2 131076
+#define SRST_P_PCIE2_PHY0 131077
+#define SRST_P_PCIE2_PHY1 131078
+#define SRST_P_PCIE2_PHY2 131079
+#define SRST_P_PCIE3_PHY 131080
+#define SRST_P_APB2ASB_SLV_CHIP_TOP 131081
+#define SRST_PCIE30_PHY 131082
+
+/********Name=PMU1SOFTRST_CON00,Offset=0x30A00********/
+#define SRST_H_PMU1_BIU 786442
+#define SRST_P_PMU1_BIU 786443
+#define SRST_H_PMU_CM0_BIU 786444
+#define SRST_F_PMU_CM0_CORE 786445
+#define SRST_T_PMU1_CM0_JTAG 786446
+
+/********Name=PMU1SOFTRST_CON01,Offset=0x30A04********/
+#define SRST_DDR_FAIL_SAFE 786449
+#define SRST_P_CRU_PMU1 786450
+#define SRST_P_PMU1_GRF 786452
+#define SRST_P_PMU1_IOC 786453
+#define SRST_P_PMU1WDT 786454
+#define SRST_T_PMU1WDT 786455
+#define SRST_P_PMU1TIMER 786456
+#define SRST_PMU1TIMER0 786458
+#define SRST_PMU1TIMER1 786459
+#define SRST_P_PMU1PWM 786460
+#define SRST_PMU1PWM 786461
+
+/********Name=PMU1SOFTRST_CON02,Offset=0x30A08********/
+#define SRST_P_I2C0 786465
+#define SRST_I2C0 786466
+#define SRST_S_UART0 786469
+#define SRST_P_UART0 786470
+#define SRST_H_I2S1_8CH 786471
+#define SRST_M_I2S1_8CH_TX 786474
+#define SRST_M_I2S1_8CH_RX 786477
+#define SRST_H_PDM0 786478
+#define SRST_PDM0 786479
+
+/********Name=PMU1SOFTRST_CON03,Offset=0x30A0C********/
+#define SRST_H_VAD 786480
+#define SRST_HDPTX0_INIT 786491
+#define SRST_HDPTX0_CMN 786492
+#define SRST_HDPTX0_LANE 786493
+#define SRST_HDPTX1_INIT 786495
+
+/********Name=PMU1SOFTRST_CON04,Offset=0x30A10********/
+#define SRST_HDPTX1_CMN 786496
+#define SRST_HDPTX1_LANE 786497
+#define SRST_M_MIPI_DCPHY0 786499
+#define SRST_S_MIPI_DCPHY0 786500
+#define SRST_M_MIPI_DCPHY1 786501
+#define SRST_S_MIPI_DCPHY1 786502
+#define SRST_OTGPHY_U3_0 786503
+#define SRST_OTGPHY_U3_1 786504
+#define SRST_OTGPHY_U2_0 786505
+#define SRST_OTGPHY_U2_1 786506
+
+/********Name=PMU1SOFTRST_CON05,Offset=0x30A14********/
+#define SRST_P_PMU0GRF 786515
+#define SRST_P_PMU0IOC 786516
+#define SRST_P_GPIO0 786517
+#define SRST_GPIO0 786518
+
+/* scmi-clocks indices */
+
+#define SCMI_CLK_CPUL 0
+#define SCMI_CLK_DSU 1
+#define SCMI_CLK_CPUB01 2
+#define SCMI_CLK_CPUB23 3
+#define SCMI_CLK_DDR 4
+#define SCMI_CLK_GPU 5
+#define SCMI_CLK_NPU 6
+#define SCMI_CLK_SBUS 7
+#define SCMI_PCLK_SBUS 8
+#define SCMI_CCLK_SD 9
+#define SCMI_DCLK_SD 10
+#define SCMI_ACLK_SECURE_NS 11
+#define SCMI_HCLK_SECURE_NS 12
+#define SCMI_TCLK_WDT 13
+#define SCMI_KEYLADDER_CORE 14
+#define SCMI_KEYLADDER_RNG 15
+#define SCMI_ACLK_SECURE_S 16
+#define SCMI_HCLK_SECURE_S 17
+#define SCMI_PCLK_SECURE_S 18
+#define SCMI_CRYPTO_RNG 19
+#define SCMI_CRYPTO_CORE 20
+#define SCMI_CRYPTO_PKA 21
+#define SCMI_SPLL 22
+#define SCMI_HCLK_SD 23
+
+/********Name=SECURE_SOFTRST_CON00,Offset=0xA00********/
+#define SRST_A_SECURE_NS_BIU 10
+#define SRST_H_SECURE_NS_BIU 11
+#define SRST_A_SECURE_S_BIU 12
+#define SRST_H_SECURE_S_BIU 13
+#define SRST_P_SECURE_S_BIU 14
+#define SRST_CRYPTO_CORE 15
+/********Name=SECURE_SOFTRST_CON01,Offset=0xA04********/
+#define SRST_CRYPTO_PKA 16
+#define SRST_CRYPTO_RNG 17
+#define SRST_A_CRYPTO 18
+#define SRST_H_CRYPTO 19
+#define SRST_KEYLADDER_CORE 25
+#define SRST_KEYLADDER_RNG 26
+#define SRST_A_KEYLADDER 27
+#define SRST_H_KEYLADDER 28
+#define SRST_P_OTPC_S 29
+#define SRST_OTPC_S 30
+#define SRST_WDT_S 31
+/********Name=SECURE_SOFTRST_CON02,Offset=0xA08********/
+#define SRST_T_WDT_S 32
+#define SRST_H_BOOTROM 33
+#define SRST_A_DCF 34
+#define SRST_P_DCF 35
+#define SRST_H_BOOTROM_NS 37
+#define SRST_P_KEYLADDER 46
+#define SRST_H_TRNG_S 47
+/********Name=SECURE_SOFTRST_CON03,Offset=0xA0C********/
+#define SRST_H_TRNG_NS 48
+#define SRST_D_SDMMC_BUFFER 49
+#define SRST_H_SDMMC 50
+#define SRST_H_SDMMC_BUFFER 51
+#define SRST_SDMMC 52
+#define SRST_P_TRNG_CHK 53
+#define SRST_TRNG_S 54
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/drm_mipi_dsi.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/drm_mipi_dsi.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/drm_mipi_dsi.h (revision 151)
@@ -0,0 +1,53 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
+ * Authors:
+ * Mark Yao <yzq@rock-chips.com>
+ *
+ * based on include/drm/drm_mipi_dsi.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DRM_MIPI_DSI_H__
+#define _DRM_MIPI_DSI_H__
+
+/* DSI mode flags */
+
+/* video mode */
+#define MIPI_DSI_MODE_VIDEO (1 << 0)
+/* video burst mode */
+#define MIPI_DSI_MODE_VIDEO_BURST (1 << 1)
+/* video pulse mode */
+#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE (1 << 2)
+/* enable auto vertical count mode */
+#define MIPI_DSI_MODE_VIDEO_AUTO_VERT (1 << 3)
+/* enable hsync-end packets in vsync-pulse and v-porch area */
+#define MIPI_DSI_MODE_VIDEO_HSE (1 << 4)
+/* disable hfront-porch area */
+#define MIPI_DSI_MODE_VIDEO_HFP (1 << 5)
+/* disable hback-porch area */
+#define MIPI_DSI_MODE_VIDEO_HBP (1 << 6)
+/* disable hsync-active area */
+#define MIPI_DSI_MODE_VIDEO_HSA (1 << 7)
+/* flush display FIFO on vsync pulse */
+#define MIPI_DSI_MODE_VSYNC_FLUSH (1 << 8)
+/* disable EoT packets in HS mode */
+#define MIPI_DSI_MODE_EOT_PACKET (1 << 9)
+/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+#define MIPI_DSI_CLOCK_NON_CONTINUOUS (1 << 10)
+/* transmit data in low power */
+#define MIPI_DSI_MODE_LPM (1 << 11)
+
+#define MIPI_DSI_FMT_RGB888 0
+#define MIPI_DSI_FMT_RGB666 1
+#define MIPI_DSI_FMT_RGB666_PACKED 2
+#define MIPI_DSI_FMT_RGB565 3
+
+#define MIPI_CSI_FMT_RAW8 0x10
+#define MIPI_CSI_FMT_RAW10 0x11
+
+#endif /* __DRM_MIPI_DSI__ */
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/media-bus-format.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/media-bus-format.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/media-bus-format.h (revision 151)
@@ -0,0 +1,2 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#include "../../uapi/linux/media-bus-format.h"
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/mipi_dsi.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/mipi_dsi.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/mipi_dsi.h (revision 151)
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+drivers/video/rockchip/transmitter/mipi_dsi.h
+*/
+#ifndef MIPI_DSI_H_
+#define MIPI_DSI_H_
+
+#ifdef CONFIG_MIPI_DSI_FT
+#include "..\..\common\config.h"
+#endif
+
+//DSI DATA TYPE
+#define DTYPE_DCS_SWRITE_0P 0x05
+#define DTYPE_DCS_SWRITE_1P 0x15
+#define DTYPE_DCS_LWRITE 0x39
+#define DTYPE_GEN_LWRITE 0x29
+#define DTYPE_GEN_SWRITE_2P 0x23
+#define DTYPE_GEN_SWRITE_1P 0x13
+#define DTYPE_GEN_SWRITE_0P 0x03
+
+//command transmit mode
+#define HSDT 0x00
+#define LPDT 0x01
+
+//DSI DATA TYPE FLAG
+#define DATA_TYPE_DCS 0x00
+#define DATA_TYPE_GEN 0x01
+
+//Video Mode
+#define VM_NBMWSP 0x00 //Non burst mode with sync pulses
+#define VM_NBMWSE 0x01 //Non burst mode with sync events
+#define VM_BM 0x02 //Burst mode
+
+//Video Pixel Format
+#define VPF_16BPP 0x00
+#define VPF_18BPP 0x01 //packed
+#define VPF_18BPPL 0x02 //loosely packed
+#define VPF_24BPP 0x03
+
+//Display Command Set
+#define dcs_enter_idle_mode 0x39
+#define dcs_enter_invert_mode 0x21
+#define dcs_enter_normal_mode 0x13
+#define dcs_enter_partial_mode 0x12
+#define dcs_enter_sleep_mode 0x10
+#define dcs_exit_idle_mode 0x38
+#define dcs_exit_invert_mode 0x20
+#define dcs_exit_sleep_mode 0x11
+#define dcs_get_address_mode 0x0b
+#define dcs_get_blue_channel 0x08
+#define dcs_get_diagnostic_result 0x0f
+#define dcs_get_display_mode 0x0d
+#define dcs_get_green_channel 0x07
+#define dcs_get_pixel_format 0x0c
+#define dcs_get_power_mode 0x0a
+#define dcs_get_red_channel 0x06
+#define dcs_get_scanline 0x45
+#define dcs_get_signal_mode 0x0e
+#define dcs_nop 0x00
+#define dcs_read_DDB_continue 0xa8
+#define dcs_read_DDB_start 0xa1
+#define dcs_read_memory_continue 0x3e
+#define dcs_read_memory_start 0x2e
+#define dcs_set_address_mode 0x36
+#define dcs_set_column_address 0x2a
+#define dcs_set_display_off 0x28
+#define dcs_set_display_on 0x29
+#define dcs_set_gamma_curve 0x26
+#define dcs_set_page_address 0x2b
+#define dcs_set_partial_area 0x30
+#define dcs_set_pixel_format 0x3a
+#define dcs_set_scroll_area 0x33
+#define dcs_set_scroll_start 0x37
+#define dcs_set_tear_off 0x34
+#define dcs_set_tear_on 0x35
+#define dcs_set_tear_scanline 0x44
+#define dcs_soft_reset 0x01
+#define dcs_write_LUT 0x2d
+#define dcs_write_memory_continue 0x3c
+#define dcs_write_memory_start 0x2c
+
+#ifndef MHz
+#define MHz 1000000
+#endif
+
+
+#if 0
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long s64;
+typedef unsigned long u64;
+#endif
+
+
+//iomux
+#define OLD_RK_IOMUX 0
+
+
+#endif /* end of MIPI_DSI_H_ */
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/rockchip_vop.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/rockchip_vop.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/display/rockchip_vop.h (revision 151)
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+
+#ifndef _DT_BINDINGS_ROCKCHIP_VOP_H
+#define _DT_BINDINGS_ROCKCHIP_VOP_H
+
+#define ROCKCHIP_VOP2_CLUSTER0 0
+#define ROCKCHIP_VOP2_CLUSTER1 1
+#define ROCKCHIP_VOP2_ESMART0 2
+#define ROCKCHIP_VOP2_ESMART1 3
+#define ROCKCHIP_VOP2_SMART0 4
+#define ROCKCHIP_VOP2_SMART1 5
+#define ROCKCHIP_VOP2_CLUSTER2 6
+#define ROCKCHIP_VOP2_CLUSTER3 7
+#define ROCKCHIP_VOP2_ESMART2 8
+#define ROCKCHIP_VOP2_ESMART3 9
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/input/rk-input.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/input/rk-input.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/input/rk-input.h (revision 151)
@@ -0,0 +1,814 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device properties and quirks
+ */
+
+#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
+#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
+#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
+#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
+
+#define INPUT_PROP_MAX 0x1f
+#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
+
+/*
+ * Event types
+ */
+
+#define EV_SYN 0x00
+#define EV_KEY 0x01
+#define EV_REL 0x02
+#define EV_ABS 0x03
+#define EV_MSC 0x04
+#define EV_SW 0x05
+#define EV_LED 0x11
+#define EV_SND 0x12
+#define EV_REP 0x14
+#define EV_FF 0x15
+#define EV_PWR 0x16
+#define EV_FF_STATUS 0x17
+#define EV_MAX 0x1f
+#define EV_CNT (EV_MAX+1)
+
+/*
+ * Synchronization events.
+ */
+
+#define SYN_REPORT 0
+#define SYN_CONFIG 1
+#define SYN_MT_REPORT 2
+#define SYN_DROPPED 3
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED 0
+#define KEY_ESC 1
+#define KEY_1 2
+#define KEY_2 3
+#define KEY_3 4
+#define KEY_4 5
+#define KEY_5 6
+#define KEY_6 7
+#define KEY_7 8
+#define KEY_8 9
+#define KEY_9 10
+#define KEY_0 11
+#define KEY_MINUS 12
+#define KEY_EQUAL 13
+#define KEY_BACKSPACE 14
+#define KEY_TAB 15
+#define KEY_Q 16
+#define KEY_W 17
+#define KEY_E 18
+#define KEY_R 19
+#define KEY_T 20
+#define KEY_Y 21
+#define KEY_U 22
+#define KEY_I 23
+#define KEY_O 24
+#define KEY_P 25
+#define KEY_LEFTBRACE 26
+#define KEY_RIGHTBRACE 27
+#define KEY_ENTER 28
+#define KEY_LEFTCTRL 29
+#define KEY_A 30
+#define KEY_S 31
+#define KEY_D 32
+#define KEY_F 33
+#define KEY_G 34
+#define KEY_H 35
+#define KEY_J 36
+#define KEY_K 37
+#define KEY_L 38
+#define KEY_SEMICOLON 39
+#define KEY_APOSTROPHE 40
+#define KEY_GRAVE 41
+#define KEY_LEFTSHIFT 42
+#define KEY_BACKSLASH 43
+#define KEY_Z 44
+#define KEY_X 45
+#define KEY_C 46
+#define KEY_V 47
+#define KEY_B 48
+#define KEY_N 49
+#define KEY_M 50
+#define KEY_COMMA 51
+#define KEY_DOT 52
+#define KEY_SLASH 53
+#define KEY_RIGHTSHIFT 54
+#define KEY_KPASTERISK 55
+#define KEY_LEFTALT 56
+#define KEY_SPACE 57
+#define KEY_CAPSLOCK 58
+#define KEY_F1 59
+#define KEY_F2 60
+#define KEY_F3 61
+#define KEY_F4 62
+#define KEY_F5 63
+#define KEY_F6 64
+#define KEY_F7 65
+#define KEY_F8 66
+#define KEY_F9 67
+#define KEY_F10 68
+#define KEY_NUMLOCK 69
+#define KEY_SCROLLLOCK 70
+#define KEY_KP7 71
+#define KEY_KP8 72
+#define KEY_KP9 73
+#define KEY_KPMINUS 74
+#define KEY_KP4 75
+#define KEY_KP5 76
+#define KEY_KP6 77
+#define KEY_KPPLUS 78
+#define KEY_KP1 79
+#define KEY_KP2 80
+#define KEY_KP3 81
+#define KEY_KP0 82
+#define KEY_KPDOT 83
+
+#define KEY_ZENKAKUHANKAKU 85
+#define KEY_102ND 86
+#define KEY_F11 87
+#define KEY_F12 88
+#define KEY_RO 89
+#define KEY_KATAKANA 90
+#define KEY_HIRAGANA 91
+#define KEY_HENKAN 92
+#define KEY_KATAKANAHIRAGANA 93
+#define KEY_MUHENKAN 94
+#define KEY_KPJPCOMMA 95
+#define KEY_KPENTER 96
+#define KEY_RIGHTCTRL 97
+#define KEY_KPSLASH 98
+#define KEY_SYSRQ 99
+#define KEY_RIGHTALT 100
+#define KEY_LINEFEED 101
+#define KEY_HOME 102
+#define KEY_UP 103
+#define KEY_PAGEUP 104
+#define KEY_LEFT 105
+#define KEY_RIGHT 106
+#define KEY_END 107
+#define KEY_DOWN 108
+#define KEY_PAGEDOWN 109
+#define KEY_INSERT 110
+#define KEY_DELETE 111
+#define KEY_MACRO 112
+#define KEY_MUTE 113
+#define KEY_VOLUMEDOWN 114
+#define KEY_VOLUMEUP 115
+#define KEY_POWER 116 /* SC System Power Down */
+#define KEY_KPEQUAL 117
+#define KEY_KPPLUSMINUS 118
+#define KEY_PAUSE 119
+#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA 121
+#define KEY_HANGEUL 122
+#define KEY_HANGUEL KEY_HANGEUL
+#define KEY_HANJA 123
+#define KEY_YEN 124
+#define KEY_LEFTMETA 125
+#define KEY_RIGHTMETA 126
+#define KEY_COMPOSE 127
+
+#define KEY_STOP 128 /* AC Stop */
+#define KEY_AGAIN 129
+#define KEY_PROPS 130 /* AC Properties */
+#define KEY_UNDO 131 /* AC Undo */
+#define KEY_FRONT 132
+#define KEY_COPY 133 /* AC Copy */
+#define KEY_OPEN 134 /* AC Open */
+#define KEY_PASTE 135 /* AC Paste */
+#define KEY_FIND 136 /* AC Search */
+#define KEY_CUT 137 /* AC Cut */
+#define KEY_HELP 138 /* AL Integrated Help Center */
+#define KEY_MENU 139 /* Menu (show menu) */
+#define KEY_CALC 140 /* AL Calculator */
+#define KEY_SETUP 141
+#define KEY_SLEEP 142 /* SC System Sleep */
+#define KEY_WAKEUP 143 /* System Wake Up */
+#define KEY_FILE 144 /* AL Local Machine Browser */
+#define KEY_SENDFILE 145
+#define KEY_DELETEFILE 146
+#define KEY_XFER 147
+#define KEY_PROG1 148
+#define KEY_PROG2 149
+#define KEY_WWW 150 /* AL Internet Browser */
+#define KEY_MSDOS 151
+#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK KEY_COFFEE
+#define KEY_DIRECTION 153
+#define KEY_CYCLEWINDOWS 154
+#define KEY_MAIL 155
+#define KEY_BOOKMARKS 156 /* AC Bookmarks */
+#define KEY_COMPUTER 157
+#define KEY_BACK 158 /* AC Back */
+#define KEY_FORWARD 159 /* AC Forward */
+#define KEY_CLOSECD 160
+#define KEY_EJECTCD 161
+#define KEY_EJECTCLOSECD 162
+#define KEY_NEXTSONG 163
+#define KEY_PLAYPAUSE 164
+#define KEY_PREVIOUSSONG 165
+#define KEY_STOPCD 166
+#define KEY_RECORD 167
+#define KEY_REWIND 168
+#define KEY_PHONE 169 /* Media Select Telephone */
+#define KEY_ISO 170
+#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE 172 /* AC Home */
+#define KEY_REFRESH 173 /* AC Refresh */
+#define KEY_EXIT 174 /* AC Exit */
+#define KEY_MOVE 175
+#define KEY_EDIT 176
+#define KEY_SCROLLUP 177
+#define KEY_SCROLLDOWN 178
+#define KEY_KPLEFTPAREN 179
+#define KEY_KPRIGHTPAREN 180
+#define KEY_NEW 181 /* AC New */
+#define KEY_REDO 182 /* AC Redo/Repeat */
+
+#define KEY_F13 183
+#define KEY_F14 184
+#define KEY_F15 185
+#define KEY_F16 186
+#define KEY_F17 187
+#define KEY_F18 188
+#define KEY_F19 189
+#define KEY_F20 190
+#define KEY_F21 191
+#define KEY_F22 192
+#define KEY_F23 193
+#define KEY_F24 194
+
+#define KEY_PLAYCD 200
+#define KEY_PAUSECD 201
+#define KEY_PROG3 202
+#define KEY_PROG4 203
+#define KEY_DASHBOARD 204 /* AL Dashboard */
+#define KEY_SUSPEND 205
+#define KEY_CLOSE 206 /* AC Close */
+#define KEY_PLAY 207
+#define KEY_FASTFORWARD 208
+#define KEY_BASSBOOST 209
+#define KEY_PRINT 210 /* AC Print */
+#define KEY_HP 211
+#define KEY_CAMERA 212
+#define KEY_SOUND 213
+#define KEY_QUESTION 214
+#define KEY_EMAIL 215
+#define KEY_CHAT 216
+#define KEY_SEARCH 217
+#define KEY_CONNECT 218
+#define KEY_FINANCE 219 /* AL Checkbook/Finance */
+#define KEY_SPORT 220
+#define KEY_SHOP 221
+#define KEY_ALTERASE 222
+#define KEY_CANCEL 223 /* AC Cancel */
+#define KEY_BRIGHTNESSDOWN 224
+#define KEY_BRIGHTNESSUP 225
+#define KEY_MEDIA 226
+
+#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
+ outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE 228
+#define KEY_KBDILLUMDOWN 229
+#define KEY_KBDILLUMUP 230
+
+#define KEY_SEND 231 /* AC Send */
+#define KEY_REPLY 232 /* AC Reply */
+#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
+#define KEY_SAVE 234 /* AC Save */
+#define KEY_DOCUMENTS 235
+
+#define KEY_BATTERY 236
+
+#define KEY_BLUETOOTH 237
+#define KEY_WLAN 238
+#define KEY_UWB 239
+
+#define KEY_UNKNOWN 240
+
+#define KEY_VIDEO_NEXT 241 /* drive next video source */
+#define KEY_VIDEO_PREV 242 /* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
+#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
+ brightness control is off,
+ rely on ambient */
+#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
+#define KEY_DISPLAY_OFF 245 /* display device to off state */
+
+#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
+#define KEY_WIMAX KEY_WWAN
+#define KEY_RFKILL 247 /* Key that controls all radios */
+
+#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC 0x100
+#define BTN_0 0x100
+#define BTN_1 0x101
+#define BTN_2 0x102
+#define BTN_3 0x103
+#define BTN_4 0x104
+#define BTN_5 0x105
+#define BTN_6 0x106
+#define BTN_7 0x107
+#define BTN_8 0x108
+#define BTN_9 0x109
+
+#define BTN_MOUSE 0x110
+#define BTN_LEFT 0x110
+#define BTN_RIGHT 0x111
+#define BTN_MIDDLE 0x112
+#define BTN_SIDE 0x113
+#define BTN_EXTRA 0x114
+#define BTN_FORWARD 0x115
+#define BTN_BACK 0x116
+#define BTN_TASK 0x117
+
+#define BTN_JOYSTICK 0x120
+#define BTN_TRIGGER 0x120
+#define BTN_THUMB 0x121
+#define BTN_THUMB2 0x122
+#define BTN_TOP 0x123
+#define BTN_TOP2 0x124
+#define BTN_PINKIE 0x125
+#define BTN_BASE 0x126
+#define BTN_BASE2 0x127
+#define BTN_BASE3 0x128
+#define BTN_BASE4 0x129
+#define BTN_BASE5 0x12a
+#define BTN_BASE6 0x12b
+#define BTN_DEAD 0x12f
+
+#define BTN_GAMEPAD 0x130
+#define BTN_SOUTH 0x130
+#define BTN_A BTN_SOUTH
+#define BTN_EAST 0x131
+#define BTN_B BTN_EAST
+#define BTN_C 0x132
+#define BTN_NORTH 0x133
+#define BTN_X BTN_NORTH
+#define BTN_WEST 0x134
+#define BTN_Y BTN_WEST
+#define BTN_Z 0x135
+#define BTN_TL 0x136
+#define BTN_TR 0x137
+#define BTN_TL2 0x138
+#define BTN_TR2 0x139
+#define BTN_SELECT 0x13a
+#define BTN_START 0x13b
+#define BTN_MODE 0x13c
+#define BTN_THUMBL 0x13d
+#define BTN_THUMBR 0x13e
+
+#define BTN_DIGI 0x140
+#define BTN_TOOL_PEN 0x140
+#define BTN_TOOL_RUBBER 0x141
+#define BTN_TOOL_BRUSH 0x142
+#define BTN_TOOL_PENCIL 0x143
+#define BTN_TOOL_AIRBRUSH 0x144
+#define BTN_TOOL_FINGER 0x145
+#define BTN_TOOL_MOUSE 0x146
+#define BTN_TOOL_LENS 0x147
+#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
+#define BTN_TOUCH 0x14a
+#define BTN_STYLUS 0x14b
+#define BTN_STYLUS2 0x14c
+#define BTN_TOOL_DOUBLETAP 0x14d
+#define BTN_TOOL_TRIPLETAP 0x14e
+#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
+
+#define BTN_WHEEL 0x150
+#define BTN_GEAR_DOWN 0x150
+#define BTN_GEAR_UP 0x151
+
+#define KEY_OK 0x160
+#define KEY_SELECT 0x161
+#define KEY_GOTO 0x162
+#define KEY_CLEAR 0x163
+#define KEY_POWER2 0x164
+#define KEY_OPTION 0x165
+#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME 0x167
+#define KEY_VENDOR 0x168
+#define KEY_ARCHIVE 0x169
+#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
+#define KEY_CHANNEL 0x16b
+#define KEY_FAVORITES 0x16c
+#define KEY_EPG 0x16d
+#define KEY_PVR 0x16e /* Media Select Home */
+#define KEY_MHP 0x16f
+#define KEY_LANGUAGE 0x170
+#define KEY_TITLE 0x171
+#define KEY_SUBTITLE 0x172
+#define KEY_ANGLE 0x173
+#define KEY_ZOOM 0x174
+#define KEY_MODE 0x175
+#define KEY_KEYBOARD 0x176
+#define KEY_SCREEN 0x177
+#define KEY_PC 0x178 /* Media Select Computer */
+#define KEY_TV 0x179 /* Media Select TV */
+#define KEY_TV2 0x17a /* Media Select Cable */
+#define KEY_VCR 0x17b /* Media Select VCR */
+#define KEY_VCR2 0x17c /* VCR Plus */
+#define KEY_SAT 0x17d /* Media Select Satellite */
+#define KEY_SAT2 0x17e
+#define KEY_CD 0x17f /* Media Select CD */
+#define KEY_TAPE 0x180 /* Media Select Tape */
+#define KEY_RADIO 0x181
+#define KEY_TUNER 0x182 /* Media Select Tuner */
+#define KEY_PLAYER 0x183
+#define KEY_TEXT 0x184
+#define KEY_DVD 0x185 /* Media Select DVD */
+#define KEY_AUX 0x186
+#define KEY_MP3 0x187
+#define KEY_AUDIO 0x188 /* AL Audio Browser */
+#define KEY_VIDEO 0x189 /* AL Movie Browser */
+#define KEY_DIRECTORY 0x18a
+#define KEY_LIST 0x18b
+#define KEY_MEMO 0x18c /* Media Select Messages */
+#define KEY_CALENDAR 0x18d
+#define KEY_RED 0x18e
+#define KEY_GREEN 0x18f
+#define KEY_YELLOW 0x190
+#define KEY_BLUE 0x191
+#define KEY_CHANNELUP 0x192 /* Channel Increment */
+#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
+#define KEY_FIRST 0x194
+#define KEY_LAST 0x195 /* Recall Last */
+#define KEY_AB 0x196
+#define KEY_NEXT 0x197
+#define KEY_RESTART 0x198
+#define KEY_SLOW 0x199
+#define KEY_SHUFFLE 0x19a
+#define KEY_BREAK 0x19b
+#define KEY_PREVIOUS 0x19c
+#define KEY_DIGITS 0x19d
+#define KEY_TEEN 0x19e
+#define KEY_TWEN 0x19f
+#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
+#define KEY_GAMES 0x1a1 /* Media Select Games */
+#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
+#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
+#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
+#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
+#define KEY_EDITOR 0x1a6 /* AL Text Editor */
+#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
+#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
+#define KEY_DATABASE 0x1aa /* AL Database App */
+#define KEY_NEWS 0x1ab /* AL Newsreader */
+#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
+#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
+#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
+#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
+#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
+#define KEY_LOGOFF 0x1b1 /* AL Logoff */
+
+#define KEY_DOLLAR 0x1b2
+#define KEY_EURO 0x1b3
+
+#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
+#define KEY_FRAMEFORWARD 0x1b5
+#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
+#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
+#define KEY_IMAGES 0x1ba /* AL Image Browser */
+
+#define KEY_DEL_EOL 0x1c0
+#define KEY_DEL_EOS 0x1c1
+#define KEY_INS_LINE 0x1c2
+#define KEY_DEL_LINE 0x1c3
+
+#define KEY_FN 0x1d0
+#define KEY_FN_ESC 0x1d1
+#define KEY_FN_F1 0x1d2
+#define KEY_FN_F2 0x1d3
+#define KEY_FN_F3 0x1d4
+#define KEY_FN_F4 0x1d5
+#define KEY_FN_F5 0x1d6
+#define KEY_FN_F6 0x1d7
+#define KEY_FN_F7 0x1d8
+#define KEY_FN_F8 0x1d9
+#define KEY_FN_F9 0x1da
+#define KEY_FN_F10 0x1db
+#define KEY_FN_F11 0x1dc
+#define KEY_FN_F12 0x1dd
+#define KEY_FN_1 0x1de
+#define KEY_FN_2 0x1df
+#define KEY_FN_D 0x1e0
+#define KEY_FN_E 0x1e1
+#define KEY_FN_F 0x1e2
+#define KEY_FN_S 0x1e3
+#define KEY_FN_B 0x1e4
+
+#define KEY_BRL_DOT1 0x1f1
+#define KEY_BRL_DOT2 0x1f2
+#define KEY_BRL_DOT3 0x1f3
+#define KEY_BRL_DOT4 0x1f4
+#define KEY_BRL_DOT5 0x1f5
+#define KEY_BRL_DOT6 0x1f6
+#define KEY_BRL_DOT7 0x1f7
+#define KEY_BRL_DOT8 0x1f8
+#define KEY_BRL_DOT9 0x1f9
+#define KEY_BRL_DOT10 0x1fa
+
+#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
+#define KEY_NUMERIC_1 0x201 /* and other keypads */
+#define KEY_NUMERIC_2 0x202
+#define KEY_NUMERIC_3 0x203
+#define KEY_NUMERIC_4 0x204
+#define KEY_NUMERIC_5 0x205
+#define KEY_NUMERIC_6 0x206
+#define KEY_NUMERIC_7 0x207
+#define KEY_NUMERIC_8 0x208
+#define KEY_NUMERIC_9 0x209
+#define KEY_NUMERIC_STAR 0x20a
+#define KEY_NUMERIC_POUND 0x20b
+
+#define KEY_CAMERA_FOCUS 0x210
+#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON 0x213
+#define KEY_TOUCHPAD_OFF 0x214
+
+#define KEY_CAMERA_ZOOMIN 0x215
+#define KEY_CAMERA_ZOOMOUT 0x216
+#define KEY_CAMERA_UP 0x217
+#define KEY_CAMERA_DOWN 0x218
+#define KEY_CAMERA_LEFT 0x219
+#define KEY_CAMERA_RIGHT 0x21a
+
+#define KEY_ATTENDANT_ON 0x21b
+#define KEY_ATTENDANT_OFF 0x21c
+#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
+
+#define BTN_DPAD_UP 0x220
+#define BTN_DPAD_DOWN 0x221
+#define BTN_DPAD_LEFT 0x222
+#define BTN_DPAD_RIGHT 0x223
+
+#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
+
+#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
+#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
+#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
+#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
+#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
+#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
+#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
+
+#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
+#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
+
+#define BTN_TRIGGER_HAPPY 0x2c0
+#define BTN_TRIGGER_HAPPY1 0x2c0
+#define BTN_TRIGGER_HAPPY2 0x2c1
+#define BTN_TRIGGER_HAPPY3 0x2c2
+#define BTN_TRIGGER_HAPPY4 0x2c3
+#define BTN_TRIGGER_HAPPY5 0x2c4
+#define BTN_TRIGGER_HAPPY6 0x2c5
+#define BTN_TRIGGER_HAPPY7 0x2c6
+#define BTN_TRIGGER_HAPPY8 0x2c7
+#define BTN_TRIGGER_HAPPY9 0x2c8
+#define BTN_TRIGGER_HAPPY10 0x2c9
+#define BTN_TRIGGER_HAPPY11 0x2ca
+#define BTN_TRIGGER_HAPPY12 0x2cb
+#define BTN_TRIGGER_HAPPY13 0x2cc
+#define BTN_TRIGGER_HAPPY14 0x2cd
+#define BTN_TRIGGER_HAPPY15 0x2ce
+#define BTN_TRIGGER_HAPPY16 0x2cf
+#define BTN_TRIGGER_HAPPY17 0x2d0
+#define BTN_TRIGGER_HAPPY18 0x2d1
+#define BTN_TRIGGER_HAPPY19 0x2d2
+#define BTN_TRIGGER_HAPPY20 0x2d3
+#define BTN_TRIGGER_HAPPY21 0x2d4
+#define BTN_TRIGGER_HAPPY22 0x2d5
+#define BTN_TRIGGER_HAPPY23 0x2d6
+#define BTN_TRIGGER_HAPPY24 0x2d7
+#define BTN_TRIGGER_HAPPY25 0x2d8
+#define BTN_TRIGGER_HAPPY26 0x2d9
+#define BTN_TRIGGER_HAPPY27 0x2da
+#define BTN_TRIGGER_HAPPY28 0x2db
+#define BTN_TRIGGER_HAPPY29 0x2dc
+#define BTN_TRIGGER_HAPPY30 0x2dd
+#define BTN_TRIGGER_HAPPY31 0x2de
+#define BTN_TRIGGER_HAPPY32 0x2df
+#define BTN_TRIGGER_HAPPY33 0x2e0
+#define BTN_TRIGGER_HAPPY34 0x2e1
+#define BTN_TRIGGER_HAPPY35 0x2e2
+#define BTN_TRIGGER_HAPPY36 0x2e3
+#define BTN_TRIGGER_HAPPY37 0x2e4
+#define BTN_TRIGGER_HAPPY38 0x2e5
+#define BTN_TRIGGER_HAPPY39 0x2e6
+#define BTN_TRIGGER_HAPPY40 0x2e7
+
+/* We avoid low common keys in module aliases so they don't get huge. */
+#define KEY_MIN_INTERESTING KEY_MUTE
+#define KEY_MAX 0x2ff
+#define KEY_CNT (KEY_MAX+1)
+
+/*
+ * Relative axes
+ */
+
+#define REL_X 0x00
+#define REL_Y 0x01
+#define REL_Z 0x02
+#define REL_RX 0x03
+#define REL_RY 0x04
+#define REL_RZ 0x05
+#define REL_HWHEEL 0x06
+#define REL_DIAL 0x07
+#define REL_WHEEL 0x08
+#define REL_MISC 0x09
+#define REL_MAX 0x0f
+#define REL_CNT (REL_MAX+1)
+
+/*
+ * Absolute axes
+ */
+
+#define ABS_X 0x00
+#define ABS_Y 0x01
+#define ABS_Z 0x02
+#define ABS_RX 0x03
+#define ABS_RY 0x04
+#define ABS_RZ 0x05
+#define ABS_THROTTLE 0x06
+#define ABS_RUDDER 0x07
+#define ABS_WHEEL 0x08
+#define ABS_GAS 0x09
+#define ABS_BRAKE 0x0a
+#define ABS_HAT0X 0x10
+#define ABS_HAT0Y 0x11
+#define ABS_HAT1X 0x12
+#define ABS_HAT1Y 0x13
+#define ABS_HAT2X 0x14
+#define ABS_HAT2Y 0x15
+#define ABS_HAT3X 0x16
+#define ABS_HAT3Y 0x17
+#define ABS_PRESSURE 0x18
+#define ABS_DISTANCE 0x19
+#define ABS_TILT_X 0x1a
+#define ABS_TILT_Y 0x1b
+#define ABS_TOOL_WIDTH 0x1c
+
+#define ABS_VOLUME 0x20
+
+#define ABS_MISC 0x28
+
+#define ABS_MT_SLOT 0x2f /* MT slot being modified */
+#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
+#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
+#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
+#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
+#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
+#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
+#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
+#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
+#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
+#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
+#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
+#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
+#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
+#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
+
+
+#define ABS_MAX 0x3f
+#define ABS_CNT (ABS_MAX+1)
+
+/*
+ * Switch events
+ */
+
+#define SW_LID 0x00 /* set = lid shut */
+#define SW_TABLET_MODE 0x01 /* set = tablet mode */
+#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
+#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
+ set = radio enabled */
+#define SW_RADIO SW_RFKILL_ALL /* deprecated */
+#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
+#define SW_DOCK 0x05 /* set = plugged into dock */
+#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
+#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
+#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
+#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
+#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
+#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
+#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
+#define SW_LINEIN_INSERT 0x0d /* set = inserted */
+#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
+#define SW_MAX 0x0f
+#define SW_CNT (SW_MAX+1)
+
+/*
+ * Misc events
+ */
+
+#define MSC_SERIAL 0x00
+#define MSC_PULSELED 0x01
+#define MSC_GESTURE 0x02
+#define MSC_RAW 0x03
+#define MSC_SCAN 0x04
+#define MSC_TIMESTAMP 0x05
+#define MSC_MAX 0x07
+#define MSC_CNT (MSC_MAX+1)
+
+/*
+ * LEDs
+ */
+
+#define LED_NUML 0x00
+#define LED_CAPSL 0x01
+#define LED_SCROLLL 0x02
+#define LED_COMPOSE 0x03
+#define LED_KANA 0x04
+#define LED_SLEEP 0x05
+#define LED_SUSPEND 0x06
+#define LED_MUTE 0x07
+#define LED_MISC 0x08
+#define LED_MAIL 0x09
+#define LED_CHARGING 0x0a
+#define LED_MAX 0x0f
+#define LED_CNT (LED_MAX+1)
+
+/*
+ * Autorepeat values
+ */
+
+#define REP_DELAY 0x00
+#define REP_PERIOD 0x01
+#define REP_MAX 0x01
+#define REP_CNT (REP_MAX+1)
+
+/*
+ * Sounds
+ */
+
+#define SND_CLICK 0x00
+#define SND_BELL 0x01
+#define SND_TONE 0x02
+#define SND_MAX 0x07
+#define SND_CNT (SND_MAX+1)
+
+/*
+ * IDs.
+ */
+
+#define ID_BUS 0
+#define ID_VENDOR 1
+#define ID_PRODUCT 2
+#define ID_VERSION 3
+
+#define BUS_PCI 0x01
+#define BUS_ISAPNP 0x02
+#define BUS_USB 0x03
+#define BUS_HIL 0x04
+#define BUS_BLUETOOTH 0x05
+#define BUS_VIRTUAL 0x06
+
+#define BUS_ISA 0x10
+#define BUS_I8042 0x11
+#define BUS_XTKBD 0x12
+#define BUS_RS232 0x13
+#define BUS_GAMEPORT 0x14
+#define BUS_PARPORT 0x15
+#define BUS_AMIGA 0x16
+#define BUS_ADB 0x17
+#define BUS_I2C 0x18
+#define BUS_HOST 0x19
+#define BUS_GSC 0x1A
+#define BUS_ATARI 0x1B
+#define BUS_SPI 0x1C
+
+/*
+ * MT_TOOL types
+ */
+#define MT_TOOL_FINGER 0
+#define MT_TOOL_PEN 1
+#define MT_TOOL_MAX 1
+
+/*
+ * Values describing the status of a force-feedback effect
+ */
+#define FF_STATUS_STOPPED 0x00
+#define FF_STATUS_PLAYING 0x01
+#define FF_STATUS_MAX 0x01
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/phy/phy-snps-pcie3.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/phy/phy-snps-pcie3.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/phy/phy-snps-pcie3.h (revision 151)
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _DT_BINDINGS_PHY_SNPS_PCIE3
+#define _DT_BINDINGS_PHY_SNPS_PCIE3
+
+/*
+ * pcie30_phy_mode[2:0]
+ * bit2: aggregation
+ * bit1: bifurcation for port 1
+ * bit0: bifurcation for port 0
+ */
+#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
+#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
+#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
+#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
+#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
+
+#endif /* _DT_BINDINGS_PHY_SNPS_PCIE3 */
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/sensor-dev.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/sensor-dev.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/sensor-dev.h (revision 151)
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__
+#define __DT_BINDINGS_ROCKCHIP_SENSORDEV_H__
+
+#define SENSOR_TYPE_NULL 0
+#define SENSOR_TYPE_ANGLE 1
+#define SENSOR_TYPE_ACCEL 2
+#define SENSOR_TYPE_COMPASS 3
+#define SENSOR_TYPE_GYROSCOPE 4
+#define SENSOR_TYPE_LIGHT 5
+#define SENSOR_TYPE_PROXIMITY 6
+#define SENSOR_TYPE_TEMPERATURE 7
+#define SENSOR_TYPE_PRESSURE 8
+#define SENSOR_TYPE_HALL 9
+#define SENSOR_NUM_TYPES 10
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip,boot-mode.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip,boot-mode.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip,boot-mode.h (revision 151)
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ROCKCHIP_BOOT_MODE_H
+#define __ROCKCHIP_BOOT_MODE_H
+
+/*high 24 bits is tag, low 8 bits is type*/
+#define REBOOT_FLAG 0x5242C300
+/* normal boot */
+#define BOOT_NORMAL (REBOOT_FLAG + 0)
+/* enter bootloader rockusb mode */
+#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
+/* enter recovery */
+#define BOOT_RECOVERY (REBOOT_FLAG + 3)
+/* reboot by panic */
+#define BOOT_PANIC (REBOOT_FLAG + 7)
+/* reboot by watchdog */
+#define BOOT_WATCHDOG (REBOOT_FLAG + 8)
+/* enter fastboot mode */
+#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
+/* enter charging mode */
+#define BOOT_CHARGING (REBOOT_FLAG + 11)
+/* enter usb mass storage mode */
+#define BOOT_UMS (REBOOT_FLAG + 12)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip-system-status.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip-system-status.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/soc/rockchip-system-status.h (revision 151)
@@ -0,0 +1,50 @@
+/*
+ *
+ * Copyright (C) 2017 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H
+#define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H
+
+#define SYS_STATUS_NORMAL (1 << 0)
+#define SYS_STATUS_SUSPEND (1 << 1)
+#define SYS_STATUS_IDLE (1 << 2)
+#define SYS_STATUS_REBOOT (1 << 3)
+#define SYS_STATUS_VIDEO_4K (1 << 4)
+#define SYS_STATUS_VIDEO_1080P (1 << 5)
+#define SYS_STATUS_GPU (1 << 6)
+#define SYS_STATUS_RGA (1 << 7)
+#define SYS_STATUS_CIF0 (1 << 8)
+#define SYS_STATUS_CIF1 (1 << 9)
+#define SYS_STATUS_LCDC0 (1 << 10)
+#define SYS_STATUS_LCDC1 (1 << 11)
+#define SYS_STATUS_BOOST (1 << 12)
+#define SYS_STATUS_PERFORMANCE (1 << 13)
+#define SYS_STATUS_ISP (1 << 14)
+#define SYS_STATUS_HDMI (1 << 15)
+#define SYS_STATUS_VIDEO_4K_10B (1 << 16)
+#define SYS_STATUS_LOW_POWER (1 << 17)
+#define SYS_STATUS_HDMIRX (1 << 18)
+#define SYS_STATUS_VIDEO_SVEP (1 << 19)
+
+#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \
+ SYS_STATUS_VIDEO_1080P | \
+ SYS_STATUS_VIDEO_4K_10B)
+#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1)
+
+#define DMC_FREQ_LEVEL_LOW (0x1 << 0)
+#define DMC_FREQ_LEVEL_MID_LOW (0x1 << 1)
+#define DMC_FREQ_LEVEL_MID_HIGH (0x1 << 2)
+#define DMC_FREQ_LEVEL_HIGH (0x1 << 3)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-px30.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-px30.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-px30.h (revision 151)
@@ -0,0 +1,53 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
+#define __DT_BINDINGS_ROCKCHIP_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_ARMPD BIT(0)
+#define RKPM_SLP_ARMOFF BIT(1)
+#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
+
+/* all plls except ddr's pll*/
+#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
+
+#define RKPM_SLP_CLK_GT BIT(16)
+#define RKPM_SLP_PMIC_LP BIT(17)
+
+#define RKPM_SLP_32K_EXT BIT(24)
+#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
+#define RKPM_SLP_PMU_DBG BIT(26)
+
+/* the wake up source */
+#define RKPM_CLUSTER_WKUP_EN BIT(0)
+#define RKPM_GPIO_WKUP_EN BIT(2)
+#define RKPM_SDIO_WKUP_EN BIT(3)
+#define RKPM_SDMMC_WKUP_EN BIT(4)
+#define RKPM_UART0_WKUP_EN BIT(5)
+#define RKPM_TIMER_WKUP_EN BIT(6)
+#define RKPM_USB_WKUP_EN BIT(7)
+#define RKPM_SFT_WKUP_EN BIT(8)
+#define RKPM_TIME_OUT_WKUP_EN BIT(10)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk1808.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk1808.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk1808.h (revision 151)
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ */
+
+#ifndef __DT_BINDINGS_RK1808_PM_H__
+#define __DT_BINDINGS_RK1808_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_ARMPD BIT(0)
+#define RKPM_SLP_ARMOFF BIT(1)
+#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
+
+/* all plls except ddr's pll*/
+#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
+
+#define RKPM_SLP_CLK_GT BIT(16)
+#define RKPM_SLP_PMIC_LP BIT(17)
+
+#define RKPM_SLP_32K_EXT BIT(24)
+#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
+#define RKPM_SLP_PMU_DBG BIT(26)
+
+/* the wake up source */
+#define RKPM_CLUSTER_WKUP_EN BIT(0)
+#define RKPM_GPIO_WKUP_EN BIT(2)
+#define RKPM_SDIO_WKUP_EN BIT(3)
+#define RKPM_SDMMC_WKUP_EN BIT(4)
+#define RKPM_UART0_WKUP_EN BIT(5)
+#define RKPM_TIMER_WKUP_EN BIT(6)
+#define RKPM_USB_WKUP_EN BIT(7)
+#define RKPM_SFT_WKUP_EN BIT(8)
+#define RKPM_VAD_WKUP_EN BIT(9)
+#define RKPM_TIME_OUT_WKUP_EN BIT(10)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk322x.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk322x.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk322x.h (revision 151)
@@ -0,0 +1,57 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__
+#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+/* the suspend mode */
+#define RKPM_CTR_PWR_DMNS BIT(0)
+#define RKPM_CTR_GTCLKS BIT(1)
+#define RKPM_CTR_PLLS BIT(2)
+#define RKPM_CTR_VOLTS BIT(3)
+#define RKPM_CTR_GPIOS BIT(4)
+#define RKPM_CTR_DDR BIT(5)
+#define RKPM_CTR_PMIC BIT(6)
+
+/* system clk is 24M,and div to min */
+#define RKPM_CTR_SYSCLK_DIV BIT(7)
+/* switch sysclk to 32k, need hardwart support, and div to min */
+#define RKPM_CTR_SYSCLK_32K BIT(8)
+/* switch sysclk to 32k,disable 24M OSC,
+ * need hardwart susport. and div to min
+ */
+#define RKPM_CTR_SYSCLK_OSC_DIS BIT(9)
+#define RKPM_CTR_VOL_PWM0 BIT(10)
+#define RKPM_CTR_VOL_PWM1 BIT(11)
+#define RKPM_CTR_VOL_PWM2 BIT(12)
+#define RKPM_CTR_VOL_PWM3 BIT(13)
+#define RKPM_CTR_BUS_IDLE BIT(14)
+#define RKPM_CTR_SRAM BIT(15)
+/*Low Power Function Selection*/
+#define RKPM_CTR_IDLESRAM_MD BIT(16)
+#define RKPM_CTR_IDLEAUTO_MD BIT(17)
+#define RKPM_CTR_ARMDP_LPMD BIT(18)
+#define RKPM_CTR_ARMOFF_LPMD BIT(19)
+#define RKPM_CTR_ARMLOGDP_LPMD BIT(20)
+#define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21)
+#define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3288.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3288.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3288.h (revision 151)
@@ -0,0 +1,59 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Power.xu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
+#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
+
+/* the suspend mode */
+#define RKPM_CTR_PWR_DMNS (1 << 0)
+#define RKPM_CTR_GTCLKS (1 << 1)
+#define RKPM_CTR_PLLS (1 << 2)
+#define RKPM_CTR_VOLTS (1 << 3)
+#define RKPM_CTR_GPIOS (1 << 4)
+#define RKPM_CTR_DDR (1 << 5)
+#define RKPM_CTR_PMIC (1 << 6)
+/* system clk is 24M,and div to min */
+#define RKPM_CTR_SYSCLK_DIV (1 << 7)
+/* switch sysclk to 32k, need hardwart support, and div to min */
+#define RKPM_CTR_SYSCLK_32K (1 << 8)
+/* switch sysclk to 32k,disable 24M OSC,
+ * need hardwart susport. and div to min
+ */
+#define RKPM_CTR_SYSCLK_OSC_DIS (1 << 9)
+#define RKPM_CTR_BUS_IDLE (1 << 14)
+#define RKPM_CTR_SRAM (1 << 15)
+/*Low Power Function Selection*/
+#define RKPM_CTR_IDLESRAM_MD (1 << 16)
+#define RKPM_CTR_IDLEAUTO_MD (1 << 17)
+#define RKPM_CTR_ARMDP_LPMD (1 << 18)
+#define RKPM_CTR_ARMOFF_LPMD (1 << 19)
+#define RKPM_CTR_ARMLOGDP_LPMD (1 << 20)
+#define RKPM_CTR_ARMOFF_LOGDP_LPMD (1 << 21)
+#define RKPM_CTR_ARMLOGOFF_DLPMD (1 << 22)
+
+/* the wake up source */
+#define RKPM_ARMINT_WKUP_EN (1 << 0)
+#define RKPM_SDMMC_WKUP_EN (1 << 2)
+#define RKPM_GPIO_WKUP_EN (1 << 3)
+
+/* the pwm regulator */
+#define PWM0_REGULATOR_EN (1 << 0)
+#define PWM1_REGULATOR_EN (1 << 1)
+#define PWM2_REGULATOR_EN (1 << 2)
+#define PWM3_REGULATOR_EN (1 << 3)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3308.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3308.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3308.h (revision 151)
@@ -0,0 +1,105 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Joseph Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_RK3308_PM_H__
+#define __DT_BINDINGS_RK3308_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+/*
+ * RK3308 system suspend mode configure definitions.
+ *
+ * Driver:
+ * These configures are pass to ATF by SMC in:
+ * drivers/soc/rockchip/rockchip_pm_config.c
+ *
+ * DTS:
+ * rockchip_suspend: rockchip-suspend {
+ * rockchip,sleep-mode-config = <...>;
+ * rockchip,wakeup-config = <...>;
+ * rockchip,apios-suspend = <...>;
+ * rockchip,pwm-regulator-config = <...>;
+ * };
+ */
+
+/*
+ * Suspend mode:
+ * rockchip,sleep-mode-config = <...>;
+ */
+#define RKPM_ARMOFF BIT(0) /* vdd_arm off */
+#define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */
+#define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */
+#define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */
+#define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */
+#define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */
+#define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */
+#define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */
+#define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */
+#define RKPM_PWM_VOLTAGE_DEFAULT BIT(10) /* pwm regulator default voltage (same with maskrom) */
+#define RKPM_PWM_VOLTAGE_DEFAULT_BS BIT(20) /* pwm regulator default voltage on 0.895v for RK3308BS chip */
+
+/*
+ * Regulator mode:
+ * rockchip,pwm-regulator-config = <...>;
+ */
+#define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */
+
+/*
+ * Wakeup source:
+ * rockchip,wakeup-config = <...>;
+ */
+#define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */
+#define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */
+#define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */
+#define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */
+#define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */
+#define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */
+#define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */
+#define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */
+#define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */
+
+/*
+ * Debug control in system suspend:
+ * rockchip,sleep-mode-config = <...>;
+ */
+#define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */
+#define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */
+#define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */
+#define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */
+#define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */
+#define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */
+#define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */
+#define RKPM_DBG_REG BIT(29) /* verbose regs */
+#define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */
+#define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */
+
+/*
+ * GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin:
+ * rockchip,apios-suspend = <...>;
+ */
+#define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */
+#define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */
+#define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */
+#define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */
+#define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */
+#define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */
+#define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */
+#define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3328.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3328.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3328.h (revision 151)
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ */
+#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
+#define __DT_BINDINGS_ROCKCHIP_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_CTR_VOL_PWM0 BIT(10)
+#define RKPM_SLP_CTR_VOL_PWM1 BIT(11)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3368.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3368.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3368.h (revision 151)
@@ -0,0 +1,56 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2015, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony.Xie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_ROCKCHIP_PM_H__
+#define __DT_BINDINGS_ROCKCHIP_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_WFI BIT(0)
+#define RKPM_SLP_ARMPD BIT(1)
+#define RKPM_SLP_ARMOFF BIT(2)
+#define RKPM_SLP_ARMOFF_LOGPD BIT(3)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(4)
+#define RKPM_RUNNING_ARMMODE BIT(5)
+
+/* func ctrl by pmu auto ctr */
+#define RKPM_SLP_PMU_PLLS_PWRDN BIT(8) /* all plls except ddr's pll*/
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
+
+/* func ctrl by software set */
+#define RKPM_SLP_SFT_PLLS_DEEP BIT(16) /* all plls except ddr's pll*/
+#define RKPM_SLP_SFT_32K_EXT BIT(17)
+#define RKPM_SLP_SFT_PD_PERI BIT(18)
+#define RKPM_SLP_SFT_PD_NBSCUS BIT(19) /* noboot scus in muti-cluster */
+
+/* the wake up source */
+#define RKPM_CLUSTER_L_WKUP_EN BIT(0)
+#define RKPM_CLUSTER_B_WKUPB_EN BIT(1)
+#define RKPM_GPIO_WKUP_EN BIT(2)
+#define RKPM_SDIO_WKUP_EN BIT(3)
+#define RKPM_SDMMC_WKUP_EN BIT(4)
+#define RKPM_SIM_WKUP_EN BIT(5)
+#define RKPM_TIMER_WKUP_EN BIT(6)
+#define RKPM_USB_WKUP_EN BIT(7)
+#define RKPM_SFT_WKUP_EN BIT(8)
+#define RKPM_WDT_M0_WKUP_EN BIT(9)
+#define RKPM_TIME_OUT_WKUP_EN BIT(10)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3399.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3399.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3399.h (revision 151)
@@ -0,0 +1,61 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Tony.Xie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__
+#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3399_H__
+
+/* the suspend mode */
+#define RKPM_SLP_WFI (1 << 0)
+#define RKPM_SLP_ARMPD (1 << 1)
+#define RKPM_SLP_PERILPPD (1 << 2)
+#define RKPM_SLP_DDR_RET (1 << 3)
+#define RKPM_SLP_PLLPD (1 << 4)
+#define RKPM_SLP_OSC_DIS (1 << 5)
+#define RKPM_SLP_CENTER_PD (1 << 6)
+#define RKPM_SLP_AP_PWROFF (1 << 7)
+
+/* the wake up source */
+#define RKPM_CLUSTER_L_WKUP_EN (1 << 0)
+#define RKPM_CLUSTER_B_WKUPB_EN (1 << 1)
+#define RKPM_GPIO_WKUP_EN (1 << 2)
+#define RKPM_SDIO_WKUP_EN (1 << 3)
+#define RKPM_SDMMC_WKUP_EN (1 << 4)
+#define RKPM_TIMER_WKUP_EN (1 << 6)
+#define RKPM_USB_WKUP_EN (1 << 7)
+#define RKPM_SFT_WKUP_EN (1 << 8)
+#define RKPM_WDT_M0_WKUP_EN (1 << 9)
+#define RKPM_TIME_OUT_WKUP_EN (1 << 10)
+#define RKPM_PWM_WKUP_EN (1 << 11)
+#define RKPM_PCIE_WKUP_EN (1 << 13)
+#define RKPM_USB_LINESTATE_WKUP_EN (1 << 14)
+
+/* the pwm regulator */
+#define PWM0_REGULATOR_EN (1 << 0)
+#define PWM1_REGULATOR_EN (1 << 1)
+#define PWM2_REGULATOR_EN (1 << 2)
+#define PWM3A_REGULATOR_EN (1 << 3)
+#define PWM3B_REGULATOR_EN (1 << 4)
+
+/* the APIO voltage domain */
+#define RKPM_APIO0_SUSPEND (1 << 0)
+#define RKPM_APIO1_SUSPEND (1 << 1)
+#define RKPM_APIO2_SUSPEND (1 << 2)
+#define RKPM_APIO3_SUSPEND (1 << 3)
+#define RKPM_APIO4_SUSPEND (1 << 4)
+#define RKPM_APIO5_SUSPEND (1 << 5)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3568.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3568.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3568.h (revision 151)
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2021, Rockchip Electronics Co., Ltd.
+ * Author: XiaoDong.Huang
+ */
+
+#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3568_H__
+#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3568_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_WFI BIT(0)
+#define RKPM_SLP_ARMOFF BIT(1)
+#define RKPM_SLP_CENTER_OFF BIT(2)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
+#define RKPM_SLP_FROM_UBOOT BIT(4)
+#define RKPM_SLP_PMIC_LP BIT(5)
+#define RKPM_SLP_HW_PLLS_OFF BIT(6)
+#define RKPM_SLP_PMUALIVE_32K BIT(7)
+#define RKPM_SLP_OSC_DIS BIT(8)
+#define RKPM_SLP_32K_EXT BIT(9)
+#define RKPM_SLP_32K_PVTM BIT(10)
+/* the wake up source */
+#define RKPM_CPU0_WKUP_EN BIT(0)
+#define RKPM_CPU1_WKUP_EN BIT(1)
+#define RKPM_CPU2_WKUP_EN BIT(2)
+#define RKPM_CPU3_WKUP_EN BIT(3)
+#define RKPM_GPIO_WKUP_EN BIT(4)
+#define RKPM_UART0_WKUP_EN BIT(5)
+#define RKPM_SDMMC0_WKUP_EN BIT(6)
+#define RKPM_SDMMC1_WKUP_EN BIT(7)
+#define RKPM_SDMMC2_WKUP_EN BIT(8)
+#define RKPM_USB_WKUP_EN BIT(9)
+#define RKPM_PCIE_WKUP_EN BIT(10)
+#define RKPM_VAD_WKUP_EN BIT(11)
+#define RKPM_TIMER_WKUP_EN BIT(12)
+#define RKPM_PWM0_WKUP_EN BIT(13)
+#define RKPM_TIMEOUT_WKUP_EN BIT(14)
+#define RKPM_SFT_WKUP_EN BIT(15)
+#define RKPM_USB_LINESTATE_WKUP_EN BIT(16)
+
+#define RKPM_SLP_LDO1_ON BIT(0)
+#define RKPM_SLP_LDO2_ON BIT(1)
+#define RKPM_SLP_LDO3_ON BIT(2)
+#define RKPM_SLP_LDO4_ON BIT(3)
+#define RKPM_SLP_LDO5_ON BIT(4)
+#define RKPM_SLP_LDO6_ON BIT(5)
+#define RKPM_SLP_LDO7_ON BIT(6)
+#define RKPM_SLP_LDO8_ON BIT(7)
+#define RKPM_SLP_LDO9_ON BIT(8)
+
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3588.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3588.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rk3588.h (revision 151)
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2022, Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ */
+
+#ifndef __DT_BINDINGS_RK3588_PM_H__
+#define __DT_BINDINGS_RK3588_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_ARMPD BIT(0)
+#define RKPM_SLP_ARMOFF BIT(1)
+#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
+#define RKPM_SLP_ARMOFF_PMUOFF BIT(4)
+
+/* all plls except ddr's pll*/
+#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
+
+#define RKPM_SLP_CLK_GT BIT(16)
+#define RKPM_SLP_PMIC_LP BIT(17)
+
+#define RKPM_SLP_32K_EXT BIT(24)
+#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
+#define RKPM_SLP_PMU_DBG BIT(26)
+
+/* the wake up source */
+#define RKPM_CPU0_WKUP_EN BIT(0)
+#define RKPM_CPU1_WKUP_EN BIT(1)
+#define RKPM_CPU2_WKUP_EN BIT(2)
+#define RKPM_CPU3_WKUP_EN BIT(3)
+#define RKPM_CPU4_WKUP_EN BIT(4)
+#define RKPM_CPU5_WKUP_EN BIT(5)
+#define RKPM_CPU6_WKUP_EN BIT(6)
+#define RKPM_CPU7_WKUP_EN BIT(7)
+#define RKPM_GPIO_WKUP_EN BIT(8)
+#define RKPM_SDMMC_WKUP_EN BIT(9)
+#define RKPM_SDIO_WKUP_EN BIT(10)
+#define RKPM_USB_WKUP_EN BIT(11)
+#define RKPM_UART0_WKUP_EN BIT(12)
+#define RKPM_VAD_WKUP_EN BIT(13)
+#define RKPM_TIMER_WKUP_EN BIT(14)
+#define RKPM_SYSINT_WKUP_EN BIT(15)
+#define RKPM_TIME_OUT_WKUP_EN BIT(16)
+#define RKPM_PMUMCU_CEC_WKUP_EN BIT(20)
+#define RKPM_PMUMCU_VAD_WKUP_EN BIT(21)
+
+/* io retention config */
+#define RKPM_EMMCIO_RET_EN BIT(0)
+#define RKPM_VCCIO1_RET_EN BIT(1)
+#define RKPM_VCCIO2_RET_EN BIT(2)
+#define RKPM_VCCIO3_RET_EN BIT(3)
+#define RKPM_VCCIO4_RET_EN BIT(4)
+#define RKPM_VCCIO5_RET_EN BIT(5)
+#define RKPM_VCCIO6_RET_EN BIT(6)
+#define RKPM_PMUIO2_RET_EN BIT(7)
+#endif
Index: v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rv1126.h
===================================================================
--- v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rv1126.h (nonexistent)
+++ v6.x/create-6.3.10-orange-pi5-patch/linux-6.3.10-new/include/dt-bindings/suspend/rockchip-rv1126.h (revision 151)
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2020, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ */
+
+#ifndef __DT_BINDINGS_RV1126_PM_H__
+#define __DT_BINDINGS_RV1126_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_ARMPD BIT(0)
+#define RKPM_SLP_ARMOFF BIT(1)
+#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
+
+/* all plls except ddr's pll*/
+#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
+
+#define RKPM_SLP_CLK_GT BIT(16)
+#define RKPM_SLP_PMIC_LP BIT(17)
+
+#define RKPM_SLP_32K_EXT BIT(24)
+#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
+#define RKPM_SLP_PMU_DBG BIT(26)
+
+/* the wake up source */
+#define RKPM_CPU0_WKUP_EN BIT(0)
+#define RKPM_CPU1_WKUP_EN BIT(1)
+#define RKPM_CPU2_WKUP_EN BIT(2)
+#define RKPM_CPU3_WKUP_EN BIT(3)
+#define RKPM_GPIO_WKUP_EN BIT(4)
+#define RKPM_SDMMC_WKUP_EN BIT(5)
+#define RKPM_SDIO_WKUP_EN BIT(6)
+#define RKPM_USB_WKUP_EN BIT(7)
+#define RKPM_UART1_WKUP_EN BIT(8)
+#define RKPM_SYSINT_WKUP_EN BIT(9)
+#define RKPM_TIME_OUT_WKUP_EN BIT(10)
+#endif
Index: v6.x/create-6.3.10-repka-pi3-patch/create.patch.sh
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/create.patch.sh (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/create.patch.sh (revision 151)
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+VERSION=6.3.10
+
+tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
+mv linux-$VERSION linux-$VERSION-orig
+
+cp -rf ./linux-$VERSION-new ./linux-$VERSION
+
+diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-repka-pi3.patch
+
+mv linux-$VERSION-repka-pi3.patch ../patches
+
+rm -rf ./linux-$VERSION
+rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.3.10-repka-pi3-patch/create.patch.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-repka-pi3-patch/file.list
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/file.list (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/file.list (revision 151)
@@ -0,0 +1,3 @@
+linux-6.3.10/arch/arm64/boot/dts/allwinner/Makefile
+linux-6.3.10/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+linux-6.3.10/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/Makefile
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/Makefile (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/Makefile (revision 151)
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-1.0ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-1.2ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-1.4ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-1.0ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-1.2ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-1.4ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-uart-1.0ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-uart-1.2ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-uart-1.4ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.0ghz.dtsi
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.0ghz.dtsi (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.0ghz.dtsi (revision 151)
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-288000000 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-336000000 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1260000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.2ghz.dtsi
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.2ghz.dtsi (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.2ghz.dtsi (revision 151)
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-288000000 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1000000 1000000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-336000000 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1260000 1260000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-10560000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1260000 1260000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.4ghz.dtsi
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.4ghz.dtsi (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp-1.4ghz.dtsi (revision 151)
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-288000000 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1000000 1000000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-336000000 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1260000 1260000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1368000000 {
+ opp-hz = /bits/ 64 <1368000000>;
+ opp-microvolt = <1360000 1360000 1360000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi (revision 151)
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-288000000 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1000000 1000000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-336000000 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1368000000 {
+ opp-hz = /bits/ 64 <1368000000>;
+ opp-microvolt = <1360000 1360000 1360000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.0ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.0ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.0ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.0 GHz";
+ repka-pinout = "1";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "disabled"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.2ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.2ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.2ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.2 GHz";
+ repka-pinout = "1";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "disabled"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.4ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.4ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-1.4ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.4 GHz";
+ repka-pinout = "1";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "disabled"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.0ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.0ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.0ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.0 GHz";
+ repka-pinout = "2";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.2ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.2ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.2ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.2 GHz";
+ repka-pinout = "2";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.4ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.4ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-1.4ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.4 GHz";
+ repka-pinout = "2";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.0ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.0 GHz";
+ repka-pinout = "4";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.2ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.2 GHz";
+ repka-pinout = "4";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-i2c2-1.4ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.4 GHz";
+ repka-pinout = "4";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.0ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.0 GHz";
+ repka-pinout = "5";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "okay";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.2ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.2 GHz";
+ repka-pinout = "5";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "okay";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-pwm-1.4ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.4 GHz";
+ repka-pinout = "5";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "okay";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.0ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.0ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.0ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.0 GHz";
+ repka-pinout = "3";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.2ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.2ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.2ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.2ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.2 GHz";
+ repka-pinout = "3";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.4ghz.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.4ghz.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt-uart-1.4ghz.dts (revision 151)
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.4ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ repka-freq = "1.4 GHz";
+ repka-pinout = "3";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3-alt.dts (revision 151)
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "okay"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "okay";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3.dts
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3.dts (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5-repka-pi3.dts (revision 151)
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp-1.0ghz.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Repka-Pi3-H5";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ mmc0 = &mmc0;
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "rbs:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "disabled"; /* PA19,PA18 */
+};
+
+&i2c0 {
+ status = "disabled"; /* PA11, PA12 */
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "arm/axp22x.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_aldo2 { /* VCC-PG 1.8 */
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pg";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-phy";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-a";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-cpux-b";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+/*
+ * The DRAM chips used by rbs-h5 boards are DDR3 -compatibl
+ *
+ */
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+};
+
+®_dldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-3";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-4";
+};
+ /* VCC-wifi-IO 1.8 */
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-1";
+};
+
+®_eldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-2";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-3";
+};
+
+/*
+ *
+ *
+ * ^__________^
+*
+*
+*/
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&spi0 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&spi0_cs1>;
+ cs-gpios = <0>, <&pio 0 3 0>; /* PA3 */
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ spidev@1 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default", "default";
+
+ status = "disabled";
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ status = "okay";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&pio {
+ spi0_cs1: spi0_cs1 {
+ pins = "PA3";
+ function = "gpio_out";
+ output-high;
+ };
+};
+
+
+&r_pwm {
+ status = "disabled";
+};
+
+/* to debag serial */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+/* to bt-wifi module */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ status = "disabled";
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+
Index: v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
===================================================================
--- v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi (nonexistent)
+++ v6.x/create-6.3.10-repka-pi3-patch/linux-6.3.10-new/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi (revision 151)
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2016 ARM Ltd.
+
+#include <arm/sunxi-h3-h5.dtsi>
+
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ syscon: system-control@1c00000 {
+ compatible = "allwinner,sun50i-h5-system-control";
+ reg = <0x01c00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c1: sram@18000 {
+ compatible = "mmio-sram";
+ reg = <0x00018000 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00018000 0x1c000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun50i-h5-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x1c000>;
+ };
+ };
+ };
+
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun50i-h5-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_VE>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun50i-h5-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
+ deinterlace: deinterlace@1e00000 {
+ compatible = "allwinner,sun8i-h3-deinterlace";
+ reg = <0x01e00000 0x20000>;
+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
+ <&ccu CLK_DEINTERLACE>,
+ <&ccu CLK_DRAM_DEINTERLACE>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_DEINTERLACE>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mbus 9>;
+ interconnect-names = "dma-mem";
+ };
+
+ mali: gpu@1e80000 {
+ compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
+ reg = <0x01e80000 0x30000>;
+ /*
+ * While the datasheet lists an interrupt for the
+ * PMU, the actual silicon does not have the PMU
+ * block. Reads all return zero, and writes are
+ * ignored.
+ */
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+
+ ths: thermal-sensor@1c25000 {
+ compatible = "allwinner,sun50i-h5-ths";
+ reg = <0x01c25000 0x400>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_hot0: cpu_hot0 {
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_hot1: cpu_hot1 {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot0: cpu_very_hot0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot1: cpu_very_hot1 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot2: cpu_very_hot2 {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot3: cpu_very_hot3 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_warm_limit_cpu {
+ trip = <&cpu_warm>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT 1>;
+ };
+
+ cpu_hot_limit_cpu0 {
+ trip = <&cpu_hot0>;
+ cooling-device = <&cpu0 1 2>;
+ };
+
+ cpu_hot_limit_cpu1 {
+ trip = <&cpu_hot1>;
+ cooling-device = <&cpu0 2 3>;
+ };
+
+ cpu_very_hot_limit_cpu0 {
+ trip = <&cpu_very_hot0>;
+ cooling-device = <&cpu0 3 4>;
+ };
+
+ cpu_very_hot_limit_cpu1 {
+ trip = <&cpu_very_hot1>;
+ cooling-device = <&cpu0 4 5>;
+ };
+
+ cpu_very_hot_limit_cpu2 {
+ trip = <&cpu_very_hot2>;
+ cooling-device = <&cpu0 5 6>;
+ };
+
+ cpu_very_hot_limit_cpu3 {
+ trip = <&cpu_very_hot3>;
+ cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
+ };
+
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+ };
+ };
+};
+
+&ccu {
+ compatible = "allwinner,sun50i-h5-ccu";
+};
+
+&display_clocks {
+ compatible = "allwinner,sun50i-h5-de2-clk";
+};
+
+&mbus {
+ compatible = "allwinner,sun50i-h5-mbus";
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc";
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+};
+
+&mmc1 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc";
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+};
+
+&mmc2 {
+ compatible = "allwinner,sun50i-h5-emmc",
+ "allwinner,sun50i-a64-emmc";
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+};
+
+&pio {
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ compatible = "allwinner,sun50i-h5-pinctrl";
+};
+
+&rtc {
+ compatible = "allwinner,sun50i-h5-rtc";
+};
+
+&sid {
+ compatible = "allwinner,sun50i-h5-sid";
+};
Index: v6.x/create-6.3.10-sdhci-reset-patch/create.patch.sh
===================================================================
--- v6.x/create-6.3.10-sdhci-reset-patch/create.patch.sh (nonexistent)
+++ v6.x/create-6.3.10-sdhci-reset-patch/create.patch.sh (revision 151)
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+VERSION=6.3.10
+
+tar --files-from=file.list -xJvf ../linux-$VERSION.tar.xz
+mv linux-$VERSION linux-$VERSION-orig
+
+cp -rf ./linux-$VERSION-new ./linux-$VERSION
+
+diff --unified -Nr linux-$VERSION-orig linux-$VERSION > linux-$VERSION-sdhci-reset.patch
+
+mv linux-$VERSION-sdhci-reset.patch ../patches
+
+rm -rf ./linux-$VERSION
+rm -rf ./linux-$VERSION-orig
Property changes on: v6.x/create-6.3.10-sdhci-reset-patch/create.patch.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: v6.x/create-6.3.10-sdhci-reset-patch/file.list
===================================================================
--- v6.x/create-6.3.10-sdhci-reset-patch/file.list (nonexistent)
+++ v6.x/create-6.3.10-sdhci-reset-patch/file.list (revision 151)
@@ -0,0 +1 @@
+linux-6.3.10/drivers/mmc/host/sdhci.c
Index: v6.x/create-6.3.10-sdhci-reset-patch/linux-6.3.10-new/drivers/mmc/host/sdhci.c
===================================================================
--- v6.x/create-6.3.10-sdhci-reset-patch/linux-6.3.10-new/drivers/mmc/host/sdhci.c (nonexistent)
+++ v6.x/create-6.3.10-sdhci-reset-patch/linux-6.3.10-new/drivers/mmc/host/sdhci.c (revision 151)
@@ -0,0 +1,4974 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
+ *
+ * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
+ *
+ * Thanks to the following companies for their support:
+ *
+ * - JMicron (hardware and technical support)
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/ktime.h>
+#include <linux/highmem.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include <linux/sizes.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+
+#include <linux/leds.h>
+
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/slot-gpio.h>
+
+#include "sdhci.h"
+
+#define DRIVER_NAME "sdhci"
+
+#define DBG(f, x...) \
+ pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
+
+#define SDHCI_DUMP(f, x...) \
+ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
+
+#define MAX_TUNING_LOOP 40
+
+static unsigned int debug_quirks = 0;
+static unsigned int debug_quirks2;
+
+static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
+
+static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
+
+void sdhci_dumpregs(struct sdhci_host *host)
+{
+ SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
+
+ SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
+ sdhci_readl(host, SDHCI_DMA_ADDRESS),
+ sdhci_readw(host, SDHCI_HOST_VERSION));
+ SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
+ sdhci_readw(host, SDHCI_BLOCK_SIZE),
+ sdhci_readw(host, SDHCI_BLOCK_COUNT));
+ SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
+ sdhci_readl(host, SDHCI_ARGUMENT),
+ sdhci_readw(host, SDHCI_TRANSFER_MODE));
+ SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
+ sdhci_readl(host, SDHCI_PRESENT_STATE),
+ sdhci_readb(host, SDHCI_HOST_CONTROL));
+ SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
+ sdhci_readb(host, SDHCI_POWER_CONTROL),
+ sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
+ SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
+ sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
+ sdhci_readw(host, SDHCI_CLOCK_CONTROL));
+ SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
+ sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
+ sdhci_readl(host, SDHCI_INT_STATUS));
+ SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
+ sdhci_readl(host, SDHCI_INT_ENABLE),
+ sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
+ SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
+ sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
+ sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
+ SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
+ sdhci_readl(host, SDHCI_CAPABILITIES),
+ sdhci_readl(host, SDHCI_CAPABILITIES_1));
+ SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
+ sdhci_readw(host, SDHCI_COMMAND),
+ sdhci_readl(host, SDHCI_MAX_CURRENT));
+ SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
+ sdhci_readl(host, SDHCI_RESPONSE),
+ sdhci_readl(host, SDHCI_RESPONSE + 4));
+ SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
+ sdhci_readl(host, SDHCI_RESPONSE + 8),
+ sdhci_readl(host, SDHCI_RESPONSE + 12));
+ SDHCI_DUMP("Host ctl2: 0x%08x\n",
+ sdhci_readw(host, SDHCI_HOST_CONTROL2));
+
+ if (host->flags & SDHCI_USE_ADMA) {
+ if (host->flags & SDHCI_USE_64_BIT_DMA) {
+ SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
+ sdhci_readl(host, SDHCI_ADMA_ERROR),
+ sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
+ sdhci_readl(host, SDHCI_ADMA_ADDRESS));
+ } else {
+ SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
+ sdhci_readl(host, SDHCI_ADMA_ERROR),
+ sdhci_readl(host, SDHCI_ADMA_ADDRESS));
+ }
+ }
+
+ if (host->ops->dump_vendor_regs)
+ host->ops->dump_vendor_regs(host);
+
+ SDHCI_DUMP("============================================\n");
+}
+EXPORT_SYMBOL_GPL(sdhci_dumpregs);
+
+/*****************************************************************************\
+ * *
+ * Low level functions *
+ * *
+\*****************************************************************************/
+
+static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
+{
+ u16 ctrl2;
+
+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (ctrl2 & SDHCI_CTRL_V4_MODE)
+ return;
+
+ ctrl2 |= SDHCI_CTRL_V4_MODE;
+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
+}
+
+/*
+ * This can be called before sdhci_add_host() by Vendor's host controller
+ * driver to enable v4 mode if supported.
+ */
+void sdhci_enable_v4_mode(struct sdhci_host *host)
+{
+ host->v4_mode = true;
+ sdhci_do_enable_v4_mode(host);
+}
+EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
+
+static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
+{
+ return cmd->data || cmd->flags & MMC_RSP_BUSY;
+}
+
+static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
+{
+ u32 present;
+
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
+ !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
+ return;
+
+ if (enable) {
+ present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
+ SDHCI_CARD_PRESENT;
+
+ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
+ SDHCI_INT_CARD_INSERT;
+ } else {
+ host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
+ }
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_enable_card_detection(struct sdhci_host *host)
+{
+ sdhci_set_card_detection(host, true);
+}
+
+static void sdhci_disable_card_detection(struct sdhci_host *host)
+{
+ sdhci_set_card_detection(host, false);
+}
+
+static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
+{
+ if (host->bus_on)
+ return;
+ host->bus_on = true;
+ pm_runtime_get_noresume(mmc_dev(host->mmc));
+}
+
+static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
+{
+ if (!host->bus_on)
+ return;
+ host->bus_on = false;
+ pm_runtime_put_noidle(mmc_dev(host->mmc));
+}
+
+void sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+ ktime_t timeout;
+
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+
+ if (mask & SDHCI_RESET_ALL) {
+ host->clock = 0;
+ /* Reset-all turns off SD Bus Power */
+ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
+ sdhci_runtime_pm_bus_off(host);
+ if (host->ops->voltage_switch)
+ host->ops->voltage_switch(host);
+ }
+
+ /* Wait max 100 ms */
+ timeout = ktime_add_ms(ktime_get(), 100);
+
+ /* hw clears the bit when it's done */
+ while (1) {
+ bool timedout = ktime_after(ktime_get(), timeout);
+
+ if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
+ break;
+ if (timedout) {
+ pr_err("%s: Reset 0x%x never completed.\n",
+ mmc_hostname(host->mmc), (int)mask);
+ sdhci_err_stats_inc(host, CTRL_TIMEOUT);
+ sdhci_dumpregs(host);
+ return;
+ }
+ udelay(10);
+ }
+}
+EXPORT_SYMBOL_GPL(sdhci_reset);
+
+static bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
+{
+ if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
+ struct mmc_host *mmc = host->mmc;
+
+ if (!mmc->ops->get_cd(mmc))
+ return false;
+ }
+
+ host->ops->reset(host, mask);
+
+ return true;
+}
+
+static void sdhci_reset_for_all(struct sdhci_host *host)
+{
+ if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if (host->ops->enable_dma)
+ host->ops->enable_dma(host);
+ }
+ /* Resetting the controller clears many */
+ host->preset_enabled = false;
+ }
+}
+
+enum sdhci_reset_reason {
+ SDHCI_RESET_FOR_INIT,
+ SDHCI_RESET_FOR_REQUEST_ERROR,
+ SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
+ SDHCI_RESET_FOR_TUNING_ABORT,
+ SDHCI_RESET_FOR_CARD_REMOVED,
+ SDHCI_RESET_FOR_CQE_RECOVERY,
+};
+
+static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
+{
+ if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
+ sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ return;
+ }
+
+ switch (reason) {
+ case SDHCI_RESET_FOR_INIT:
+ sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ break;
+ case SDHCI_RESET_FOR_REQUEST_ERROR:
+ case SDHCI_RESET_FOR_TUNING_ABORT:
+ case SDHCI_RESET_FOR_CARD_REMOVED:
+ case SDHCI_RESET_FOR_CQE_RECOVERY:
+ sdhci_do_reset(host, SDHCI_RESET_CMD);
+ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ break;
+ case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
+ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ break;
+ }
+}
+
+#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
+
+static void sdhci_set_default_irqs(struct sdhci_host *host)
+{
+ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
+ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
+ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
+ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
+ SDHCI_INT_RESPONSE;
+
+ if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
+ host->tuning_mode == SDHCI_TUNING_MODE_3)
+ host->ier |= SDHCI_INT_RETUNE;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_config_dma(struct sdhci_host *host)
+{
+ u8 ctrl;
+ u16 ctrl2;
+
+ if (host->version < SDHCI_SPEC_200)
+ return;
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+
+ /*
+ * Always adjust the DMA selection as some controllers
+ * (e.g. JMicron) can't do PIO properly when the selection
+ * is ADMA.
+ */
+ ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ if (!(host->flags & SDHCI_REQ_USE_DMA))
+ goto out;
+
+ /* Note if DMA Select is zero then SDMA is selected */
+ if (host->flags & SDHCI_USE_ADMA)
+ ctrl |= SDHCI_CTRL_ADMA32;
+
+ if (host->flags & SDHCI_USE_64_BIT_DMA) {
+ /*
+ * If v4 mode, all supported DMA can be 64-bit addressing if
+ * controller supports 64-bit system address, otherwise only
+ * ADMA can support 64-bit addressing.
+ */
+ if (host->v4_mode) {
+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
+ } else if (host->flags & SDHCI_USE_ADMA) {
+ /*
+ * Don't need to undo SDHCI_CTRL_ADMA32 in order to
+ * set SDHCI_CTRL_ADMA64.
+ */
+ ctrl |= SDHCI_CTRL_ADMA64;
+ }
+ }
+
+out:
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
+static void sdhci_init(struct sdhci_host *host, int soft)
+{
+ struct mmc_host *mmc = host->mmc;
+ unsigned long flags;
+
+ if (soft)
+ sdhci_reset_for(host, INIT);
+ else
+ sdhci_reset_for_all(host);
+
+ if (host->v4_mode)
+ sdhci_do_enable_v4_mode(host);
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_set_default_irqs(host);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ host->cqe_on = false;
+
+ if (soft) {
+ /* force clock reconfiguration */
+ host->clock = 0;
+ host->reinit_uhs = true;
+ mmc->ops->set_ios(mmc, &mmc->ios);
+ }
+}
+
+static void sdhci_reinit(struct sdhci_host *host)
+{
+ u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
+
+ sdhci_init(host, 0);
+ sdhci_enable_card_detection(host);
+
+ /*
+ * A change to the card detect bits indicates a change in present state,
+ * refer sdhci_set_card_detection(). A card detect interrupt might have
+ * been missed while the host controller was being reset, so trigger a
+ * rescan to check.
+ */
+ if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
+ mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+}
+
+static void __sdhci_led_activate(struct sdhci_host *host)
+{
+ u8 ctrl;
+
+ if (host->quirks & SDHCI_QUIRK_NO_LED)
+ return;
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl |= SDHCI_CTRL_LED;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
+static void __sdhci_led_deactivate(struct sdhci_host *host)
+{
+ u8 ctrl;
+
+ if (host->quirks & SDHCI_QUIRK_NO_LED)
+ return;
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl &= ~SDHCI_CTRL_LED;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
+#if IS_REACHABLE(CONFIG_LEDS_CLASS)
+static void sdhci_led_control(struct led_classdev *led,
+ enum led_brightness brightness)
+{
+ struct sdhci_host *host = container_of(led, struct sdhci_host, led);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (host->runtime_suspended)
+ goto out;
+
+ if (brightness == LED_OFF)
+ __sdhci_led_deactivate(host);
+ else
+ __sdhci_led_activate(host);
+out:
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static int sdhci_led_register(struct sdhci_host *host)
+{
+ struct mmc_host *mmc = host->mmc;
+
+ if (host->quirks & SDHCI_QUIRK_NO_LED)
+ return 0;
+
+ snprintf(host->led_name, sizeof(host->led_name),
+ "%s::", mmc_hostname(mmc));
+
+ host->led.name = host->led_name;
+ host->led.brightness = LED_OFF;
+ host->led.default_trigger = mmc_hostname(mmc);
+ host->led.brightness_set = sdhci_led_control;
+
+ return led_classdev_register(mmc_dev(mmc), &host->led);
+}
+
+static void sdhci_led_unregister(struct sdhci_host *host)
+{
+ if (host->quirks & SDHCI_QUIRK_NO_LED)
+ return;
+
+ led_classdev_unregister(&host->led);
+}
+
+static inline void sdhci_led_activate(struct sdhci_host *host)
+{
+}
+
+static inline void sdhci_led_deactivate(struct sdhci_host *host)
+{
+}
+
+#else
+
+static inline int sdhci_led_register(struct sdhci_host *host)
+{
+ return 0;
+}
+
+static inline void sdhci_led_unregister(struct sdhci_host *host)
+{
+}
+
+static inline void sdhci_led_activate(struct sdhci_host *host)
+{
+ __sdhci_led_activate(host);
+}
+
+static inline void sdhci_led_deactivate(struct sdhci_host *host)
+{
+ __sdhci_led_deactivate(host);
+}
+
+#endif
+
+static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
+ unsigned long timeout)
+{
+ if (sdhci_data_line_cmd(mrq->cmd))
+ mod_timer(&host->data_timer, timeout);
+ else
+ mod_timer(&host->timer, timeout);
+}
+
+static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
+{
+ if (sdhci_data_line_cmd(mrq->cmd))
+ del_timer(&host->data_timer);
+ else
+ del_timer(&host->timer);
+}
+
+static inline bool sdhci_has_requests(struct sdhci_host *host)
+{
+ return host->cmd || host->data_cmd;
+}
+
+/*****************************************************************************\
+ * *
+ * Core functions *
+ * *
+\*****************************************************************************/
+
+static void sdhci_read_block_pio(struct sdhci_host *host)
+{
+ size_t blksize, len, chunk;
+ u32 scratch;
+ u8 *buf;
+
+ DBG("PIO reading\n");
+
+ blksize = host->data->blksz;
+ chunk = 0;
+
+ while (blksize) {
+ BUG_ON(!sg_miter_next(&host->sg_miter));
+
+ len = min(host->sg_miter.length, blksize);
+
+ blksize -= len;
+ host->sg_miter.consumed = len;
+
+ buf = host->sg_miter.addr;
+
+ while (len) {
+ if (chunk == 0) {
+ scratch = sdhci_readl(host, SDHCI_BUFFER);
+ chunk = 4;
+ }
+
+ *buf = scratch & 0xFF;
+
+ buf++;
+ scratch >>= 8;
+ chunk--;
+ len--;
+ }
+ }
+
+ sg_miter_stop(&host->sg_miter);
+}
+
+static void sdhci_write_block_pio(struct sdhci_host *host)
+{
+ size_t blksize, len, chunk;
+ u32 scratch;
+ u8 *buf;
+
+ DBG("PIO writing\n");
+
+ blksize = host->data->blksz;
+ chunk = 0;
+ scratch = 0;
+
+ while (blksize) {
+ BUG_ON(!sg_miter_next(&host->sg_miter));
+
+ len = min(host->sg_miter.length, blksize);
+
+ blksize -= len;
+ host->sg_miter.consumed = len;
+
+ buf = host->sg_miter.addr;
+
+ while (len) {
+ scratch |= (u32)*buf << (chunk * 8);
+
+ buf++;
+ chunk++;
+ len--;
+
+ if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
+ sdhci_writel(host, scratch, SDHCI_BUFFER);
+ chunk = 0;
+ scratch = 0;
+ }
+ }
+ }
+
+ sg_miter_stop(&host->sg_miter);
+}
+
+static void sdhci_transfer_pio(struct sdhci_host *host)
+{
+ u32 mask;
+
+ if (host->blocks == 0)
+ return;
+
+ if (host->data->flags & MMC_DATA_READ)
+ mask = SDHCI_DATA_AVAILABLE;
+ else
+ mask = SDHCI_SPACE_AVAILABLE;
+
+ /*
+ * Some controllers (JMicron JMB38x) mess up the buffer bits
+ * for transfers < 4 bytes. As long as it is just one block,
+ * we can ignore the bits.
+ */
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
+ (host->data->blocks == 1))
+ mask = ~0;
+
+ while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
+ if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
+ udelay(100);
+
+ if (host->data->flags & MMC_DATA_READ)
+ sdhci_read_block_pio(host);
+ else
+ sdhci_write_block_pio(host);
+
+ host->blocks--;
+ if (host->blocks == 0)
+ break;
+ }
+
+ DBG("PIO transfer complete.\n");
+}
+
+static int sdhci_pre_dma_transfer(struct sdhci_host *host,
+ struct mmc_data *data, int cookie)
+{
+ int sg_count;
+
+ /*
+ * If the data buffers are already mapped, return the previous
+ * dma_map_sg() result.
+ */
+ if (data->host_cookie == COOKIE_PRE_MAPPED)
+ return data->sg_count;
+
+ /* Bounce write requests to the bounce buffer */
+ if (host->bounce_buffer) {
+ unsigned int length = data->blksz * data->blocks;
+
+ if (length > host->bounce_buffer_size) {
+ pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
+ mmc_hostname(host->mmc), length,
+ host->bounce_buffer_size);
+ return -EIO;
+ }
+ if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
+ /* Copy the data to the bounce buffer */
+ if (host->ops->copy_to_bounce_buffer) {
+ host->ops->copy_to_bounce_buffer(host,
+ data, length);
+ } else {
+ sg_copy_to_buffer(data->sg, data->sg_len,
+ host->bounce_buffer, length);
+ }
+ }
+ /* Switch ownership to the DMA */
+ dma_sync_single_for_device(mmc_dev(host->mmc),
+ host->bounce_addr,
+ host->bounce_buffer_size,
+ mmc_get_dma_dir(data));
+ /* Just a dummy value */
+ sg_count = 1;
+ } else {
+ /* Just access the data directly from memory */
+ sg_count = dma_map_sg(mmc_dev(host->mmc),
+ data->sg, data->sg_len,
+ mmc_get_dma_dir(data));
+ }
+
+ if (sg_count == 0)
+ return -ENOSPC;
+
+ data->sg_count = sg_count;
+ data->host_cookie = cookie;
+
+ return sg_count;
+}
+
+static char *sdhci_kmap_atomic(struct scatterlist *sg)
+{
+ return kmap_local_page(sg_page(sg)) + sg->offset;
+}
+
+static void sdhci_kunmap_atomic(void *buffer)
+{
+ kunmap_local(buffer);
+}
+
+void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
+ dma_addr_t addr, int len, unsigned int cmd)
+{
+ struct sdhci_adma2_64_desc *dma_desc = *desc;
+
+ /* 32-bit and 64-bit descriptors have these members in same position */
+ dma_desc->cmd = cpu_to_le16(cmd);
+ dma_desc->len = cpu_to_le16(len);
+ dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
+
+ if (host->flags & SDHCI_USE_64_BIT_DMA)
+ dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
+
+ *desc += host->desc_sz;
+}
+EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
+
+static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
+ void **desc, dma_addr_t addr,
+ int len, unsigned int cmd)
+{
+ if (host->ops->adma_write_desc)
+ host->ops->adma_write_desc(host, desc, addr, len, cmd);
+ else
+ sdhci_adma_write_desc(host, desc, addr, len, cmd);
+}
+
+static void sdhci_adma_mark_end(void *desc)
+{
+ struct sdhci_adma2_64_desc *dma_desc = desc;
+
+ /* 32-bit and 64-bit descriptors have 'cmd' in same position */
+ dma_desc->cmd |= cpu_to_le16(ADMA2_END);
+}
+
+static void sdhci_adma_table_pre(struct sdhci_host *host,
+ struct mmc_data *data, int sg_count)
+{
+ struct scatterlist *sg;
+ dma_addr_t addr, align_addr;
+ void *desc, *align;
+ char *buffer;
+ int len, offset, i;
+
+ /*
+ * The spec does not specify endianness of descriptor table.
+ * We currently guess that it is LE.
+ */
+
+ host->sg_count = sg_count;
+
+ desc = host->adma_table;
+ align = host->align_buffer;
+
+ align_addr = host->align_addr;
+
+ for_each_sg(data->sg, sg, host->sg_count, i) {
+ addr = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ /*
+ * The SDHCI specification states that ADMA addresses must
+ * be 32-bit aligned. If they aren't, then we use a bounce
+ * buffer for the (up to three) bytes that screw up the
+ * alignment.
+ */
+ offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
+ SDHCI_ADMA2_MASK;
+ if (offset) {
+ if (data->flags & MMC_DATA_WRITE) {
+ buffer = sdhci_kmap_atomic(sg);
+ memcpy(align, buffer, offset);
+ sdhci_kunmap_atomic(buffer);
+ }
+
+ /* tran, valid */
+ __sdhci_adma_write_desc(host, &desc, align_addr,
+ offset, ADMA2_TRAN_VALID);
+
+ BUG_ON(offset > 65536);
+
+ align += SDHCI_ADMA2_ALIGN;
+ align_addr += SDHCI_ADMA2_ALIGN;
+
+ addr += offset;
+ len -= offset;
+ }
+
+ /*
+ * The block layer forces a minimum segment size of PAGE_SIZE,
+ * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
+ * multiple descriptors, noting that the ADMA table is sized
+ * for 4KiB chunks anyway, so it will be big enough.
+ */
+ while (len > host->max_adma) {
+ int n = 32 * 1024; /* 32KiB*/
+
+ __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
+ addr += n;
+ len -= n;
+ }
+
+ /* tran, valid */
+ if (len)
+ __sdhci_adma_write_desc(host, &desc, addr, len,
+ ADMA2_TRAN_VALID);
+
+ /*
+ * If this triggers then we have a calculation bug
+ * somewhere. :/
+ */
+ WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
+ }
+
+ if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
+ /* Mark the last descriptor as the terminating descriptor */
+ if (desc != host->adma_table) {
+ desc -= host->desc_sz;
+ sdhci_adma_mark_end(desc);
+ }
+ } else {
+ /* Add a terminating entry - nop, end, valid */
+ __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
+ }
+}
+
+static void sdhci_adma_table_post(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ struct scatterlist *sg;
+ int i, size;
+ void *align;
+ char *buffer;
+
+ if (data->flags & MMC_DATA_READ) {
+ bool has_unaligned = false;
+
+ /* Do a quick scan of the SG list for any unaligned mappings */
+ for_each_sg(data->sg, sg, host->sg_count, i)
+ if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
+ has_unaligned = true;
+ break;
+ }
+
+ if (has_unaligned) {
+ dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
+ data->sg_len, DMA_FROM_DEVICE);
+
+ align = host->align_buffer;
+
+ for_each_sg(data->sg, sg, host->sg_count, i) {
+ if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
+ size = SDHCI_ADMA2_ALIGN -
+ (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
+
+ buffer = sdhci_kmap_atomic(sg);
+ memcpy(buffer, align, size);
+ sdhci_kunmap_atomic(buffer);
+
+ align += SDHCI_ADMA2_ALIGN;
+ }
+ }
+ }
+ }
+}
+
+static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
+{
+ sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
+ if (host->flags & SDHCI_USE_64_BIT_DMA)
+ sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
+}
+
+static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
+{
+ if (host->bounce_buffer)
+ return host->bounce_addr;
+ else
+ return sg_dma_address(host->data->sg);
+}
+
+static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
+{
+ if (host->v4_mode)
+ sdhci_set_adma_addr(host, addr);
+ else
+ sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
+}
+
+static unsigned int sdhci_target_timeout(struct sdhci_host *host,
+ struct mmc_command *cmd,
+ struct mmc_data *data)
+{
+ unsigned int target_timeout;
+
+ /* timeout in us */
+ if (!data) {
+ target_timeout = cmd->busy_timeout * 1000;
+ } else {
+ target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
+ if (host->clock && data->timeout_clks) {
+ unsigned long long val;
+
+ /*
+ * data->timeout_clks is in units of clock cycles.
+ * host->clock is in Hz. target_timeout is in us.
+ * Hence, us = 1000000 * cycles / Hz. Round up.
+ */
+ val = 1000000ULL * data->timeout_clks;
+ if (do_div(val, host->clock))
+ target_timeout++;
+ target_timeout += val;
+ }
+ }
+
+ return target_timeout;
+}
+
+static void sdhci_calc_sw_timeout(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ struct mmc_data *data = cmd->data;
+ struct mmc_host *mmc = host->mmc;
+ struct mmc_ios *ios = &mmc->ios;
+ unsigned char bus_width = 1 << ios->bus_width;
+ unsigned int blksz;
+ unsigned int freq;
+ u64 target_timeout;
+ u64 transfer_time;
+
+ target_timeout = sdhci_target_timeout(host, cmd, data);
+ target_timeout *= NSEC_PER_USEC;
+
+ if (data) {
+ blksz = data->blksz;
+ freq = mmc->actual_clock ? : host->clock;
+ transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
+ do_div(transfer_time, freq);
+ /* multiply by '2' to account for any unknowns */
+ transfer_time = transfer_time * 2;
+ /* calculate timeout for the entire data */
+ host->data_timeout = data->blocks * target_timeout +
+ transfer_time;
+ } else {
+ host->data_timeout = target_timeout;
+ }
+
+ if (host->data_timeout)
+ host->data_timeout += MMC_CMD_TRANSFER_TIME;
+}
+
+static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
+ bool *too_big)
+{
+ u8 count;
+ struct mmc_data *data;
+ unsigned target_timeout, current_timeout;
+
+ *too_big = false;
+
+ /*
+ * If the host controller provides us with an incorrect timeout
+ * value, just skip the check and use the maximum. The hardware may take
+ * longer to time out, but that's much better than having a too-short
+ * timeout value.
+ */
+ if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
+ return host->max_timeout_count;
+
+ /* Unspecified command, assume max */
+ if (cmd == NULL)
+ return host->max_timeout_count;
+
+ data = cmd->data;
+ /* Unspecified timeout, assume max */
+ if (!data && !cmd->busy_timeout)
+ return host->max_timeout_count;
+
+ /* timeout in us */
+ target_timeout = sdhci_target_timeout(host, cmd, data);
+
+ /*
+ * Figure out needed cycles.
+ * We do this in steps in order to fit inside a 32 bit int.
+ * The first step is the minimum timeout, which will have a
+ * minimum resolution of 6 bits:
+ * (1) 2^13*1000 > 2^22,
+ * (2) host->timeout_clk < 2^16
+ * =>
+ * (1) / (2) > 2^6
+ */
+ count = 0;
+ current_timeout = (1 << 13) * 1000 / host->timeout_clk;
+ while (current_timeout < target_timeout) {
+ count++;
+ current_timeout <<= 1;
+ if (count > host->max_timeout_count) {
+ if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
+ DBG("Too large timeout 0x%x requested for CMD%d!\n",
+ count, cmd->opcode);
+ count = host->max_timeout_count;
+ *too_big = true;
+ break;
+ }
+ }
+
+ return count;
+}
+
+static void sdhci_set_transfer_irqs(struct sdhci_host *host)
+{
+ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
+
+ if (host->flags & SDHCI_REQ_USE_DMA)
+ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
+ else
+ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
+
+ if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
+ host->ier |= SDHCI_INT_AUTO_CMD_ERR;
+ else
+ host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+}
+
+void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
+{
+ if (enable)
+ host->ier |= SDHCI_INT_DATA_TIMEOUT;
+ else
+ host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
+
+void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
+{
+ bool too_big = false;
+ u8 count = sdhci_calc_timeout(host, cmd, &too_big);
+
+ if (too_big &&
+ host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
+ sdhci_calc_sw_timeout(host, cmd);
+ sdhci_set_data_timeout_irq(host, false);
+ } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
+ sdhci_set_data_timeout_irq(host, true);
+ }
+
+ sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
+}
+EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
+
+static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
+{
+ if (host->ops->set_timeout)
+ host->ops->set_timeout(host, cmd);
+ else
+ __sdhci_set_timeout(host, cmd);
+}
+
+static void sdhci_initialize_data(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ WARN_ON(host->data);
+
+ /* Sanity checks */
+ BUG_ON(data->blksz * data->blocks > 524288);
+ BUG_ON(data->blksz > host->mmc->max_blk_size);
+ BUG_ON(data->blocks > 65535);
+
+ host->data = data;
+ host->data_early = 0;
+ host->data->bytes_xfered = 0;
+}
+
+static inline void sdhci_set_block_info(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ /* Set the DMA boundary value and block size */
+ sdhci_writew(host,
+ SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
+ SDHCI_BLOCK_SIZE);
+ /*
+ * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
+ * can be supported, in that case 16-bit block count register must be 0.
+ */
+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
+ (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
+ if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
+ sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
+ } else {
+ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
+ }
+}
+
+static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
+{
+ struct mmc_data *data = cmd->data;
+
+ sdhci_initialize_data(host, data);
+
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ struct scatterlist *sg;
+ unsigned int length_mask, offset_mask;
+ int i;
+
+ host->flags |= SDHCI_REQ_USE_DMA;
+
+ /*
+ * FIXME: This doesn't account for merging when mapping the
+ * scatterlist.
+ *
+ * The assumption here being that alignment and lengths are
+ * the same after DMA mapping to device address space.
+ */
+ length_mask = 0;
+ offset_mask = 0;
+ if (host->flags & SDHCI_USE_ADMA) {
+ if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
+ length_mask = 3;
+ /*
+ * As we use up to 3 byte chunks to work
+ * around alignment problems, we need to
+ * check the offset as well.
+ */
+ offset_mask = 3;
+ }
+ } else {
+ if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
+ length_mask = 3;
+ if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
+ offset_mask = 3;
+ }
+
+ if (unlikely(length_mask | offset_mask)) {
+ for_each_sg(data->sg, sg, data->sg_len, i) {
+ if (sg->length & length_mask) {
+ DBG("Reverting to PIO because of transfer size (%d)\n",
+ sg->length);
+ host->flags &= ~SDHCI_REQ_USE_DMA;
+ break;
+ }
+ if (sg->offset & offset_mask) {
+ DBG("Reverting to PIO because of bad alignment\n");
+ host->flags &= ~SDHCI_REQ_USE_DMA;
+ break;
+ }
+ }
+ }
+ }
+
+ if (host->flags & SDHCI_REQ_USE_DMA) {
+ int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
+
+ if (sg_cnt <= 0) {
+ /*
+ * This only happens when someone fed
+ * us an invalid request.
+ */
+ WARN_ON(1);
+ host->flags &= ~SDHCI_REQ_USE_DMA;
+ } else if (host->flags & SDHCI_USE_ADMA) {
+ sdhci_adma_table_pre(host, data, sg_cnt);
+ sdhci_set_adma_addr(host, host->adma_addr);
+ } else {
+ WARN_ON(sg_cnt != 1);
+ sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
+ }
+ }
+
+ sdhci_config_dma(host);
+
+ if (!(host->flags & SDHCI_REQ_USE_DMA)) {
+ int flags;
+
+ flags = SG_MITER_ATOMIC;
+ if (host->data->flags & MMC_DATA_READ)
+ flags |= SG_MITER_TO_SG;
+ else
+ flags |= SG_MITER_FROM_SG;
+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
+ host->blocks = data->blocks;
+ }
+
+ sdhci_set_transfer_irqs(host);
+
+ sdhci_set_block_info(host, data);
+}
+
+#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
+
+static int sdhci_external_dma_init(struct sdhci_host *host)
+{
+ int ret = 0;
+ struct mmc_host *mmc = host->mmc;
+
+ host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
+ if (IS_ERR(host->tx_chan)) {
+ ret = PTR_ERR(host->tx_chan);
+ if (ret != -EPROBE_DEFER)
+ pr_warn("Failed to request TX DMA channel.\n");
+ host->tx_chan = NULL;
+ return ret;
+ }
+
+ host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
+ if (IS_ERR(host->rx_chan)) {
+ if (host->tx_chan) {
+ dma_release_channel(host->tx_chan);
+ host->tx_chan = NULL;
+ }
+
+ ret = PTR_ERR(host->rx_chan);
+ if (ret != -EPROBE_DEFER)
+ pr_warn("Failed to request RX DMA channel.\n");
+ host->rx_chan = NULL;
+ }
+
+ return ret;
+}
+
+static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
+}
+
+static int sdhci_external_dma_setup(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ int ret, i;
+ enum dma_transfer_direction dir;
+ struct dma_async_tx_descriptor *desc;
+ struct mmc_data *data = cmd->data;
+ struct dma_chan *chan;
+ struct dma_slave_config cfg;
+ dma_cookie_t cookie;
+ int sg_cnt;
+
+ if (!host->mapbase)
+ return -EINVAL;
+
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.src_addr = host->mapbase + SDHCI_BUFFER;
+ cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ cfg.src_maxburst = data->blksz / 4;
+ cfg.dst_maxburst = data->blksz / 4;
+
+ /* Sanity check: all the SG entries must be aligned by block size. */
+ for (i = 0; i < data->sg_len; i++) {
+ if ((data->sg + i)->length % data->blksz)
+ return -EINVAL;
+ }
+
+ chan = sdhci_external_dma_channel(host, data);
+
+ ret = dmaengine_slave_config(chan, &cfg);
+ if (ret)
+ return ret;
+
+ sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
+ if (sg_cnt <= 0)
+ return -EINVAL;
+
+ dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
+ desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!desc)
+ return -EINVAL;
+
+ desc->callback = NULL;
+ desc->callback_param = NULL;
+
+ cookie = dmaengine_submit(desc);
+ if (dma_submit_error(cookie))
+ ret = cookie;
+
+ return ret;
+}
+
+static void sdhci_external_dma_release(struct sdhci_host *host)
+{
+ if (host->tx_chan) {
+ dma_release_channel(host->tx_chan);
+ host->tx_chan = NULL;
+ }
+
+ if (host->rx_chan) {
+ dma_release_channel(host->rx_chan);
+ host->rx_chan = NULL;
+ }
+
+ sdhci_switch_external_dma(host, false);
+}
+
+static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ struct mmc_data *data = cmd->data;
+
+ sdhci_initialize_data(host, data);
+
+ host->flags |= SDHCI_REQ_USE_DMA;
+ sdhci_set_transfer_irqs(host);
+
+ sdhci_set_block_info(host, data);
+}
+
+static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ if (!sdhci_external_dma_setup(host, cmd)) {
+ __sdhci_external_dma_prepare_data(host, cmd);
+ } else {
+ sdhci_external_dma_release(host);
+ pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
+ mmc_hostname(host->mmc));
+ sdhci_prepare_data(host, cmd);
+ }
+}
+
+static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ struct dma_chan *chan;
+
+ if (!cmd->data)
+ return;
+
+ chan = sdhci_external_dma_channel(host, cmd->data);
+ if (chan)
+ dma_async_issue_pending(chan);
+}
+
+#else
+
+static inline int sdhci_external_dma_init(struct sdhci_host *host)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void sdhci_external_dma_release(struct sdhci_host *host)
+{
+}
+
+static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ /* This should never happen */
+ WARN_ON_ONCE(1);
+}
+
+static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+}
+
+static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ return NULL;
+}
+
+#endif
+
+void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
+{
+ host->use_external_dma = en;
+}
+EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
+
+static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
+ struct mmc_request *mrq)
+{
+ return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
+ !mrq->cap_cmd_during_tfr;
+}
+
+static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
+ struct mmc_request *mrq)
+{
+ return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
+}
+
+static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
+ struct mmc_request *mrq)
+{
+ return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
+}
+
+static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
+ struct mmc_command *cmd,
+ u16 *mode)
+{
+ bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
+ (cmd->opcode != SD_IO_RW_EXTENDED);
+ bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
+ u16 ctrl2;
+
+ /*
+ * In case of Version 4.10 or later, use of 'Auto CMD Auto
+ * Select' is recommended rather than use of 'Auto CMD12
+ * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
+ * here because some controllers (e.g sdhci-of-dwmshc) expect it.
+ */
+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
+ (use_cmd12 || use_cmd23)) {
+ *mode |= SDHCI_TRNS_AUTO_SEL;
+
+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (use_cmd23)
+ ctrl2 |= SDHCI_CMD23_ENABLE;
+ else
+ ctrl2 &= ~SDHCI_CMD23_ENABLE;
+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
+
+ return;
+ }
+
+ /*
+ * If we are sending CMD23, CMD12 never gets sent
+ * on successful completion (so no Auto-CMD12).
+ */
+ if (use_cmd12)
+ *mode |= SDHCI_TRNS_AUTO_CMD12;
+ else if (use_cmd23)
+ *mode |= SDHCI_TRNS_AUTO_CMD23;
+}
+
+static void sdhci_set_transfer_mode(struct sdhci_host *host,
+ struct mmc_command *cmd)
+{
+ u16 mode = 0;
+ struct mmc_data *data = cmd->data;
+
+ if (data == NULL) {
+ if (host->quirks2 &
+ SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
+ /* must not clear SDHCI_TRANSFER_MODE when tuning */
+ if (!mmc_op_tuning(cmd->opcode))
+ sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
+ } else {
+ /* clear Auto CMD settings for no data CMDs */
+ mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
+ sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
+ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
+ }
+ return;
+ }
+
+ WARN_ON(!host->data);
+
+ if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
+ mode = SDHCI_TRNS_BLK_CNT_EN;
+
+ if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
+ mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
+ sdhci_auto_cmd_select(host, cmd, &mode);
+ if (sdhci_auto_cmd23(host, cmd->mrq))
+ sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
+ }
+
+ if (data->flags & MMC_DATA_READ)
+ mode |= SDHCI_TRNS_READ;
+ if (host->flags & SDHCI_REQ_USE_DMA)
+ mode |= SDHCI_TRNS_DMA;
+
+ sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
+}
+
+static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
+{
+ return (!(host->flags & SDHCI_DEVICE_DEAD) &&
+ ((mrq->cmd && mrq->cmd->error) ||
+ (mrq->sbc && mrq->sbc->error) ||
+ (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
+ (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
+}
+
+static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
+{
+ int i;
+
+ for (i = 0; i < SDHCI_MAX_MRQS; i++) {
+ if (host->mrqs_done[i] == mrq) {
+ WARN_ON(1);
+ return;
+ }
+ }
+
+ for (i = 0; i < SDHCI_MAX_MRQS; i++) {
+ if (!host->mrqs_done[i]) {
+ host->mrqs_done[i] = mrq;
+ break;
+ }
+ }
+
+ WARN_ON(i >= SDHCI_MAX_MRQS);
+}
+
+static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
+{
+ if (host->cmd && host->cmd->mrq == mrq)
+ host->cmd = NULL;
+
+ if (host->data_cmd && host->data_cmd->mrq == mrq)
+ host->data_cmd = NULL;
+
+ if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
+ host->deferred_cmd = NULL;
+
+ if (host->data && host->data->mrq == mrq)
+ host->data = NULL;
+
+ if (sdhci_needs_reset(host, mrq))
+ host->pending_reset = true;
+
+ sdhci_set_mrq_done(host, mrq);
+
+ sdhci_del_timer(host, mrq);
+
+ if (!sdhci_has_requests(host))
+ sdhci_led_deactivate(host);
+}
+
+static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
+{
+ __sdhci_finish_mrq(host, mrq);
+
+ queue_work(host->complete_wq, &host->complete_work);
+}
+
+static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
+{
+ struct mmc_command *data_cmd = host->data_cmd;
+ struct mmc_data *data = host->data;
+
+ host->data = NULL;
+ host->data_cmd = NULL;
+
+ /*
+ * The controller needs a reset of internal state machines upon error
+ * conditions.
+ */
+ if (data->error) {
+ if (!host->cmd || host->cmd == data_cmd)
+ sdhci_reset_for(host, REQUEST_ERROR);
+ else
+ sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
+ }
+
+ if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
+ (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
+ sdhci_adma_table_post(host, data);
+
+ /*
+ * The specification states that the block count register must
+ * be updated, but it does not specify at what point in the
+ * data flow. That makes the register entirely useless to read
+ * back so we have to assume that nothing made it to the card
+ * in the event of an error.
+ */
+ if (data->error)
+ data->bytes_xfered = 0;
+ else
+ data->bytes_xfered = data->blksz * data->blocks;
+
+ /*
+ * Need to send CMD12 if -
+ * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
+ * b) error in multiblock transfer
+ */
+ if (data->stop &&
+ ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
+ data->error)) {
+ /*
+ * 'cap_cmd_during_tfr' request must not use the command line
+ * after mmc_command_done() has been called. It is upper layer's
+ * responsibility to send the stop command if required.
+ */
+ if (data->mrq->cap_cmd_during_tfr) {
+ __sdhci_finish_mrq(host, data->mrq);
+ } else {
+ /* Avoid triggering warning in sdhci_send_command() */
+ host->cmd = NULL;
+ if (!sdhci_send_command(host, data->stop)) {
+ if (sw_data_timeout) {
+ /*
+ * This is anyway a sw data timeout, so
+ * give up now.
+ */
+ data->stop->error = -EIO;
+ __sdhci_finish_mrq(host, data->mrq);
+ } else {
+ WARN_ON(host->deferred_cmd);
+ host->deferred_cmd = data->stop;
+ }
+ }
+ }
+ } else {
+ __sdhci_finish_mrq(host, data->mrq);
+ }
+}
+
+static void sdhci_finish_data(struct sdhci_host *host)
+{
+ __sdhci_finish_data(host, false);
+}
+
+static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
+{
+ int flags;
+ u32 mask;
+ unsigned long timeout;
+
+ WARN_ON(host->cmd);
+
+ /* Initially, a command has no error */
+ cmd->error = 0;
+
+ if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
+ cmd->opcode == MMC_STOP_TRANSMISSION)
+ cmd->flags |= MMC_RSP_BUSY;
+
+ mask = SDHCI_CMD_INHIBIT;
+ if (sdhci_data_line_cmd(cmd))
+ mask |= SDHCI_DATA_INHIBIT;
+
+ /* We shouldn't wait for data inihibit for stop commands, even
+ though they might use busy signaling */
+ if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
+ mask &= ~SDHCI_DATA_INHIBIT;
+
+ if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
+ return false;
+
+ host->cmd = cmd;
+ host->data_timeout = 0;
+ if (sdhci_data_line_cmd(cmd)) {
+ WARN_ON(host->data_cmd);
+ host->data_cmd = cmd;
+ sdhci_set_timeout(host, cmd);
+ }
+
+ if (cmd->data) {
+ if (host->use_external_dma)
+ sdhci_external_dma_prepare_data(host, cmd);
+ else
+ sdhci_prepare_data(host, cmd);
+ }
+
+ sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
+
+ sdhci_set_transfer_mode(host, cmd);
+
+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
+ WARN_ONCE(1, "Unsupported response type!\n");
+ /*
+ * This does not happen in practice because 136-bit response
+ * commands never have busy waiting, so rather than complicate
+ * the error path, just remove busy waiting and continue.
+ */
+ cmd->flags &= ~MMC_RSP_BUSY;
+ }
+
+ if (!(cmd->flags & MMC_RSP_PRESENT))
+ flags = SDHCI_CMD_RESP_NONE;
+ else if (cmd->flags & MMC_RSP_136)
+ flags = SDHCI_CMD_RESP_LONG;
+ else if (cmd->flags & MMC_RSP_BUSY)
+ flags = SDHCI_CMD_RESP_SHORT_BUSY;
+ else
+ flags = SDHCI_CMD_RESP_SHORT;
+
+ if (cmd->flags & MMC_RSP_CRC)
+ flags |= SDHCI_CMD_CRC;
+ if (cmd->flags & MMC_RSP_OPCODE)
+ flags |= SDHCI_CMD_INDEX;
+
+ /* CMD19 is special in that the Data Present Select should be set */
+ if (cmd->data || mmc_op_tuning(cmd->opcode))
+ flags |= SDHCI_CMD_DATA;
+
+ timeout = jiffies;
+ if (host->data_timeout)
+ timeout += nsecs_to_jiffies(host->data_timeout);
+ else if (!cmd->data && cmd->busy_timeout > 9000)
+ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
+ else
+ timeout += 10 * HZ;
+ sdhci_mod_timer(host, cmd->mrq, timeout);
+
+ if (host->use_external_dma)
+ sdhci_external_dma_pre_transfer(host, cmd);
+
+ sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
+
+ return true;
+}
+
+static bool sdhci_present_error(struct sdhci_host *host,
+ struct mmc_command *cmd, bool present)
+{
+ if (!present || host->flags & SDHCI_DEVICE_DEAD) {
+ cmd->error = -ENOMEDIUM;
+ return true;
+ }
+
+ return false;
+}
+
+static bool sdhci_send_command_retry(struct sdhci_host *host,
+ struct mmc_command *cmd,
+ unsigned long flags)
+ __releases(host->lock)
+ __acquires(host->lock)
+{
+ struct mmc_command *deferred_cmd = host->deferred_cmd;
+ int timeout = 10; /* Approx. 10 ms */
+ bool present;
+
+ while (!sdhci_send_command(host, cmd)) {
+ if (!timeout--) {
+ pr_err("%s: Controller never released inhibit bit(s).\n",
+ mmc_hostname(host->mmc));
+ sdhci_err_stats_inc(host, CTRL_TIMEOUT);
+ sdhci_dumpregs(host);
+ cmd->error = -EIO;
+ return false;
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ usleep_range(1000, 1250);
+
+ present = host->mmc->ops->get_cd(host->mmc);
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ /* A deferred command might disappear, handle that */
+ if (cmd == deferred_cmd && cmd != host->deferred_cmd)
+ return true;
+
+ if (sdhci_present_error(host, cmd, present))
+ return false;
+ }
+
+ if (cmd == host->deferred_cmd)
+ host->deferred_cmd = NULL;
+
+ return true;
+}
+
+static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
+{
+ int i, reg;
+
+ for (i = 0; i < 4; i++) {
+ reg = SDHCI_RESPONSE + (3 - i) * 4;
+ cmd->resp[i] = sdhci_readl(host, reg);
+ }
+
+ if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
+ return;
+
+ /* CRC is stripped so we need to do some shifting */
+ for (i = 0; i < 4; i++) {
+ cmd->resp[i] <<= 8;
+ if (i != 3)
+ cmd->resp[i] |= cmd->resp[i + 1] >> 24;
+ }
+}
+
+static void sdhci_finish_command(struct sdhci_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+
+ host->cmd = NULL;
+
+ if (cmd->flags & MMC_RSP_PRESENT) {
+ if (cmd->flags & MMC_RSP_136) {
+ sdhci_read_rsp_136(host, cmd);
+ } else {
+ cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
+ }
+ }
+
+ if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
+ mmc_command_done(host->mmc, cmd->mrq);
+
+ /*
+ * The host can send and interrupt when the busy state has
+ * ended, allowing us to wait without wasting CPU cycles.
+ * The busy signal uses DAT0 so this is similar to waiting
+ * for data to complete.
+ *
+ * Note: The 1.0 specification is a bit ambiguous about this
+ * feature so there might be some problems with older
+ * controllers.
+ */
+ if (cmd->flags & MMC_RSP_BUSY) {
+ if (cmd->data) {
+ DBG("Cannot wait for busy signal when also doing a data transfer");
+ } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
+ cmd == host->data_cmd) {
+ /* Command complete before busy is ended */
+ return;
+ }
+ }
+
+ /* Finished CMD23, now send actual command. */
+ if (cmd == cmd->mrq->sbc) {
+ if (!sdhci_send_command(host, cmd->mrq->cmd)) {
+ WARN_ON(host->deferred_cmd);
+ host->deferred_cmd = cmd->mrq->cmd;
+ }
+ } else {
+
+ /* Processed actual command. */
+ if (host->data && host->data_early)
+ sdhci_finish_data(host);
+
+ if (!cmd->data)
+ __sdhci_finish_mrq(host, cmd->mrq);
+ }
+}
+
+static u16 sdhci_get_preset_value(struct sdhci_host *host)
+{
+ u16 preset = 0;
+
+ switch (host->timing) {
+ case MMC_TIMING_MMC_HS:
+ case MMC_TIMING_SD_HS:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
+ break;
+ case MMC_TIMING_UHS_SDR12:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
+ break;
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_MMC_HS200:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ case MMC_TIMING_MMC_DDR52:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
+ break;
+ case MMC_TIMING_MMC_HS400:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
+ break;
+ default:
+ pr_warn("%s: Invalid UHS-I mode selected\n",
+ mmc_hostname(host->mmc));
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
+ break;
+ }
+ return preset;
+}
+
+u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
+ unsigned int *actual_clock)
+{
+ int div = 0; /* Initialized for compiler warning */
+ int real_div = div, clk_mul = 1;
+ u16 clk = 0;
+ bool switch_base_clk = false;
+
+ if (host->version >= SDHCI_SPEC_300) {
+ if (host->preset_enabled) {
+ u16 pre_val;
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ pre_val = sdhci_get_preset_value(host);
+ div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
+ if (host->clk_mul &&
+ (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
+ clk = SDHCI_PROG_CLOCK_MODE;
+ real_div = div + 1;
+ clk_mul = host->clk_mul;
+ } else {
+ real_div = max_t(int, 1, div << 1);
+ }
+ goto clock_set;
+ }
+
+ /*
+ * Check if the Host Controller supports Programmable Clock
+ * Mode.
+ */
+ if (host->clk_mul) {
+ for (div = 1; div <= 1024; div++) {
+ if ((host->max_clk * host->clk_mul / div)
+ <= clock)
+ break;
+ }
+ if ((host->max_clk * host->clk_mul / div) <= clock) {
+ /*
+ * Set Programmable Clock Mode in the Clock
+ * Control register.
+ */
+ clk = SDHCI_PROG_CLOCK_MODE;
+ real_div = div;
+ clk_mul = host->clk_mul;
+ div--;
+ } else {
+ /*
+ * Divisor can be too small to reach clock
+ * speed requirement. Then use the base clock.
+ */
+ switch_base_clk = true;
+ }
+ }
+
+ if (!host->clk_mul || switch_base_clk) {
+ /* Version 3.00 divisors must be a multiple of 2. */
+ if (host->max_clk <= clock)
+ div = 1;
+ else {
+ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
+ div += 2) {
+ if ((host->max_clk / div) <= clock)
+ break;
+ }
+ }
+ real_div = div;
+ div >>= 1;
+ if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
+ && !div && host->max_clk <= 25000000)
+ div = 1;
+ }
+ } else {
+ /* Version 2.00 divisors must be a power of 2. */
+ for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
+ if ((host->max_clk / div) <= clock)
+ break;
+ }
+ real_div = div;
+ div >>= 1;
+ }
+
+clock_set:
+ if (real_div)
+ *actual_clock = (host->max_clk * clk_mul) / real_div;
+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
+ << SDHCI_DIVIDER_HI_SHIFT;
+
+ return clk;
+}
+EXPORT_SYMBOL_GPL(sdhci_calc_clk);
+
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
+{
+ ktime_t timeout;
+
+ clk |= SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Wait max 150 ms */
+ timeout = ktime_add_ms(ktime_get(), 150);
+ while (1) {
+ bool timedout = ktime_after(ktime_get(), timeout);
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ if (clk & SDHCI_CLOCK_INT_STABLE)
+ break;
+ if (timedout) {
+ pr_err("%s: Internal clock never stabilised.\n",
+ mmc_hostname(host->mmc));
+ sdhci_err_stats_inc(host, CTRL_TIMEOUT);
+ sdhci_dumpregs(host);
+ return;
+ }
+ udelay(10);
+ }
+
+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
+ clk |= SDHCI_CLOCK_PLL_EN;
+ clk &= ~SDHCI_CLOCK_INT_STABLE;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Wait max 150 ms */
+ timeout = ktime_add_ms(ktime_get(), 150);
+ while (1) {
+ bool timedout = ktime_after(ktime_get(), timeout);
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ if (clk & SDHCI_CLOCK_INT_STABLE)
+ break;
+ if (timedout) {
+ pr_err("%s: PLL clock never stabilised.\n",
+ mmc_hostname(host->mmc));
+ sdhci_err_stats_inc(host, CTRL_TIMEOUT);
+ sdhci_dumpregs(host);
+ return;
+ }
+ udelay(10);
+ }
+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+EXPORT_SYMBOL_GPL(sdhci_enable_clk);
+
+void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ u16 clk;
+
+ host->mmc->actual_clock = 0;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
+ sdhci_enable_clk(host, clk);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_clock);
+
+static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
+ unsigned short vdd)
+{
+ struct mmc_host *mmc = host->mmc;
+
+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
+
+ if (mode != MMC_POWER_OFF)
+ sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
+ else
+ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
+}
+
+void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
+ unsigned short vdd)
+{
+ u8 pwr = 0;
+
+ if (mode != MMC_POWER_OFF) {
+ switch (1 << vdd) {
+ case MMC_VDD_165_195:
+ /*
+ * Without a regulator, SDHCI does not support 2.0v
+ * so we only get here if the driver deliberately
+ * added the 2.0v range to ocr_avail. Map it to 1.8v
+ * for the purpose of turning on the power.
+ */
+ case MMC_VDD_20_21:
+ pwr = SDHCI_POWER_180;
+ break;
+ case MMC_VDD_29_30:
+ case MMC_VDD_30_31:
+ pwr = SDHCI_POWER_300;
+ break;
+ case MMC_VDD_32_33:
+ case MMC_VDD_33_34:
+ /*
+ * 3.4 ~ 3.6V are valid only for those platforms where it's
+ * known that the voltage range is supported by hardware.
+ */
+ case MMC_VDD_34_35:
+ case MMC_VDD_35_36:
+ pwr = SDHCI_POWER_330;
+ break;
+ default:
+ WARN(1, "%s: Invalid vdd %#x\n",
+ mmc_hostname(host->mmc), vdd);
+ break;
+ }
+ }
+
+ if (host->pwr == pwr)
+ return;
+
+ host->pwr = pwr;
+
+ if (pwr == 0) {
+ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
+ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
+ sdhci_runtime_pm_bus_off(host);
+ } else {
+ /*
+ * Spec says that we should clear the power reg before setting
+ * a new value. Some controllers don't seem to like this though.
+ */
+ if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
+ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
+
+ /*
+ * At least the Marvell CaFe chip gets confused if we set the
+ * voltage and set turn on power at the same time, so set the
+ * voltage first.
+ */
+ if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
+ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+ pwr |= SDHCI_POWER_ON;
+
+ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
+ sdhci_runtime_pm_bus_on(host);
+
+ /*
+ * Some controllers need an extra 10ms delay of 10ms before
+ * they can apply clock after applying power
+ */
+ if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
+ mdelay(10);
+ }
+}
+EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
+
+void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
+ unsigned short vdd)
+{
+ if (IS_ERR(host->mmc->supply.vmmc))
+ sdhci_set_power_noreg(host, mode, vdd);
+ else
+ sdhci_set_power_reg(host, mode, vdd);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_power);
+
+/*
+ * Some controllers need to configure a valid bus voltage on their power
+ * register regardless of whether an external regulator is taking care of power
+ * supply. This helper function takes care of it if set as the controller's
+ * sdhci_ops.set_power callback.
+ */
+void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
+ unsigned char mode,
+ unsigned short vdd)
+{
+ if (!IS_ERR(host->mmc->supply.vmmc)) {
+ struct mmc_host *mmc = host->mmc;
+
+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
+ }
+ sdhci_set_power_noreg(host, mode, vdd);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
+
+/*****************************************************************************\
+ * *
+ * MMC callbacks *
+ * *
+\*****************************************************************************/
+
+void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct mmc_command *cmd;
+ unsigned long flags;
+ bool present;
+
+ /* Firstly check card presence */
+ present = mmc->ops->get_cd(mmc);
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ sdhci_led_activate(host);
+
+ if (sdhci_present_error(host, mrq->cmd, present))
+ goto out_finish;
+
+ cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
+
+ if (!sdhci_send_command_retry(host, cmd, flags))
+ goto out_finish;
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return;
+
+out_finish:
+ sdhci_finish_mrq(host, mrq);
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+EXPORT_SYMBOL_GPL(sdhci_request);
+
+int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct mmc_command *cmd;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (sdhci_present_error(host, mrq->cmd, true)) {
+ sdhci_finish_mrq(host, mrq);
+ goto out_finish;
+ }
+
+ cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
+
+ /*
+ * The HSQ may send a command in interrupt context without polling
+ * the busy signaling, which means we should return BUSY if controller
+ * has not released inhibit bits to allow HSQ trying to send request
+ * again in non-atomic context. So we should not finish this request
+ * here.
+ */
+ if (!sdhci_send_command(host, cmd))
+ ret = -EBUSY;
+ else
+ sdhci_led_activate(host);
+
+out_finish:
+ spin_unlock_irqrestore(&host->lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_request_atomic);
+
+void sdhci_set_bus_width(struct sdhci_host *host, int width)
+{
+ u8 ctrl;
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ if (width == MMC_BUS_WIDTH_8) {
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ ctrl |= SDHCI_CTRL_8BITBUS;
+ } else {
+ if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
+ ctrl &= ~SDHCI_CTRL_8BITBUS;
+ if (width == MMC_BUS_WIDTH_4)
+ ctrl |= SDHCI_CTRL_4BITBUS;
+ else
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
+
+void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
+{
+ u16 ctrl_2;
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if ((timing == MMC_TIMING_MMC_HS200) ||
+ (timing == MMC_TIMING_UHS_SDR104))
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+ else if (timing == MMC_TIMING_UHS_SDR12)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ else if (timing == MMC_TIMING_UHS_SDR25)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ else if (timing == MMC_TIMING_UHS_SDR50)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+ else if ((timing == MMC_TIMING_UHS_DDR50) ||
+ (timing == MMC_TIMING_MMC_DDR52))
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+ else if (timing == MMC_TIMING_MMC_HS400)
+ ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
+
+static bool sdhci_timing_has_preset(unsigned char timing)
+{
+ switch (timing) {
+ case MMC_TIMING_UHS_SDR12:
+ case MMC_TIMING_UHS_SDR25:
+ case MMC_TIMING_UHS_SDR50:
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_UHS_DDR50:
+ case MMC_TIMING_MMC_DDR52:
+ return true;
+ }
+ return false;
+}
+
+static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
+{
+ return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
+ sdhci_timing_has_preset(timing);
+}
+
+static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
+{
+ /*
+ * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
+ * Frequency. Check if preset values need to be enabled, or the Driver
+ * Strength needs updating. Note, clock changes are handled separately.
+ */
+ return !host->preset_enabled &&
+ (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
+}
+
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ bool reinit_uhs = host->reinit_uhs;
+ bool turning_on_clk = false;
+ u8 ctrl;
+
+ host->reinit_uhs = false;
+
+ if (ios->power_mode == MMC_POWER_UNDEFINED)
+ return;
+
+ if (host->flags & SDHCI_DEVICE_DEAD) {
+ if (!IS_ERR(mmc->supply.vmmc) &&
+ ios->power_mode == MMC_POWER_OFF)
+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
+ return;
+ }
+
+ /*
+ * Reset the chip on each power off.
+ * Should clear out any weird states.
+ */
+ if (ios->power_mode == MMC_POWER_OFF) {
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ sdhci_reinit(host);
+ }
+
+ if (host->version >= SDHCI_SPEC_300 &&
+ (ios->power_mode == MMC_POWER_UP) &&
+ !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
+ sdhci_enable_preset_value(host, false);
+
+ if (!ios->clock || ios->clock != host->clock) {
+ turning_on_clk = ios->clock && !host->clock;
+
+ host->ops->set_clock(host, ios->clock);
+ host->clock = ios->clock;
+
+ if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
+ host->clock) {
+ host->timeout_clk = mmc->actual_clock ?
+ mmc->actual_clock / 1000 :
+ host->clock / 1000;
+ mmc->max_busy_timeout =
+ host->ops->get_max_timeout_count ?
+ host->ops->get_max_timeout_count(host) :
+ 1 << 27;
+ mmc->max_busy_timeout /= host->timeout_clk;
+ }
+ }
+
+ if (host->ops->set_power)
+ host->ops->set_power(host, ios->power_mode, ios->vdd);
+ else
+ sdhci_set_power(host, ios->power_mode, ios->vdd);
+
+ if (host->ops->platform_send_init_74_clocks)
+ host->ops->platform_send_init_74_clocks(host, ios->power_mode);
+
+ host->ops->set_bus_width(host, ios->bus_width);
+
+ /*
+ * Special case to avoid multiple clock changes during voltage
+ * switching.
+ */
+ if (!reinit_uhs &&
+ turning_on_clk &&
+ host->timing == ios->timing &&
+ host->version >= SDHCI_SPEC_300 &&
+ !sdhci_presetable_values_change(host, ios))
+ return;
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+
+ if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
+ if (ios->timing == MMC_TIMING_SD_HS ||
+ ios->timing == MMC_TIMING_MMC_HS ||
+ ios->timing == MMC_TIMING_MMC_HS400 ||
+ ios->timing == MMC_TIMING_MMC_HS200 ||
+ ios->timing == MMC_TIMING_MMC_DDR52 ||
+ ios->timing == MMC_TIMING_UHS_SDR50 ||
+ ios->timing == MMC_TIMING_UHS_SDR104 ||
+ ios->timing == MMC_TIMING_UHS_DDR50 ||
+ ios->timing == MMC_TIMING_UHS_SDR25)
+ ctrl |= SDHCI_CTRL_HISPD;
+ else
+ ctrl &= ~SDHCI_CTRL_HISPD;
+ }
+
+ if (host->version >= SDHCI_SPEC_300) {
+ u16 clk, ctrl_2;
+
+ /*
+ * According to SDHCI Spec v3.00, if the Preset Value
+ * Enable in the Host Control 2 register is set, we
+ * need to reset SD Clock Enable before changing High
+ * Speed Enable to avoid generating clock glitches.
+ */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ if (clk & SDHCI_CLOCK_CARD_EN) {
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+ }
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ if (!host->preset_enabled) {
+ /*
+ * We only need to set Driver Strength if the
+ * preset value enable is not set.
+ */
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
+ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
+ else {
+ pr_warn("%s: invalid driver type, default to driver type B\n",
+ mmc_hostname(mmc));
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
+ }
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ host->drv_type = ios->drv_type;
+ }
+
+ host->ops->set_uhs_signaling(host, ios->timing);
+ host->timing = ios->timing;
+
+ if (sdhci_preset_needed(host, ios->timing)) {
+ u16 preset;
+
+ sdhci_enable_preset_value(host, true);
+ preset = sdhci_get_preset_value(host);
+ ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
+ preset);
+ host->drv_type = ios->drv_type;
+ }
+
+ /* Re-enable SD Clock */
+ host->ops->set_clock(host, host->clock);
+ } else
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
+
+static int sdhci_get_cd(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int gpio_cd = mmc_gpio_get_cd(mmc);
+
+ if (host->flags & SDHCI_DEVICE_DEAD)
+ return 0;
+
+ /* If nonremovable, assume that the card is always present. */
+ if (!mmc_card_is_removable(mmc))
+ return 1;
+
+ /*
+ * Try slot gpio detect, if defined it take precedence
+ * over build in controller functionality
+ */
+ if (gpio_cd >= 0)
+ return !!gpio_cd;
+
+ /* If polling, assume that the card is always present. */
+ if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ return 1;
+
+ /* Host native card detect */
+ return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
+}
+
+int sdhci_get_cd_nogpio(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (host->flags & SDHCI_DEVICE_DEAD)
+ goto out;
+
+ ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
+out:
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
+
+static int sdhci_check_ro(struct sdhci_host *host)
+{
+ unsigned long flags;
+ int is_readonly;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (host->flags & SDHCI_DEVICE_DEAD)
+ is_readonly = 0;
+ else if (host->ops->get_ro)
+ is_readonly = host->ops->get_ro(host);
+ else if (mmc_can_gpio_ro(host->mmc))
+ is_readonly = mmc_gpio_get_ro(host->mmc);
+ else
+ is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
+ & SDHCI_WRITE_PROTECT);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ /* This quirk needs to be replaced by a callback-function later */
+ return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
+ !is_readonly : is_readonly;
+}
+
+#define SAMPLE_COUNT 5
+
+static int sdhci_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int i, ro_count;
+
+ if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
+ return sdhci_check_ro(host);
+
+ ro_count = 0;
+ for (i = 0; i < SAMPLE_COUNT; i++) {
+ if (sdhci_check_ro(host)) {
+ if (++ro_count > SAMPLE_COUNT / 2)
+ return 1;
+ }
+ msleep(30);
+ }
+ return 0;
+}
+
+static void sdhci_hw_reset(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ if (host->ops && host->ops->hw_reset)
+ host->ops->hw_reset(host);
+}
+
+static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
+{
+ if (!(host->flags & SDHCI_DEVICE_DEAD)) {
+ if (enable)
+ host->ier |= SDHCI_INT_CARD_INT;
+ else
+ host->ier &= ~SDHCI_INT_CARD_INT;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+}
+
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ if (enable)
+ pm_runtime_get_noresume(mmc_dev(mmc));
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_enable_sdio_irq_nolock(host, enable);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ if (!enable)
+ pm_runtime_put_noidle(mmc_dev(mmc));
+}
+EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
+
+static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_enable_sdio_irq_nolock(host, true);
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ u16 ctrl;
+ int ret;
+
+ /*
+ * Signal Voltage Switching is only applicable for Host Controllers
+ * v3.00 and above.
+ */
+ if (host->version < SDHCI_SPEC_300)
+ return 0;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ switch (ios->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ if (!(host->flags & SDHCI_SIGNALING_330))
+ return -EINVAL;
+ /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
+ ctrl &= ~SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ if (!IS_ERR(mmc->supply.vqmmc)) {
+ ret = mmc_regulator_set_vqmmc(mmc, ios);
+ if (ret < 0) {
+ pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
+ mmc_hostname(mmc));
+ return -EIO;
+ }
+ }
+ /* Wait for 5ms */
+ usleep_range(5000, 5500);
+
+ /* 3.3V regulator output should be stable within 5 ms */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (!(ctrl & SDHCI_CTRL_VDD_180))
+ return 0;
+
+ pr_warn("%s: 3.3V regulator output did not become stable\n",
+ mmc_hostname(mmc));
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_180:
+ if (!(host->flags & SDHCI_SIGNALING_180))
+ return -EINVAL;
+ if (!IS_ERR(mmc->supply.vqmmc)) {
+ ret = mmc_regulator_set_vqmmc(mmc, ios);
+ if (ret < 0) {
+ pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
+ mmc_hostname(mmc));
+ return -EIO;
+ }
+ }
+
+ /*
+ * Enable 1.8V Signal Enable in the Host Control2
+ * register
+ */
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /* Some controller need to do more when switching */
+ if (host->ops->voltage_switch)
+ host->ops->voltage_switch(host);
+
+ /* 1.8V regulator output should be stable within 5 ms */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (ctrl & SDHCI_CTRL_VDD_180)
+ return 0;
+
+ pr_warn("%s: 1.8V regulator output did not become stable\n",
+ mmc_hostname(mmc));
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_120:
+ if (!(host->flags & SDHCI_SIGNALING_120))
+ return -EINVAL;
+ if (!IS_ERR(mmc->supply.vqmmc)) {
+ ret = mmc_regulator_set_vqmmc(mmc, ios);
+ if (ret < 0) {
+ pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
+ mmc_hostname(mmc));
+ return -EIO;
+ }
+ }
+ return 0;
+ default:
+ /* No signal voltage switch required */
+ return 0;
+ }
+}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
+
+static int sdhci_card_busy(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ u32 present_state;
+
+ /* Check whether DAT[0] is 0 */
+ present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
+
+ return !(present_state & SDHCI_DATA_0_LVL_MASK);
+}
+
+static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->flags |= SDHCI_HS400_TUNING;
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return 0;
+}
+
+void sdhci_start_tuning(struct sdhci_host *host)
+{
+ u16 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
+ ctrl |= SDHCI_CTRL_TUNED_CLK;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /*
+ * As per the Host Controller spec v3.00, tuning command
+ * generates Buffer Read Ready interrupt, so enable that.
+ *
+ * Note: The spec clearly says that when tuning sequence
+ * is being performed, the controller does not generate
+ * interrupts other than Buffer Read Ready interrupt. But
+ * to make sure we don't hit a controller bug, we _only_
+ * enable Buffer Read Ready interrupt here.
+ */
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(sdhci_start_tuning);
+
+void sdhci_end_tuning(struct sdhci_host *host)
+{
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(sdhci_end_tuning);
+
+void sdhci_reset_tuning(struct sdhci_host *host)
+{
+ u16 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+}
+EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
+
+void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
+{
+ sdhci_reset_tuning(host);
+
+ sdhci_reset_for(host, TUNING_ABORT);
+
+ sdhci_end_tuning(host);
+
+ mmc_send_abort_tuning(host->mmc, opcode);
+}
+EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
+
+/*
+ * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
+ * tuning command does not have a data payload (or rather the hardware does it
+ * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
+ * interrupt setup is different to other commands and there is no timeout
+ * interrupt so special handling is needed.
+ */
+void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
+{
+ struct mmc_host *mmc = host->mmc;
+ struct mmc_command cmd = {};
+ struct mmc_request mrq = {};
+ unsigned long flags;
+ u32 b = host->sdma_boundary;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ cmd.opcode = opcode;
+ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
+ cmd.mrq = &mrq;
+
+ mrq.cmd = &cmd;
+ /*
+ * In response to CMD19, the card sends 64 bytes of tuning
+ * block to the Host Controller. So we set the block size
+ * to 64 here.
+ */
+ if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
+ mmc->ios.bus_width == MMC_BUS_WIDTH_8)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
+ else
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
+
+ /*
+ * The tuning block is sent by the card to the host controller.
+ * So we set the TRNS_READ bit in the Transfer Mode register.
+ * This also takes care of setting DMA Enable and Multi Block
+ * Select in the same register to 0.
+ */
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ if (!sdhci_send_command_retry(host, &cmd, flags)) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ host->tuning_done = 0;
+ return;
+ }
+
+ host->cmd = NULL;
+
+ sdhci_del_timer(host, &mrq);
+
+ host->tuning_done = 0;
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ /* Wait for Buffer Read Ready interrupt */
+ wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
+ msecs_to_jiffies(50));
+
+}
+EXPORT_SYMBOL_GPL(sdhci_send_tuning);
+
+static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
+{
+ int i;
+
+ /*
+ * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
+ * of loops reaches tuning loop count.
+ */
+ for (i = 0; i < host->tuning_loop_count; i++) {
+ u16 ctrl;
+
+ sdhci_send_tuning(host, opcode);
+
+ if (!host->tuning_done) {
+ pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
+ mmc_hostname(host->mmc));
+ sdhci_abort_tuning(host, opcode);
+ return -ETIMEDOUT;
+ }
+
+ /* Spec does not require a delay between tuning cycles */
+ if (host->tuning_delay > 0)
+ mdelay(host->tuning_delay);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
+ if (ctrl & SDHCI_CTRL_TUNED_CLK)
+ return 0; /* Success! */
+ break;
+ }
+
+ }
+
+ pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
+ mmc_hostname(host->mmc));
+ sdhci_reset_tuning(host);
+ return -EAGAIN;
+}
+
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int err = 0;
+ unsigned int tuning_count = 0;
+ bool hs400_tuning;
+
+ hs400_tuning = host->flags & SDHCI_HS400_TUNING;
+
+ if (host->tuning_mode == SDHCI_TUNING_MODE_1)
+ tuning_count = host->tuning_count;
+
+ /*
+ * The Host Controller needs tuning in case of SDR104 and DDR50
+ * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
+ * the Capabilities register.
+ * If the Host Controller supports the HS200 mode then the
+ * tuning function has to be executed.
+ */
+ switch (host->timing) {
+ /* HS400 tuning is done in HS200 mode */
+ case MMC_TIMING_MMC_HS400:
+ err = -EINVAL;
+ goto out;
+
+ case MMC_TIMING_MMC_HS200:
+ /*
+ * Periodic re-tuning for HS400 is not expected to be needed, so
+ * disable it here.
+ */
+ if (hs400_tuning)
+ tuning_count = 0;
+ break;
+
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_UHS_DDR50:
+ break;
+
+ case MMC_TIMING_UHS_SDR50:
+ if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
+ break;
+ fallthrough;
+
+ default:
+ goto out;
+ }
+
+ if (host->ops->platform_execute_tuning) {
+ err = host->ops->platform_execute_tuning(host, opcode);
+ goto out;
+ }
+
+ mmc->retune_period = tuning_count;
+
+ if (host->tuning_delay < 0)
+ host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
+
+ sdhci_start_tuning(host);
+
+ host->tuning_err = __sdhci_execute_tuning(host, opcode);
+
+ sdhci_end_tuning(host);
+out:
+ host->flags &= ~SDHCI_HS400_TUNING;
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
+
+static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
+{
+ /* Host Controller v3.00 defines preset value registers */
+ if (host->version < SDHCI_SPEC_300)
+ return;
+
+ /*
+ * We only enable or disable Preset Value if they are not already
+ * enabled or disabled respectively. Otherwise, we bail out.
+ */
+ if (host->preset_enabled != enable) {
+ u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ if (enable)
+ ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
+ else
+ ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ if (enable)
+ host->flags |= SDHCI_PV_ENABLED;
+ else
+ host->flags &= ~SDHCI_PV_ENABLED;
+
+ host->preset_enabled = enable;
+ }
+}
+
+static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
+ int err)
+{
+ struct mmc_data *data = mrq->data;
+
+ if (data->host_cookie != COOKIE_UNMAPPED)
+ dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
+ mmc_get_dma_dir(data));
+
+ data->host_cookie = COOKIE_UNMAPPED;
+}
+
+static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ mrq->data->host_cookie = COOKIE_UNMAPPED;
+
+ /*
+ * No pre-mapping in the pre hook if we're using the bounce buffer,
+ * for that we would need two bounce buffers since one buffer is
+ * in flight when this is getting called.
+ */
+ if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
+ sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
+}
+
+static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
+{
+ if (host->data_cmd) {
+ host->data_cmd->error = err;
+ sdhci_finish_mrq(host, host->data_cmd->mrq);
+ }
+
+ if (host->cmd) {
+ host->cmd->error = err;
+ sdhci_finish_mrq(host, host->cmd->mrq);
+ }
+}
+
+static void sdhci_card_event(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+ int present;
+
+ /* First check if client has provided their own card event */
+ if (host->ops->card_event)
+ host->ops->card_event(host);
+
+ present = mmc->ops->get_cd(mmc);
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ /* Check sdhci_has_requests() first in case we are runtime suspended */
+ if (sdhci_has_requests(host) && !present) {
+ pr_err("%s: Card removed during transfer!\n",
+ mmc_hostname(mmc));
+ pr_err("%s: Resetting controller.\n",
+ mmc_hostname(mmc));
+
+ sdhci_reset_for(host, CARD_REMOVED);
+
+ sdhci_error_out_mrqs(host, -ENOMEDIUM);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static const struct mmc_host_ops sdhci_ops = {
+ .request = sdhci_request,
+ .post_req = sdhci_post_req,
+ .pre_req = sdhci_pre_req,
+ .set_ios = sdhci_set_ios,
+ .get_cd = sdhci_get_cd,
+ .get_ro = sdhci_get_ro,
+ .card_hw_reset = sdhci_hw_reset,
+ .enable_sdio_irq = sdhci_enable_sdio_irq,
+ .ack_sdio_irq = sdhci_ack_sdio_irq,
+ .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
+ .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
+ .execute_tuning = sdhci_execute_tuning,
+ .card_event = sdhci_card_event,
+ .card_busy = sdhci_card_busy,
+};
+
+/*****************************************************************************\
+ * *
+ * Request done *
+ * *
+\*****************************************************************************/
+
+static bool sdhci_request_done(struct sdhci_host *host)
+{
+ unsigned long flags;
+ struct mmc_request *mrq;
+ int i;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ for (i = 0; i < SDHCI_MAX_MRQS; i++) {
+ mrq = host->mrqs_done[i];
+ if (mrq)
+ break;
+ }
+
+ if (!mrq) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ return true;
+ }
+
+ /*
+ * The controller needs a reset of internal state machines
+ * upon error conditions.
+ */
+ if (sdhci_needs_reset(host, mrq)) {
+ /*
+ * Do not finish until command and data lines are available for
+ * reset. Note there can only be one other mrq, so it cannot
+ * also be in mrqs_done, otherwise host->cmd and host->data_cmd
+ * would both be null.
+ */
+ if (host->cmd || host->data_cmd) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ return true;
+ }
+
+ /* Some controllers need this kick or reset won't work here */
+ if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
+ /* This is to force an update */
+ host->ops->set_clock(host, host->clock);
+
+ sdhci_reset_for(host, REQUEST_ERROR);
+
+ host->pending_reset = false;
+ }
+
+ /*
+ * Always unmap the data buffers if they were mapped by
+ * sdhci_prepare_data() whenever we finish with a request.
+ * This avoids leaking DMA mappings on error.
+ */
+ if (host->flags & SDHCI_REQ_USE_DMA) {
+ struct mmc_data *data = mrq->data;
+
+ if (host->use_external_dma && data &&
+ (mrq->cmd->error || data->error)) {
+ struct dma_chan *chan = sdhci_external_dma_channel(host, data);
+
+ host->mrqs_done[i] = NULL;
+ spin_unlock_irqrestore(&host->lock, flags);
+ dmaengine_terminate_sync(chan);
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_set_mrq_done(host, mrq);
+ }
+
+ if (data && data->host_cookie == COOKIE_MAPPED) {
+ if (host->bounce_buffer) {
+ /*
+ * On reads, copy the bounced data into the
+ * sglist
+ */
+ if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
+ unsigned int length = data->bytes_xfered;
+
+ if (length > host->bounce_buffer_size) {
+ pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
+ mmc_hostname(host->mmc),
+ host->bounce_buffer_size,
+ data->bytes_xfered);
+ /* Cap it down and continue */
+ length = host->bounce_buffer_size;
+ }
+ dma_sync_single_for_cpu(
+ mmc_dev(host->mmc),
+ host->bounce_addr,
+ host->bounce_buffer_size,
+ DMA_FROM_DEVICE);
+ sg_copy_from_buffer(data->sg,
+ data->sg_len,
+ host->bounce_buffer,
+ length);
+ } else {
+ /* No copying, just switch ownership */
+ dma_sync_single_for_cpu(
+ mmc_dev(host->mmc),
+ host->bounce_addr,
+ host->bounce_buffer_size,
+ mmc_get_dma_dir(data));
+ }
+ } else {
+ /* Unmap the raw data */
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len,
+ mmc_get_dma_dir(data));
+ }
+ data->host_cookie = COOKIE_UNMAPPED;
+ }
+ }
+
+ host->mrqs_done[i] = NULL;
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ if (host->ops->request_done)
+ host->ops->request_done(host, mrq);
+ else
+ mmc_request_done(host->mmc, mrq);
+
+ return false;
+}
+
+static void sdhci_complete_work(struct work_struct *work)
+{
+ struct sdhci_host *host = container_of(work, struct sdhci_host,
+ complete_work);
+
+ while (!sdhci_request_done(host))
+ ;
+}
+
+static void sdhci_timeout_timer(struct timer_list *t)
+{
+ struct sdhci_host *host;
+ unsigned long flags;
+
+ host = from_timer(host, t, timer);
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
+ pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
+ mmc_hostname(host->mmc));
+ sdhci_err_stats_inc(host, REQ_TIMEOUT);
+ sdhci_dumpregs(host);
+
+ host->cmd->error = -ETIMEDOUT;
+ sdhci_finish_mrq(host, host->cmd->mrq);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void sdhci_timeout_data_timer(struct timer_list *t)
+{
+ struct sdhci_host *host;
+ unsigned long flags;
+
+ host = from_timer(host, t, data_timer);
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (host->data || host->data_cmd ||
+ (host->cmd && sdhci_data_line_cmd(host->cmd))) {
+ pr_err("%s: Timeout waiting for hardware interrupt.\n",
+ mmc_hostname(host->mmc));
+ sdhci_err_stats_inc(host, REQ_TIMEOUT);
+ sdhci_dumpregs(host);
+
+ if (host->data) {
+ host->data->error = -ETIMEDOUT;
+ __sdhci_finish_data(host, true);
+ queue_work(host->complete_wq, &host->complete_work);
+ } else if (host->data_cmd) {
+ host->data_cmd->error = -ETIMEDOUT;
+ sdhci_finish_mrq(host, host->data_cmd->mrq);
+ } else {
+ host->cmd->error = -ETIMEDOUT;
+ sdhci_finish_mrq(host, host->cmd->mrq);
+ }
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+/*****************************************************************************\
+ * *
+ * Interrupt handling *
+ * *
+\*****************************************************************************/
+
+static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
+{
+ /* Handle auto-CMD12 error */
+ if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
+ struct mmc_request *mrq = host->data_cmd->mrq;
+ u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
+ int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
+ SDHCI_INT_DATA_TIMEOUT :
+ SDHCI_INT_DATA_CRC;
+
+ /* Treat auto-CMD12 error the same as data error */
+ if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
+ *intmask_p |= data_err_bit;
+ return;
+ }
+ }
+
+ if (!host->cmd) {
+ /*
+ * SDHCI recovers from errors by resetting the cmd and data
+ * circuits. Until that is done, there very well might be more
+ * interrupts, so ignore them in that case.
+ */
+ if (host->pending_reset)
+ return;
+ pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
+ mmc_hostname(host->mmc), (unsigned)intmask);
+ sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
+ sdhci_dumpregs(host);
+ return;
+ }
+
+ if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
+ SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
+ if (intmask & SDHCI_INT_TIMEOUT) {
+ host->cmd->error = -ETIMEDOUT;
+ sdhci_err_stats_inc(host, CMD_TIMEOUT);
+ } else {
+ host->cmd->error = -EILSEQ;
+ if (!mmc_op_tuning(host->cmd->opcode))
+ sdhci_err_stats_inc(host, CMD_CRC);
+ }
+ /* Treat data command CRC error the same as data CRC error */
+ if (host->cmd->data &&
+ (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
+ SDHCI_INT_CRC) {
+ host->cmd = NULL;
+ *intmask_p |= SDHCI_INT_DATA_CRC;
+ return;
+ }
+
+ __sdhci_finish_mrq(host, host->cmd->mrq);
+ return;
+ }
+
+ /* Handle auto-CMD23 error */
+ if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
+ struct mmc_request *mrq = host->cmd->mrq;
+ u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
+ int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
+ -ETIMEDOUT :
+ -EILSEQ;
+
+ sdhci_err_stats_inc(host, AUTO_CMD);
+
+ if (sdhci_auto_cmd23(host, mrq)) {
+ mrq->sbc->error = err;
+ __sdhci_finish_mrq(host, mrq);
+ return;
+ }
+ }
+
+ if (intmask & SDHCI_INT_RESPONSE)
+ sdhci_finish_command(host);
+}
+
+static void sdhci_adma_show_error(struct sdhci_host *host)
+{
+ void *desc = host->adma_table;
+ dma_addr_t dma = host->adma_addr;
+
+ sdhci_dumpregs(host);
+
+ while (true) {
+ struct sdhci_adma2_64_desc *dma_desc = desc;
+
+ if (host->flags & SDHCI_USE_64_BIT_DMA)
+ SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
+ (unsigned long long)dma,
+ le32_to_cpu(dma_desc->addr_hi),
+ le32_to_cpu(dma_desc->addr_lo),
+ le16_to_cpu(dma_desc->len),
+ le16_to_cpu(dma_desc->cmd));
+ else
+ SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
+ (unsigned long long)dma,
+ le32_to_cpu(dma_desc->addr_lo),
+ le16_to_cpu(dma_desc->len),
+ le16_to_cpu(dma_desc->cmd));
+
+ desc += host->desc_sz;
+ dma += host->desc_sz;
+
+ if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
+ break;
+ }
+}
+
+static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
+{
+ /*
+ * CMD19 generates _only_ Buffer Read Ready interrupt if
+ * use sdhci_send_tuning.
+ * Need to exclude this case: PIO mode and use mmc_send_tuning,
+ * If not, sdhci_transfer_pio will never be called, make the
+ * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
+ */
+ if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
+ if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
+ host->tuning_done = 1;
+ wake_up(&host->buf_ready_int);
+ return;
+ }
+ }
+
+ if (!host->data) {
+ struct mmc_command *data_cmd = host->data_cmd;
+
+ /*
+ * The "data complete" interrupt is also used to
+ * indicate that a busy state has ended. See comment
+ * above in sdhci_cmd_irq().
+ */
+ if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
+ if (intmask & SDHCI_INT_DATA_TIMEOUT) {
+ host->data_cmd = NULL;
+ data_cmd->error = -ETIMEDOUT;
+ sdhci_err_stats_inc(host, CMD_TIMEOUT);
+ __sdhci_finish_mrq(host, data_cmd->mrq);
+ return;
+ }
+ if (intmask & SDHCI_INT_DATA_END) {
+ host->data_cmd = NULL;
+ /*
+ * Some cards handle busy-end interrupt
+ * before the command completed, so make
+ * sure we do things in the proper order.
+ */
+ if (host->cmd == data_cmd)
+ return;
+
+ __sdhci_finish_mrq(host, data_cmd->mrq);
+ return;
+ }
+ }
+
+ /*
+ * SDHCI recovers from errors by resetting the cmd and data
+ * circuits. Until that is done, there very well might be more
+ * interrupts, so ignore them in that case.
+ */
+ if (host->pending_reset)
+ return;
+
+ pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
+ mmc_hostname(host->mmc), (unsigned)intmask);
+ sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
+ sdhci_dumpregs(host);
+
+ return;
+ }
+
+ if (intmask & SDHCI_INT_DATA_TIMEOUT) {
+ host->data->error = -ETIMEDOUT;
+ sdhci_err_stats_inc(host, DAT_TIMEOUT);
+ } else if (intmask & SDHCI_INT_DATA_END_BIT) {
+ host->data->error = -EILSEQ;
+ if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
+ sdhci_err_stats_inc(host, DAT_CRC);
+ } else if ((intmask & SDHCI_INT_DATA_CRC) &&
+ SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
+ != MMC_BUS_TEST_R) {
+ host->data->error = -EILSEQ;
+ if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
+ sdhci_err_stats_inc(host, DAT_CRC);
+ } else if (intmask & SDHCI_INT_ADMA_ERROR) {
+ pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
+ intmask);
+ sdhci_adma_show_error(host);
+ sdhci_err_stats_inc(host, ADMA);
+ host->data->error = -EIO;
+ if (host->ops->adma_workaround)
+ host->ops->adma_workaround(host, intmask);
+ }
+
+ if (host->data->error)
+ sdhci_finish_data(host);
+ else {
+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
+ sdhci_transfer_pio(host);
+
+ /*
+ * We currently don't do anything fancy with DMA
+ * boundaries, but as we can't disable the feature
+ * we need to at least restart the transfer.
+ *
+ * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
+ * should return a valid address to continue from, but as
+ * some controllers are faulty, don't trust them.
+ */
+ if (intmask & SDHCI_INT_DMA_END) {
+ dma_addr_t dmastart, dmanow;
+
+ dmastart = sdhci_sdma_address(host);
+ dmanow = dmastart + host->data->bytes_xfered;
+ /*
+ * Force update to the next DMA block boundary.
+ */
+ dmanow = (dmanow &
+ ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+ SDHCI_DEFAULT_BOUNDARY_SIZE;
+ host->data->bytes_xfered = dmanow - dmastart;
+ DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
+ &dmastart, host->data->bytes_xfered, &dmanow);
+ sdhci_set_sdma_addr(host, dmanow);
+ }
+
+ if (intmask & SDHCI_INT_DATA_END) {
+ if (host->cmd == host->data_cmd) {
+ /*
+ * Data managed to finish before the
+ * command completed. Make sure we do
+ * things in the proper order.
+ */
+ host->data_early = 1;
+ } else {
+ sdhci_finish_data(host);
+ }
+ }
+ }
+}
+
+static inline bool sdhci_defer_done(struct sdhci_host *host,
+ struct mmc_request *mrq)
+{
+ struct mmc_data *data = mrq->data;
+
+ return host->pending_reset || host->always_defer_done ||
+ ((host->flags & SDHCI_REQ_USE_DMA) && data &&
+ data->host_cookie == COOKIE_MAPPED);
+}
+
+static irqreturn_t sdhci_irq(int irq, void *dev_id)
+{
+ struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
+ irqreturn_t result = IRQ_NONE;
+ struct sdhci_host *host = dev_id;
+ u32 intmask, mask, unexpected = 0;
+ int max_loops = 16;
+ int i;
+
+ spin_lock(&host->lock);
+
+ if (host->runtime_suspended) {
+ spin_unlock(&host->lock);
+ return IRQ_NONE;
+ }
+
+ intmask = sdhci_readl(host, SDHCI_INT_STATUS);
+ if (!intmask || intmask == 0xffffffff) {
+ result = IRQ_NONE;
+ goto out;
+ }
+
+ do {
+ DBG("IRQ status 0x%08x\n", intmask);
+
+ if (host->ops->irq) {
+ intmask = host->ops->irq(host, intmask);
+ if (!intmask)
+ goto cont;
+ }
+
+ /* Clear selected interrupts. */
+ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
+ SDHCI_INT_BUS_POWER);
+ sdhci_writel(host, mask, SDHCI_INT_STATUS);
+
+ if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+ u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
+ SDHCI_CARD_PRESENT;
+
+ /*
+ * There is a observation on i.mx esdhc. INSERT
+ * bit will be immediately set again when it gets
+ * cleared, if a card is inserted. We have to mask
+ * the irq to prevent interrupt storm which will
+ * freeze the system. And the REMOVE gets the
+ * same situation.
+ *
+ * More testing are needed here to ensure it works
+ * for other platforms though.
+ */
+ host->ier &= ~(SDHCI_INT_CARD_INSERT |
+ SDHCI_INT_CARD_REMOVE);
+ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
+ SDHCI_INT_CARD_INSERT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+ sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
+ SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
+
+ host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
+ SDHCI_INT_CARD_REMOVE);
+ result = IRQ_WAKE_THREAD;
+ }
+
+ if (intmask & SDHCI_INT_CMD_MASK)
+ sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
+
+ if (intmask & SDHCI_INT_DATA_MASK)
+ sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
+
+ if (intmask & SDHCI_INT_BUS_POWER)
+ pr_err("%s: Card is consuming too much power!\n",
+ mmc_hostname(host->mmc));
+
+ if (intmask & SDHCI_INT_RETUNE)
+ mmc_retune_needed(host->mmc);
+
+ if ((intmask & SDHCI_INT_CARD_INT) &&
+ (host->ier & SDHCI_INT_CARD_INT)) {
+ sdhci_enable_sdio_irq_nolock(host, false);
+ sdio_signal_irq(host->mmc);
+ }
+
+ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
+ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
+ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
+ SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
+
+ if (intmask) {
+ unexpected |= intmask;
+ sdhci_writel(host, intmask, SDHCI_INT_STATUS);
+ }
+cont:
+ if (result == IRQ_NONE)
+ result = IRQ_HANDLED;
+
+ intmask = sdhci_readl(host, SDHCI_INT_STATUS);
+ } while (intmask && --max_loops);
+
+ /* Determine if mrqs can be completed immediately */
+ for (i = 0; i < SDHCI_MAX_MRQS; i++) {
+ struct mmc_request *mrq = host->mrqs_done[i];
+
+ if (!mrq)
+ continue;
+
+ if (sdhci_defer_done(host, mrq)) {
+ result = IRQ_WAKE_THREAD;
+ } else {
+ mrqs_done[i] = mrq;
+ host->mrqs_done[i] = NULL;
+ }
+ }
+out:
+ if (host->deferred_cmd)
+ result = IRQ_WAKE_THREAD;
+
+ spin_unlock(&host->lock);
+
+ /* Process mrqs ready for immediate completion */
+ for (i = 0; i < SDHCI_MAX_MRQS; i++) {
+ if (!mrqs_done[i])
+ continue;
+
+ if (host->ops->request_done)
+ host->ops->request_done(host, mrqs_done[i]);
+ else
+ mmc_request_done(host->mmc, mrqs_done[i]);
+ }
+
+ if (unexpected) {
+ pr_err("%s: Unexpected interrupt 0x%08x.\n",
+ mmc_hostname(host->mmc), unexpected);
+ sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
+ sdhci_dumpregs(host);
+ }
+
+ return result;
+}
+
+static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
+{
+ struct sdhci_host *host = dev_id;
+ struct mmc_command *cmd;
+ unsigned long flags;
+ u32 isr;
+
+ while (!sdhci_request_done(host))
+ ;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ isr = host->thread_isr;
+ host->thread_isr = 0;
+
+ cmd = host->deferred_cmd;
+ if (cmd && !sdhci_send_command_retry(host, cmd, flags))
+ sdhci_finish_mrq(host, cmd->mrq);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+ struct mmc_host *mmc = host->mmc;
+
+ mmc->ops->card_event(mmc);
+ mmc_detect_change(mmc, msecs_to_jiffies(200));
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*****************************************************************************\
+ * *
+ * Suspend/resume *
+ * *
+\*****************************************************************************/
+
+#ifdef CONFIG_PM
+
+static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
+{
+ return mmc_card_is_removable(host->mmc) &&
+ !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
+ !mmc_can_gpio_cd(host->mmc);
+}
+
+/*
+ * To enable wakeup events, the corresponding events have to be enabled in
+ * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
+ * Table' in the SD Host Controller Standard Specification.
+ * It is useless to restore SDHCI_INT_ENABLE state in
+ * sdhci_disable_irq_wakeups() since it will be set by
+ * sdhci_enable_card_detection() or sdhci_init().
+ */
+static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
+{
+ u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
+ SDHCI_WAKE_ON_INT;
+ u32 irq_val = 0;
+ u8 wake_val = 0;
+ u8 val;
+
+ if (sdhci_cd_irq_can_wakeup(host)) {
+ wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
+ irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
+ }
+
+ if (mmc_card_wake_sdio_irq(host->mmc)) {
+ wake_val |= SDHCI_WAKE_ON_INT;
+ irq_val |= SDHCI_INT_CARD_INT;
+ }
+
+ if (!irq_val)
+ return false;
+
+ val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
+ val &= ~mask;
+ val |= wake_val;
+ sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
+
+ sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
+
+ host->irq_wake_enabled = !enable_irq_wake(host->irq);
+
+ return host->irq_wake_enabled;
+}
+
+static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
+{
+ u8 val;
+ u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
+ | SDHCI_WAKE_ON_INT;
+
+ val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
+ val &= ~mask;
+ sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
+
+ disable_irq_wake(host->irq);
+
+ host->irq_wake_enabled = false;
+}
+
+int sdhci_suspend_host(struct sdhci_host *host)
+{
+ sdhci_disable_card_detection(host);
+
+ mmc_retune_timer_stop(host->mmc);
+
+ if (!device_may_wakeup(mmc_dev(host->mmc)) ||
+ !sdhci_enable_irq_wakeups(host)) {
+ host->ier = 0;
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+ }
+
+ return 0;
+}
+
+EXPORT_SYMBOL_GPL(sdhci_suspend_host);
+
+int sdhci_resume_host(struct sdhci_host *host)
+{
+ struct mmc_host *mmc = host->mmc;
+ int ret = 0;
+
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if (host->ops->enable_dma)
+ host->ops->enable_dma(host);
+ }
+
+ if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
+ (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
+ /* Card keeps power but host controller does not */
+ sdhci_init(host, 0);
+ host->pwr = 0;
+ host->clock = 0;
+ host->reinit_uhs = true;
+ mmc->ops->set_ios(mmc, &mmc->ios);
+ } else {
+ sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
+ }
+
+ if (host->irq_wake_enabled) {
+ sdhci_disable_irq_wakeups(host);
+ } else {
+ ret = request_threaded_irq(host->irq, sdhci_irq,
+ sdhci_thread_irq, IRQF_SHARED,
+ mmc_hostname(mmc), host);
+ if (ret)
+ return ret;
+ }
+
+ sdhci_enable_card_detection(host);
+
+ return ret;
+}
+
+EXPORT_SYMBOL_GPL(sdhci_resume_host);
+
+int sdhci_runtime_suspend_host(struct sdhci_host *host)
+{
+ unsigned long flags;
+
+ mmc_retune_timer_stop(host->mmc);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->ier &= SDHCI_INT_CARD_INT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ synchronize_hardirq(host->irq);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->runtime_suspended = true;
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
+
+int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
+{
+ struct mmc_host *mmc = host->mmc;
+ unsigned long flags;
+ int host_flags = host->flags;
+
+ if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if (host->ops->enable_dma)
+ host->ops->enable_dma(host);
+ }
+
+ sdhci_init(host, soft_reset);
+
+ if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
+ mmc->ios.power_mode != MMC_POWER_OFF) {
+ /* Force clock and power re-program */
+ host->pwr = 0;
+ host->clock = 0;
+ host->reinit_uhs = true;
+ mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
+ mmc->ops->set_ios(mmc, &mmc->ios);
+
+ if ((host_flags & SDHCI_PV_ENABLED) &&
+ !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_enable_preset_value(host, true);
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
+ mmc->ops->hs400_enhanced_strobe)
+ mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
+ }
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->runtime_suspended = false;
+
+ /* Enable SDIO IRQ */
+ if (sdio_irq_claimed(mmc))
+ sdhci_enable_sdio_irq_nolock(host, true);
+
+ /* Enable Card Detection */
+ sdhci_enable_card_detection(host);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
+
+#endif /* CONFIG_PM */
+
+/*****************************************************************************\
+ * *
+ * Command Queue Engine (CQE) helpers *
+ * *
+\*****************************************************************************/
+
+void sdhci_cqe_enable(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+ u8 ctrl;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ /*
+ * Host from V4.10 supports ADMA3 DMA type.
+ * ADMA3 performs integrated descriptor which is more suitable
+ * for cmd queuing to fetch both command and transfer descriptors.
+ */
+ if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
+ ctrl |= SDHCI_CTRL_ADMA3;
+ else if (host->flags & SDHCI_USE_64_BIT_DMA)
+ ctrl |= SDHCI_CTRL_ADMA64;
+ else
+ ctrl |= SDHCI_CTRL_ADMA32;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
+ SDHCI_BLOCK_SIZE);
+
+ /* Set maximum timeout */
+ sdhci_set_timeout(host, NULL);
+
+ host->ier = host->cqe_ier;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+ host->cqe_on = true;
+
+ pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
+ mmc_hostname(mmc), host->ier,
+ sdhci_readl(host, SDHCI_INT_STATUS));
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
+
+void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ sdhci_set_default_irqs(host);
+
+ host->cqe_on = false;
+
+ if (recovery)
+ sdhci_reset_for(host, CQE_RECOVERY);
+
+ pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
+ mmc_hostname(mmc), host->ier,
+ sdhci_readl(host, SDHCI_INT_STATUS));
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
+
+bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
+ int *data_error)
+{
+ u32 mask;
+
+ if (!host->cqe_on)
+ return false;
+
+ if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
+ *cmd_error = -EILSEQ;
+ if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
+ sdhci_err_stats_inc(host, CMD_CRC);
+ } else if (intmask & SDHCI_INT_TIMEOUT) {
+ *cmd_error = -ETIMEDOUT;
+ sdhci_err_stats_inc(host, CMD_TIMEOUT);
+ } else
+ *cmd_error = 0;
+
+ if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) {
+ *data_error = -EILSEQ;
+ if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
+ sdhci_err_stats_inc(host, DAT_CRC);
+ } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
+ *data_error = -ETIMEDOUT;
+ sdhci_err_stats_inc(host, DAT_TIMEOUT);
+ } else if (intmask & SDHCI_INT_ADMA_ERROR) {
+ *data_error = -EIO;
+ sdhci_err_stats_inc(host, ADMA);
+ } else
+ *data_error = 0;
+
+ /* Clear selected interrupts. */
+ mask = intmask & host->cqe_ier;
+ sdhci_writel(host, mask, SDHCI_INT_STATUS);
+
+ if (intmask & SDHCI_INT_BUS_POWER)
+ pr_err("%s: Card is consuming too much power!\n",
+ mmc_hostname(host->mmc));
+
+ intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
+ if (intmask) {
+ sdhci_writel(host, intmask, SDHCI_INT_STATUS);
+ pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
+ mmc_hostname(host->mmc), intmask);
+ sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
+ sdhci_dumpregs(host);
+ }
+
+ return true;
+}
+EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
+
+/*****************************************************************************\
+ * *
+ * Device allocation/registration *
+ * *
+\*****************************************************************************/
+
+struct sdhci_host *sdhci_alloc_host(struct device *dev,
+ size_t priv_size)
+{
+ struct mmc_host *mmc;
+ struct sdhci_host *host;
+
+ WARN_ON(dev == NULL);
+
+ mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
+ if (!mmc)
+ return ERR_PTR(-ENOMEM);
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+ host->mmc_host_ops = sdhci_ops;
+ mmc->ops = &host->mmc_host_ops;
+
+ host->flags = SDHCI_SIGNALING_330;
+
+ host->cqe_ier = SDHCI_CQE_INT_MASK;
+ host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
+
+ host->tuning_delay = -1;
+ host->tuning_loop_count = MAX_TUNING_LOOP;
+
+ host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
+
+ /*
+ * The DMA table descriptor count is calculated as the maximum
+ * number of segments times 2, to allow for an alignment
+ * descriptor for each segment, plus 1 for a nop end descriptor.
+ */
+ host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
+ host->max_adma = 65536;
+
+ host->max_timeout_count = 0xE;
+
+ return host;
+}
+
+EXPORT_SYMBOL_GPL(sdhci_alloc_host);
+
+static int sdhci_set_dma_mask(struct sdhci_host *host)
+{
+ struct mmc_host *mmc = host->mmc;
+ struct device *dev = mmc_dev(mmc);
+ int ret = -EINVAL;
+
+ if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
+ host->flags &= ~SDHCI_USE_64_BIT_DMA;
+
+ /* Try 64-bit mask if hardware is capable of it */
+ if (host->flags & SDHCI_USE_64_BIT_DMA) {
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (ret) {
+ pr_warn("%s: Failed to set 64-bit DMA mask.\n",
+ mmc_hostname(mmc));
+ host->flags &= ~SDHCI_USE_64_BIT_DMA;
+ }
+ }
+
+ /* 32-bit mask as default & fallback */
+ if (ret) {
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+ if (ret)
+ pr_warn("%s: Failed to set 32-bit DMA mask.\n",
+ mmc_hostname(mmc));
+ }
+
+ return ret;
+}
+
+void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
+ const u32 *caps, const u32 *caps1)
+{
+ u16 v;
+ u64 dt_caps_mask = 0;
+ u64 dt_caps = 0;
+
+ if (host->read_caps)
+ return;
+
+ host->read_caps = true;
+
+ if (debug_quirks)
+ host->quirks = debug_quirks;
+
+ if (debug_quirks2)
+ host->quirks2 = debug_quirks2;
+
+ sdhci_reset_for_all(host);
+
+ if (host->v4_mode)
+ sdhci_do_enable_v4_mode(host);
+
+ device_property_read_u64(mmc_dev(host->mmc),
+ "sdhci-caps-mask", &dt_caps_mask);
+ device_property_read_u64(mmc_dev(host->mmc),
+ "sdhci-caps", &dt_caps);
+
+ v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
+ host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
+
+ if (caps) {
+ host->caps = *caps;
+ } else {
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+ host->caps &= ~lower_32_bits(dt_caps_mask);
+ host->caps |= lower_32_bits(dt_caps);
+ }
+
+ if (host->version < SDHCI_SPEC_300)
+ return;
+
+ if (caps1) {
+ host->caps1 = *caps1;
+ } else {
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~upper_32_bits(dt_caps_mask);
+ host->caps1 |= upper_32_bits(dt_caps);
+ }
+}
+EXPORT_SYMBOL_GPL(__sdhci_read_caps);
+
+static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
+{
+ struct mmc_host *mmc = host->mmc;
+ unsigned int max_blocks;
+ unsigned int bounce_size;
+ int ret;
+
+ /*
+ * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
+ * has diminishing returns, this is probably because SD/MMC
+ * cards are usually optimized to handle this size of requests.
+ */
+ bounce_size = SZ_64K;
+ /*
+ * Adjust downwards to maximum request size if this is less
+ * than our segment size, else hammer down the maximum
+ * request size to the maximum buffer size.
+ */
+ if (mmc->max_req_size < bounce_size)
+ bounce_size = mmc->max_req_size;
+ max_blocks = bounce_size / 512;
+
+ /*
+ * When we just support one segment, we can get significant
+ * speedups by the help of a bounce buffer to group scattered
+ * reads/writes together.
+ */
+ host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
+ bounce_size,
+ GFP_KERNEL);
+ if (!host->bounce_buffer) {
+ pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
+ mmc_hostname(mmc),
+ bounce_size);
+ /*
+ * Exiting with zero here makes sure we proceed with
+ * mmc->max_segs == 1.
+ */
+ return;
+ }
+
+ host->bounce_addr = dma_map_single(mmc_dev(mmc),
+ host->bounce_buffer,
+ bounce_size,
+ DMA_BIDIRECTIONAL);
+ ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
+ if (ret) {
+ devm_kfree(mmc_dev(mmc), host->bounce_buffer);
+ host->bounce_buffer = NULL;
+ /* Again fall back to max_segs == 1 */
+ return;
+ }
+
+ host->bounce_buffer_size = bounce_size;
+
+ /* Lie about this since we're bouncing */
+ mmc->max_segs = max_blocks;
+ mmc->max_seg_size = bounce_size;
+ mmc->max_req_size = bounce_size;
+
+ pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
+ mmc_hostname(mmc), max_blocks, bounce_size);
+}
+
+static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
+{
+ /*
+ * According to SD Host Controller spec v4.10, bit[27] added from
+ * version 4.10 in Capabilities Register is used as 64-bit System
+ * Address support for V4 mode.
+ */
+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
+ return host->caps & SDHCI_CAN_64BIT_V4;
+
+ return host->caps & SDHCI_CAN_64BIT;
+}
+
+int sdhci_setup_host(struct sdhci_host *host)
+{
+ struct mmc_host *mmc;
+ u32 max_current_caps;
+ unsigned int ocr_avail;
+ unsigned int override_timeout_clk;
+ u32 max_clk;
+ int ret = 0;
+ bool enable_vqmmc = false;
+
+ WARN_ON(host == NULL);
+ if (host == NULL)
+ return -EINVAL;
+
+ mmc = host->mmc;
+
+ /*
+ * If there are external regulators, get them. Note this must be done
+ * early before resetting the host and reading the capabilities so that
+ * the host can take the appropriate action if regulators are not
+ * available.
+ */
+ if (!mmc->supply.vqmmc) {
+ ret = mmc_regulator_get_supply(mmc);
+ if (ret)
+ return ret;
+ enable_vqmmc = true;
+ }
+
+ DBG("Version: 0x%08x | Present: 0x%08x\n",
+ sdhci_readw(host, SDHCI_HOST_VERSION),
+ sdhci_readl(host, SDHCI_PRESENT_STATE));
+ DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
+ sdhci_readl(host, SDHCI_CAPABILITIES),
+ sdhci_readl(host, SDHCI_CAPABILITIES_1));
+
+ sdhci_read_caps(host);
+
+ override_timeout_clk = host->timeout_clk;
+
+ if (host->version > SDHCI_SPEC_420) {
+ pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
+ mmc_hostname(mmc), host->version);
+ }
+
+ if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
+ host->flags |= SDHCI_USE_SDMA;
+ else if (!(host->caps & SDHCI_CAN_DO_SDMA))
+ DBG("Controller doesn't have SDMA capability\n");
+ else
+ host->flags |= SDHCI_USE_SDMA;
+
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
+ (host->flags & SDHCI_USE_SDMA)) {
+ DBG("Disabling DMA as it is marked broken\n");
+ host->flags &= ~SDHCI_USE_SDMA;
+ }
+
+ if ((host->version >= SDHCI_SPEC_200) &&
+ (host->caps & SDHCI_CAN_DO_ADMA2))
+ host->flags |= SDHCI_USE_ADMA;
+
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
+ (host->flags & SDHCI_USE_ADMA)) {
+ DBG("Disabling ADMA as it is marked broken\n");
+ host->flags &= ~SDHCI_USE_ADMA;
+ }
+
+ if (sdhci_can_64bit_dma(host))
+ host->flags |= SDHCI_USE_64_BIT_DMA;
+
+ if (host->use_external_dma) {
+ ret = sdhci_external_dma_init(host);
+ if (ret == -EPROBE_DEFER)
+ goto unreg;
+ /*
+ * Fall back to use the DMA/PIO integrated in standard SDHCI
+ * instead of external DMA devices.
+ */
+ else if (ret)
+ sdhci_switch_external_dma(host, false);
+ /* Disable internal DMA sources */
+ else
+ host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
+ }
+
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if (host->ops->set_dma_mask)
+ ret = host->ops->set_dma_mask(host);
+ else
+ ret = sdhci_set_dma_mask(host);
+
+ if (!ret && host->ops->enable_dma)
+ ret = host->ops->enable_dma(host);
+
+ if (ret) {
+ pr_warn("%s: No suitable DMA available - falling back to PIO\n",
+ mmc_hostname(mmc));
+ host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
+
+ ret = 0;
+ }
+ }
+
+ /* SDMA does not support 64-bit DMA if v4 mode not set */
+ if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
+ host->flags &= ~SDHCI_USE_SDMA;
+
+ if (host->flags & SDHCI_USE_ADMA) {
+ dma_addr_t dma;
+ void *buf;
+
+ if (!(host->flags & SDHCI_USE_64_BIT_DMA))
+ host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
+ else if (!host->alloc_desc_sz)
+ host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
+
+ host->desc_sz = host->alloc_desc_sz;
+ host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
+
+ host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
+ /*
+ * Use zalloc to zero the reserved high 32-bits of 128-bit
+ * descriptors so that they never need to be written.
+ */
+ buf = dma_alloc_coherent(mmc_dev(mmc),
+ host->align_buffer_sz + host->adma_table_sz,
+ &dma, GFP_KERNEL);
+ if (!buf) {
+ pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
+ mmc_hostname(mmc));
+ host->flags &= ~SDHCI_USE_ADMA;
+ } else if ((dma + host->align_buffer_sz) &
+ (SDHCI_ADMA2_DESC_ALIGN - 1)) {
+ pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
+ mmc_hostname(mmc));
+ host->flags &= ~SDHCI_USE_ADMA;
+ dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
+ host->adma_table_sz, buf, dma);
+ } else {
+ host->align_buffer = buf;
+ host->align_addr = dma;
+
+ host->adma_table = buf + host->align_buffer_sz;
+ host->adma_addr = dma + host->align_buffer_sz;
+ }
+ }
+
+ /*
+ * If we use DMA, then it's up to the caller to set the DMA
+ * mask, but PIO does not need the hw shim so we set a new
+ * mask here in that case.
+ */
+ if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
+ host->dma_mask = DMA_BIT_MASK(64);
+ mmc_dev(mmc)->dma_mask = &host->dma_mask;
+ }
+
+ if (host->version >= SDHCI_SPEC_300)
+ host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
+ else
+ host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
+
+ host->max_clk *= 1000000;
+ if (host->max_clk == 0 || host->quirks &
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
+ if (!host->ops->get_max_clock) {
+ pr_err("%s: Hardware doesn't specify base clock frequency.\n",
+ mmc_hostname(mmc));
+ ret = -ENODEV;
+ goto undma;
+ }
+ host->max_clk = host->ops->get_max_clock(host);
+ }
+
+ /*
+ * In case of Host Controller v3.00, find out whether clock
+ * multiplier is supported.
+ */
+ host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
+
+ /*
+ * In case the value in Clock Multiplier is 0, then programmable
+ * clock mode is not supported, otherwise the actual clock
+ * multiplier is one more than the value of Clock Multiplier
+ * in the Capabilities Register.
+ */
+ if (host->clk_mul)
+ host->clk_mul += 1;
+
+ /*
+ * Set host parameters.
+ */
+ max_clk = host->max_clk;
+
+ if (host->ops->get_min_clock)
+ mmc->f_min = host->ops->get_min_clock(host);
+ else if (host->version >= SDHCI_SPEC_300) {
+ if (host->clk_mul)
+ max_clk = host->max_clk * host->clk_mul;
+ /*
+ * Divided Clock Mode minimum clock rate is always less than
+ * Programmable Clock Mode minimum clock rate.
+ */
+ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
+ } else
+ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
+
+ if (!mmc->f_max || mmc->f_max > max_clk)
+ mmc->f_max = max_clk;
+
+ if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
+ host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
+
+ if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
+ host->timeout_clk *= 1000;
+
+ if (host->timeout_clk == 0) {
+ if (!host->ops->get_timeout_clock) {
+ pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
+ mmc_hostname(mmc));
+ ret = -ENODEV;
+ goto undma;
+ }
+
+ host->timeout_clk =
+ DIV_ROUND_UP(host->ops->get_timeout_clock(host),
+ 1000);
+ }
+
+ if (override_timeout_clk)
+ host->timeout_clk = override_timeout_clk;
+
+ mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
+ host->ops->get_max_timeout_count(host) : 1 << 27;
+ mmc->max_busy_timeout /= host->timeout_clk;
+ }
+
+ if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
+ !host->ops->get_max_timeout_count)
+ mmc->max_busy_timeout = 0;
+
+ mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
+ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
+
+ if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ host->flags |= SDHCI_AUTO_CMD12;
+
+ /*
+ * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
+ * For v4 mode, SDMA may use Auto-CMD23 as well.
+ */
+ if ((host->version >= SDHCI_SPEC_300) &&
+ ((host->flags & SDHCI_USE_ADMA) ||
+ !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
+ !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
+ host->flags |= SDHCI_AUTO_CMD23;
+ DBG("Auto-CMD23 available\n");
+ } else {
+ DBG("Auto-CMD23 unavailable\n");
+ }
+
+ /*
+ * A controller may support 8-bit width, but the board itself
+ * might not have the pins brought out. Boards that support
+ * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
+ * their platform code before calling sdhci_add_host(), and we
+ * won't assume 8-bit width for hosts without that CAP.
+ */
+ if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+ if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
+ mmc->caps &= ~MMC_CAP_CMD23;
+
+ if (host->caps & SDHCI_CAN_DO_HISPD)
+ mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
+ mmc_card_is_removable(mmc) &&
+ mmc_gpio_get_cd(mmc) < 0)
+ mmc->caps |= MMC_CAP_NEEDS_POLL;
+
+ if (!IS_ERR(mmc->supply.vqmmc)) {
+ if (enable_vqmmc) {
+ ret = regulator_enable(mmc->supply.vqmmc);
+ host->sdhci_core_to_disable_vqmmc = !ret;
+ }
+
+ /* If vqmmc provides no 1.8V signalling, then there's no UHS */
+ if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
+ 1950000))
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
+ SDHCI_SUPPORT_SDR50 |
+ SDHCI_SUPPORT_DDR50);
+
+ /* In eMMC case vqmmc might be a fixed 1.8V regulator */
+ if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
+ 3600000))
+ host->flags &= ~SDHCI_SIGNALING_330;
+
+ if (ret) {
+ pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
+ mmc_hostname(mmc), ret);
+ mmc->supply.vqmmc = ERR_PTR(-EINVAL);
+ }
+
+ }
+
+ if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
+ host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+ SDHCI_SUPPORT_DDR50);
+ /*
+ * The SDHCI controller in a SoC might support HS200/HS400
+ * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
+ * but if the board is modeled such that the IO lines are not
+ * connected to 1.8v then HS200/HS400 cannot be supported.
+ * Disable HS200/HS400 if the board does not have 1.8v connected
+ * to the IO lines. (Applicable for other modes in 1.8v)
+ */
+ mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
+ mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
+ }
+
+ /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
+ if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+ SDHCI_SUPPORT_DDR50))
+ mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+
+ /* SDR104 supports also implies SDR50 support */
+ if (host->caps1 & SDHCI_SUPPORT_SDR104) {
+ mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+ /* SD3.0: SDR104 is supported so (for eMMC) the caps2
+ * field can be promoted to support HS200.
+ */
+ if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
+ mmc->caps2 |= MMC_CAP2_HS200;
+ } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
+ mmc->caps |= MMC_CAP_UHS_SDR50;
+ }
+
+ if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
+ (host->caps1 & SDHCI_SUPPORT_HS400))
+ mmc->caps2 |= MMC_CAP2_HS400;
+
+ if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
+ (IS_ERR(mmc->supply.vqmmc) ||
+ !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
+ 1300000)))
+ mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
+
+ if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
+ !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
+ mmc->caps |= MMC_CAP_UHS_DDR50;
+
+ /* Does the host need tuning for SDR50? */
+ if (host->caps1 & SDHCI_USE_SDR50_TUNING)
+ host->flags |= SDHCI_SDR50_NEEDS_TUNING;
+
+ /* Driver Type(s) (A, C, D) supported by the host */
+ if (host->caps1 & SDHCI_DRIVER_TYPE_A)
+ mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
+ if (host->caps1 & SDHCI_DRIVER_TYPE_C)
+ mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
+ if (host->caps1 & SDHCI_DRIVER_TYPE_D)
+ mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
+
+ /* Initial value for re-tuning timer count */
+ host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
+ host->caps1);
+
+ /*
+ * In case Re-tuning Timer is not disabled, the actual value of
+ * re-tuning timer will be 2 ^ (n - 1).
+ */
+ if (host->tuning_count)
+ host->tuning_count = 1 << (host->tuning_count - 1);
+
+ /* Re-tuning mode supported by the Host Controller */
+ host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
+
+ ocr_avail = 0;
+
+ /*
+ * According to SD Host Controller spec v3.00, if the Host System
+ * can afford more than 150mA, Host Driver should set XPC to 1. Also
+ * the value is meaningful only if Voltage Support in the Capabilities
+ * register is set. The actual current value is 4 times the register
+ * value.
+ */
+ max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
+ if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
+ int curr = regulator_get_current_limit(mmc->supply.vmmc);
+ if (curr > 0) {
+
+ /* convert to SDHCI_MAX_CURRENT format */
+ curr = curr/1000; /* convert to mA */
+ curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
+
+ curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
+ max_current_caps =
+ FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
+ FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
+ FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
+ }
+ }
+
+ if (host->caps & SDHCI_CAN_VDD_330) {
+ ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
+ max_current_caps) *
+ SDHCI_MAX_CURRENT_MULTIPLIER;
+ }
+ if (host->caps & SDHCI_CAN_VDD_300) {
+ ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
+
+ mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
+ max_current_caps) *
+ SDHCI_MAX_CURRENT_MULTIPLIER;
+ }
+ if (host->caps & SDHCI_CAN_VDD_180) {
+ ocr_avail |= MMC_VDD_165_195;
+
+ mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
+ max_current_caps) *
+ SDHCI_MAX_CURRENT_MULTIPLIER;
+ }
+
+ /* If OCR set by host, use it instead. */
+ if (host->ocr_mask)
+ ocr_avail = host->ocr_mask;
+
+ /* If OCR set by external regulators, give it highest prio. */
+ if (mmc->ocr_avail)
+ ocr_avail = mmc->ocr_avail;
+
+ mmc->ocr_avail = ocr_avail;
+ mmc->ocr_avail_sdio = ocr_avail;
+ if (host->ocr_avail_sdio)
+ mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
+ mmc->ocr_avail_sd = ocr_avail;
+ if (host->ocr_avail_sd)
+ mmc->ocr_avail_sd &= host->ocr_avail_sd;
+ else /* normal SD controllers don't support 1.8V */
+ mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
+ mmc->ocr_avail_mmc = ocr_avail;
+ if (host->ocr_avail_mmc)
+ mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
+
+ if (mmc->ocr_avail == 0) {
+ pr_err("%s: Hardware doesn't report any support voltages.\n",
+ mmc_hostname(mmc));
+ ret = -ENODEV;
+ goto unreg;
+ }
+
+ if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
+ MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
+ (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
+ host->flags |= SDHCI_SIGNALING_180;
+
+ if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
+ host->flags |= SDHCI_SIGNALING_120;
+
+ spin_lock_init(&host->lock);
+
+ /*
+ * Maximum number of sectors in one transfer. Limited by SDMA boundary
+ * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
+ * is less anyway.
+ */
+ mmc->max_req_size = 524288;
+
+ /*
+ * Maximum number of segments. Depends on if the hardware
+ * can do scatter/gather or not.
+ */
+ if (host->flags & SDHCI_USE_ADMA) {
+ mmc->max_segs = SDHCI_MAX_SEGS;
+ } else if (host->flags & SDHCI_USE_SDMA) {
+ mmc->max_segs = 1;
+ mmc->max_req_size = min_t(size_t, mmc->max_req_size,
+ dma_max_mapping_size(mmc_dev(mmc)));
+ } else { /* PIO */
+ mmc->max_segs = SDHCI_MAX_SEGS;
+ }
+
+ /*
+ * Maximum segment size. Could be one segment with the maximum number
+ * of bytes. When doing hardware scatter/gather, each entry cannot
+ * be larger than 64 KiB though.
+ */
+ if (host->flags & SDHCI_USE_ADMA) {
+ if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
+ host->max_adma = 65532; /* 32-bit alignment */
+ mmc->max_seg_size = 65535;
+ } else {
+ mmc->max_seg_size = 65536;
+ }
+ } else {
+ mmc->max_seg_size = mmc->max_req_size;
+ }
+
+ /*
+ * Maximum block size. This varies from controller to controller and
+ * is specified in the capabilities register.
+ */
+ if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
+ mmc->max_blk_size = 2;
+ } else {
+ mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
+ SDHCI_MAX_BLOCK_SHIFT;
+ if (mmc->max_blk_size >= 3) {
+ pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
+ mmc_hostname(mmc));
+ mmc->max_blk_size = 0;
+ }
+ }
+
+ mmc->max_blk_size = 512 << mmc->max_blk_size;
+
+ /*
+ * Maximum block count.
+ */
+ mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
+
+ if (mmc->max_segs == 1)
+ /* This may alter mmc->*_blk_* parameters */
+ sdhci_allocate_bounce_buffer(host);
+
+ return 0;
+
+unreg:
+ if (host->sdhci_core_to_disable_vqmmc)
+ regulator_disable(mmc->supply.vqmmc);
+undma:
+ if (host->align_buffer)
+ dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
+ host->adma_table_sz, host->align_buffer,
+ host->align_addr);
+ host->adma_table = NULL;
+ host->align_buffer = NULL;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_setup_host);
+
+void sdhci_cleanup_host(struct sdhci_host *host)
+{
+ struct mmc_host *mmc = host->mmc;
+
+ if (host->sdhci_core_to_disable_vqmmc)
+ regulator_disable(mmc->supply.vqmmc);
+
+ if (host->align_buffer)
+ dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
+ host->adma_table_sz, host->align_buffer,
+ host->align_addr);
+
+ if (host->use_external_dma)
+ sdhci_external_dma_release(host);
+
+ host->adma_table = NULL;
+ host->align_buffer = NULL;
+}
+EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
+
+int __sdhci_add_host(struct sdhci_host *host)
+{
+ unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
+ struct mmc_host *mmc = host->mmc;
+ int ret;
+
+ if ((mmc->caps2 & MMC_CAP2_CQE) &&
+ (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
+ mmc->caps2 &= ~MMC_CAP2_CQE;
+ mmc->cqe_ops = NULL;
+ }
+
+ host->complete_wq = alloc_workqueue("sdhci", flags, 0);
+ if (!host->complete_wq)
+ return -ENOMEM;
+
+ INIT_WORK(&host->complete_work, sdhci_complete_work);
+
+ timer_setup(&host->timer, sdhci_timeout_timer, 0);
+ timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
+
+ init_waitqueue_head(&host->buf_ready_int);
+
+ sdhci_init(host, 0);
+
+ ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
+ IRQF_SHARED, mmc_hostname(mmc), host);
+ if (ret) {
+ pr_err("%s: Failed to request IRQ %d: %d\n",
+ mmc_hostname(mmc), host->irq, ret);
+ goto unwq;
+ }
+
+ ret = sdhci_led_register(host);
+ if (ret) {
+ pr_err("%s: Failed to register LED device: %d\n",
+ mmc_hostname(mmc), ret);
+ goto unirq;
+ }
+
+ ret = mmc_add_host(mmc);
+ if (ret)
+ goto unled;
+
+ pr_info("%s: SDHCI controller on %s [%s] using %s\n",
+ mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
+ host->use_external_dma ? "External DMA" :
+ (host->flags & SDHCI_USE_ADMA) ?
+ (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
+ (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
+
+ sdhci_enable_card_detection(host);
+
+ return 0;
+
+unled:
+ sdhci_led_unregister(host);
+unirq:
+ sdhci_reset_for_all(host);
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+unwq:
+ destroy_workqueue(host->complete_wq);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(__sdhci_add_host);
+
+int sdhci_add_host(struct sdhci_host *host)
+{
+ int ret;
+
+ ret = sdhci_setup_host(host);
+ if (ret)
+ return ret;
+
+ ret = __sdhci_add_host(host);
+ if (ret)
+ goto cleanup;
+
+ return 0;
+
+cleanup:
+ sdhci_cleanup_host(host);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_add_host);
+
+void sdhci_remove_host(struct sdhci_host *host, int dead)
+{
+ struct mmc_host *mmc = host->mmc;
+ unsigned long flags;
+
+ if (dead) {
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->flags |= SDHCI_DEVICE_DEAD;
+
+ if (sdhci_has_requests(host)) {
+ pr_err("%s: Controller removed during "
+ " transfer!\n", mmc_hostname(mmc));
+ sdhci_error_out_mrqs(host, -ENOMEDIUM);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ sdhci_disable_card_detection(host);
+
+ mmc_remove_host(mmc);
+
+ sdhci_led_unregister(host);
+
+ if (!dead)
+ sdhci_reset_for_all(host);
+
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+
+ del_timer_sync(&host->timer);
+ del_timer_sync(&host->data_timer);
+
+ destroy_workqueue(host->complete_wq);
+
+ if (host->sdhci_core_to_disable_vqmmc)
+ regulator_disable(mmc->supply.vqmmc);
+
+ if (host->align_buffer)
+ dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
+ host->adma_table_sz, host->align_buffer,
+ host->align_addr);
+
+ if (host->use_external_dma)
+ sdhci_external_dma_release(host);
+
+ host->adma_table = NULL;
+ host->align_buffer = NULL;
+}
+
+EXPORT_SYMBOL_GPL(sdhci_remove_host);
+
+void sdhci_free_host(struct sdhci_host *host)
+{
+ mmc_free_host(host->mmc);
+}
+
+EXPORT_SYMBOL_GPL(sdhci_free_host);
+
+/*****************************************************************************\
+ * *
+ * Driver init/exit *
+ * *
+\*****************************************************************************/
+
+static int __init sdhci_drv_init(void)
+{
+ pr_info(DRIVER_NAME
+ ": Secure Digital Host Controller Interface driver\n");
+ pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
+
+ return 0;
+}
+
+static void __exit sdhci_drv_exit(void)
+{
+}
+
+module_init(sdhci_drv_init);
+module_exit(sdhci_drv_exit);
+
+module_param(debug_quirks, uint, 0444);
+module_param(debug_quirks2, uint, 0444);
+
+MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
+MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
+MODULE_LICENSE("GPL");
+
+MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
+MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Radix cross Linux
The main Radix cross Linux repository contains the build scripts of packages, which have the most complete and common functionality for desktop machines
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